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AMDGPU: Replace ptr undef in tests with poison
1 parent 5662582 commit 6b657b1

31 files changed

+111
-111
lines changed

‎llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -58,7 +58,7 @@ define amdgpu_ps void @raw_buffer_atomic_add_rtn_f64(<4 x i32> inreg %rsrc, doub
5858
; GFX942-NEXT: s_endpgm
5959
main_body:
6060
%ret = call double @llvm.amdgcn.raw.buffer.atomic.fadd.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
61-
store double %ret, ptr undef
61+
store double %ret, ptr poison
6262
ret void
6363
}
6464

@@ -141,7 +141,7 @@ define amdgpu_ps void @raw_ptr_buffer_atomic_add_rtn_f64(ptr addrspace(8) inreg
141141
; GFX942-NEXT: s_endpgm
142142
main_body:
143143
%ret = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
144-
store double %ret, ptr undef
144+
store double %ret, ptr poison
145145
ret void
146146
}
147147

@@ -224,7 +224,7 @@ define amdgpu_ps void @struct_buffer_atomic_add_rtn_f64(<4 x i32> inreg %rsrc, d
224224
; GFX942-NEXT: s_endpgm
225225
main_body:
226226
%ret = call double @llvm.amdgcn.struct.buffer.atomic.fadd.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
227-
store double %ret, ptr undef
227+
store double %ret, ptr poison
228228
ret void
229229
}
230230

@@ -307,7 +307,7 @@ define amdgpu_ps void @struct_ptr_buffer_atomic_add_rtn_f64(ptr addrspace(8) inr
307307
; GFX942-NEXT: s_endpgm
308308
main_body:
309309
%ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fadd.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
310-
store double %ret, ptr undef
310+
store double %ret, ptr poison
311311
ret void
312312
}
313313

@@ -390,7 +390,7 @@ define amdgpu_ps void @raw_buffer_atomic_min_rtn_f64(<4 x i32> inreg %rsrc, doub
390390
; GFX942-NEXT: s_endpgm
391391
main_body:
392392
%ret = call double @llvm.amdgcn.raw.buffer.atomic.fmin.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
393-
store double %ret, ptr undef
393+
store double %ret, ptr poison
394394
ret void
395395
}
396396

@@ -473,7 +473,7 @@ define amdgpu_ps void @raw_ptr_buffer_atomic_min_rtn_f64(ptr addrspace(8) inreg
473473
; GFX942-NEXT: s_endpgm
474474
main_body:
475475
%ret = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fmin.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
476-
store double %ret, ptr undef
476+
store double %ret, ptr poison
477477
ret void
478478
}
479479

@@ -556,7 +556,7 @@ define amdgpu_ps void @struct_buffer_atomic_min_rtn_f64(<4 x i32> inreg %rsrc, d
556556
; GFX942-NEXT: s_endpgm
557557
main_body:
558558
%ret = call double @llvm.amdgcn.struct.buffer.atomic.fmin.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
559-
store double %ret, ptr undef
559+
store double %ret, ptr poison
560560
ret void
561561
}
562562

@@ -639,7 +639,7 @@ define amdgpu_ps void @struct_ptr_buffer_atomic_min_rtn_f64(ptr addrspace(8) inr
639639
; GFX942-NEXT: s_endpgm
640640
main_body:
641641
%ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
642-
store double %ret, ptr undef
642+
store double %ret, ptr poison
643643
ret void
644644
}
645645

@@ -722,7 +722,7 @@ define amdgpu_ps void @raw_buffer_atomic_max_rtn_f64(<4 x i32> inreg %rsrc, doub
722722
; GFX942-NEXT: s_endpgm
723723
main_body:
724724
%ret = call double @llvm.amdgcn.raw.buffer.atomic.fmax.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
725-
store double %ret, ptr undef
725+
store double %ret, ptr poison
726726
ret void
727727
}
728728

@@ -805,7 +805,7 @@ define amdgpu_ps void @raw_ptr_buffer_atomic_max_rtn_f64(ptr addrspace(8) inreg
805805
; GFX942-NEXT: s_endpgm
806806
main_body:
807807
%ret = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fmax.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
808-
store double %ret, ptr undef
808+
store double %ret, ptr poison
809809
ret void
810810
}
811811

@@ -888,7 +888,7 @@ define amdgpu_ps void @struct_buffer_atomic_max_rtn_f64(<4 x i32> inreg %rsrc, d
888888
; GFX942-NEXT: s_endpgm
889889
main_body:
890890
%ret = call double @llvm.amdgcn.struct.buffer.atomic.fmax.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
891-
store double %ret, ptr undef
891+
store double %ret, ptr poison
892892
ret void
893893
}
894894

@@ -971,7 +971,7 @@ define amdgpu_ps void @struct_ptr_buffer_atomic_max_rtn_f64(ptr addrspace(8) inr
971971
; GFX942-NEXT: s_endpgm
972972
main_body:
973973
%ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
974-
store double %ret, ptr undef
974+
store double %ret, ptr poison
975975
ret void
976976
}
977977

‎llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -735,7 +735,7 @@ define amdgpu_kernel void @image_bvh_intersect_ray_nsa_reassign(ptr %p_node_ptr,
735735
%ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float 7.0, i32 1
736736
%ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float 8.0, i32 2
737737
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f32(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
738-
store <4 x i32> %v, ptr undef
738+
store <4 x i32> %v, ptr poison
739739
ret void
740740
}
741741

@@ -839,7 +839,7 @@ define amdgpu_kernel void @image_bvh_intersect_ray_a16_nsa_reassign(ptr %p_node_
839839
%ray_inv_dir1 = insertelement <3 x half> %ray_inv_dir0, half 7.0, i32 1
840840
%ray_inv_dir = insertelement <3 x half> %ray_inv_dir1, half 8.0, i32 2
841841
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i32.v4f16(i32 %node_ptr, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr)
842-
store <4 x i32> %v, ptr undef
842+
store <4 x i32> %v, ptr poison
843843
ret void
844844
}
845845

@@ -921,7 +921,7 @@ define amdgpu_kernel void @image_bvh64_intersect_ray_nsa_reassign(ptr %p_ray, <4
921921
%ray_inv_dir1 = insertelement <3 x float> %ray_inv_dir0, float 7.0, i32 1
922922
%ray_inv_dir = insertelement <3 x float> %ray_inv_dir1, float 8.0, i32 2
923923
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f32(i64 1111111111111, float %ray_extent, <3 x float> %ray_origin, <3 x float> %ray_dir, <3 x float> %ray_inv_dir, <4 x i32> %tdescr)
924-
store <4 x i32> %v, ptr undef
924+
store <4 x i32> %v, ptr poison
925925
ret void
926926
}
927927

@@ -995,6 +995,6 @@ define amdgpu_kernel void @image_bvh64_intersect_ray_a16_nsa_reassign(ptr %p_ray
995995
%ray_inv_dir1 = insertelement <3 x half> %ray_inv_dir0, half 7.0, i32 1
996996
%ray_inv_dir = insertelement <3 x half> %ray_inv_dir1, half 8.0, i32 2
997997
%v = call <4 x i32> @llvm.amdgcn.image.bvh.intersect.ray.i64.v4f16(i64 1111111111110, float %ray_extent, <3 x float> %ray_origin, <3 x half> %ray_dir, <3 x half> %ray_inv_dir, <4 x i32> %tdescr)
998-
store <4 x i32> %v, ptr undef
998+
store <4 x i32> %v, ptr poison
999999
ret void
10001000
}

‎llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@ declare <2 x half> @llvm.amdgcn.raw.buffer.atomic.fadd.v2f16(<2 x half>, <4 x i3
1111
define amdgpu_kernel void @buffer_atomic_add_f32_rtn(float %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 %soffset) {
1212
main_body:
1313
%ret = call float @llvm.amdgcn.raw.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
14-
store float %ret, ptr undef
14+
store float %ret, ptr poison
1515
ret void
1616
}
1717

@@ -20,6 +20,6 @@ main_body:
2020
define amdgpu_kernel void @buffer_atomic_add_v2f16_rtn(<2 x half> %val, <4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
2121
main_body:
2222
%ret = call <2 x half> @llvm.amdgcn.raw.buffer.atomic.fadd.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
23-
store <2 x half> %ret, ptr undef
23+
store <2 x half> %ret, ptr poison
2424
ret void
2525
}

‎llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@ declare <2 x half> @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2f16(<2 x half>, ptr
1111
define amdgpu_kernel void @buffer_atomic_add_f32_rtn(float %val, ptr addrspace(8) inreg %rsrc, i32 %voffset, i32 %soffset) {
1212
main_body:
1313
%ret = call float @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.f32(float %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 0)
14-
store float %ret, ptr undef
14+
store float %ret, ptr poison
1515
ret void
1616
}
1717

@@ -20,6 +20,6 @@ main_body:
2020
define amdgpu_kernel void @buffer_atomic_add_v2f16_rtn(<2 x half> %val, ptr addrspace(8) inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
2121
main_body:
2222
%ret = call <2 x half> @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.v2f16(<2 x half> %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 0)
23-
store <2 x half> %ret, ptr undef
23+
store <2 x half> %ret, ptr poison
2424
ret void
2525
}

‎llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@ declare <2 x half> @llvm.amdgcn.struct.buffer.atomic.fadd.v2f16(<2 x half>, <4 x
1212
define amdgpu_kernel void @buffer_atomic_add_f32_rtn(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset) {
1313
main_body:
1414
%ret = call float @llvm.amdgcn.struct.buffer.atomic.fadd.f32(float %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
15-
store float %ret, ptr undef
15+
store float %ret, ptr poison
1616
ret void
1717
}
1818

@@ -21,6 +21,6 @@ main_body:
2121
define amdgpu_kernel void @buffer_atomic_add_v2f16_rtn(<2 x half> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset) {
2222
main_body:
2323
%ret = call <2 x half> @llvm.amdgcn.struct.buffer.atomic.fadd.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
24-
store <2 x half> %ret, ptr undef
24+
store <2 x half> %ret, ptr poison
2525
ret void
2626
}

‎llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@ declare <2 x half> @llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2f16(<2 x half>,
1212
define amdgpu_kernel void @buffer_atomic_add_f32_rtn(float %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset) {
1313
main_body:
1414
%ret = call float @llvm.amdgcn.struct.ptr.buffer.atomic.fadd.f32(float %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
15-
store float %ret, ptr undef
15+
store float %ret, ptr poison
1616
ret void
1717
}
1818

@@ -21,6 +21,6 @@ main_body:
2121
define amdgpu_kernel void @buffer_atomic_add_v2f16_rtn(<2 x half> %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset) {
2222
main_body:
2323
%ret = call <2 x half> @llvm.amdgcn.struct.ptr.buffer.atomic.fadd.v2f16(<2 x half> %val, ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
24-
store <2 x half> %ret, ptr undef
24+
store <2 x half> %ret, ptr poison
2525
ret void
2626
}

‎llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -105,7 +105,7 @@ define amdgpu_kernel void @s_trig_preop_f64(double %a, i32 %b) {
105105
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
106106
; GFX11-NEXT: s_endpgm
107107
%result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 %b)
108-
store volatile double %result, ptr undef
108+
store volatile double %result, ptr poison
109109
ret void
110110
}
111111

@@ -167,7 +167,7 @@ define amdgpu_kernel void @s_trig_preop_f64_imm(double %a, i32 %b) {
167167
; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
168168
; GFX11-NEXT: s_endpgm
169169
%result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 7)
170-
store volatile double %result, ptr undef
170+
store volatile double %result, ptr poison
171171
ret void
172172
}
173173

‎llvm/test/CodeGen/AMDGPU/addrspacecast.r600.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -70,7 +70,7 @@ define amdgpu_kernel void @addrspacecast_flat_undef_to_local(ptr addrspace(1) %o
7070
; CHECK: ; %bb.0:
7171
; CHECK-NEXT: CF_END
7272
; CHECK-NEXT: PAD
73-
store ptr addrspace(3) addrspacecast (ptr undef to ptr addrspace(3)), ptr addrspace(1) %out
73+
store ptr addrspace(3) addrspacecast (ptr poison to ptr addrspace(3)), ptr addrspace(1) %out
7474
ret void
7575
}
7676

‎llvm/test/CodeGen/AMDGPU/amdgpu-alias-analysis.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -176,7 +176,7 @@ define void @test_7_7(ptr addrspace(7) %p, ptr addrspace(7) %p1) {
176176
ret void
177177
}
178178

179-
@cst = internal addrspace(4) global ptr undef, align 4
179+
@cst = internal addrspace(4) global ptr poison, align 4
180180

181181
; CHECK-LABEL: Function: test_8_0
182182
; CHECK-DAG: NoAlias: i8 addrspace(3)* %p, i8* %p1

‎llvm/test/CodeGen/AMDGPU/amdgpu-inline.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -162,7 +162,7 @@ entry:
162162
br label %bb.1
163163

164164
bb.1:
165-
store float 1.0, ptr undef
165+
store float 1.0, ptr poison
166166
br label %bb.2
167167

168168
bb.2:

‎llvm/test/CodeGen/AMDGPU/attr-amdgpu-num-sgpr.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -68,7 +68,7 @@ define amdgpu_kernel void @max_10_sgprs() #0 {
6868
; %x.3 = call i64 @llvm.amdgcn.dispatch.id()
6969
; %x.4 = call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()
7070
; %x.5 = call ptr addrspace(4) @llvm.amdgcn.queue.ptr()
71-
; store volatile i32 0, ptr undef
71+
; store volatile i32 0, ptr poison
7272
; br label %stores
7373
;
7474
;stores:
@@ -99,7 +99,7 @@ define amdgpu_kernel void @max_10_sgprs() #0 {
9999
; ptr addrspace(1) %out3,
100100
; ptr addrspace(1) %out4,
101101
; i32 %one, i32 %two, i32 %three, i32 %four) #2 {
102-
; store volatile i32 0, ptr undef
102+
; store volatile i32 0, ptr poison
103103
; %x.0 = call i32 @llvm.amdgcn.workgroup.id.x()
104104
; store volatile i32 %x.0, ptr addrspace(1) poison
105105
; %x.1 = call i32 @llvm.amdgcn.workgroup.id.y()

‎llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@ define amdgpu_kernel void @eq_t(float %x) {
1414
%s1 = select i1 %c1, i32 56789, i32 1
1515
%c2 = icmp eq i32 %s1, 56789
1616
%s2 = select i1 %c2, float 4.0, float 2.0
17-
store float %s2, ptr undef, align 4
17+
store float %s2, ptr poison, align 4
1818
ret void
1919
}
2020

@@ -31,7 +31,7 @@ define amdgpu_kernel void @ne_t(float %x) {
3131
%s1 = select i1 %c1, i32 56789, i32 1
3232
%c2 = icmp ne i32 %s1, 56789
3333
%s2 = select i1 %c2, float 4.0, float 2.0
34-
store float %s2, ptr undef, align 4
34+
store float %s2, ptr poison, align 4
3535
ret void
3636
}
3737

@@ -48,7 +48,7 @@ define amdgpu_kernel void @eq_f(float %x) {
4848
%s1 = select i1 %c1, i32 1, i32 56789
4949
%c2 = icmp eq i32 %s1, 56789
5050
%s2 = select i1 %c2, float 4.0, float 2.0
51-
store float %s2, ptr undef, align 4
51+
store float %s2, ptr poison, align 4
5252
ret void
5353
}
5454

@@ -65,7 +65,7 @@ define amdgpu_kernel void @ne_f(float %x) {
6565
%s1 = select i1 %c1, i32 1, i32 56789
6666
%c2 = icmp ne i32 %s1, 56789
6767
%s2 = select i1 %c2, float 4.0, float 2.0
68-
store float %s2, ptr undef, align 4
68+
store float %s2, ptr poison, align 4
6969
ret void
7070
}
7171

@@ -79,6 +79,6 @@ define amdgpu_kernel void @different_constants(float %x) {
7979
%s1 = select i1 %c1, i32 56789, i32 1
8080
%c2 = icmp eq i32 %s1, 5678
8181
%s2 = select i1 %c2, float 4.0, float 2.0
82-
store float %s2, ptr undef, align 4
82+
store float %s2, ptr poison, align 4
8383
ret void
8484
}

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