@@ -1282,3 +1282,36 @@ define i32 @zext_load_i32_by_i8_bswap_shl_16(ptr %arg) {
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%tmp8 = or i32 %tmp7 , %tmp30
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ret i32 %tmp8
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}
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+
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+ ; FIXME: This is a miscompile.
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+ define i32 @pr80911_vector_load_multiuse (ptr %ptr , ptr %clobber ) nounwind {
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+ ; CHECK-LABEL: pr80911_vector_load_multiuse:
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+ ; CHECK: # %bb.0:
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+ ; CHECK-NEXT: pushl %esi
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+ ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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+ ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %edx
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+ ; CHECK-NEXT: movl (%edx), %esi
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+ ; CHECK-NEXT: movzwl (%edx), %eax
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+ ; CHECK-NEXT: movl $0, (%ecx)
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+ ; CHECK-NEXT: movl %esi, (%edx)
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+ ; CHECK-NEXT: popl %esi
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+ ; CHECK-NEXT: retl
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+ ;
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+ ; CHECK64-LABEL: pr80911_vector_load_multiuse:
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+ ; CHECK64: # %bb.0:
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+ ; CHECK64-NEXT: movzwl (%rdi), %eax
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+ ; CHECK64-NEXT: movl $0, (%rsi)
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+ ; CHECK64-NEXT: movl (%rdi), %ecx
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+ ; CHECK64-NEXT: movl %ecx, (%rdi)
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+ ; CHECK64-NEXT: retq
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+ %load = load <4 x i8 >, ptr %ptr , align 16
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+ store i32 0 , ptr %clobber
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+ store <4 x i8 > %load , ptr %ptr , align 16
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+ %e1 = extractelement <4 x i8 > %load , i64 1
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+ %e1.ext = zext i8 %e1 to i32
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+ %e1.ext.shift = shl nuw nsw i32 %e1.ext , 8
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+ %e0 = extractelement <4 x i8 > %load , i64 0
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+ %e0.ext = zext i8 %e0 to i32
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+ %res = or i32 %e1.ext.shift , %e0.ext
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+ ret i32 %res
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+ }
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