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farzonlfarzonl
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remove target specific changes
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-192
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4 files changed

+1
-192
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‎llvm/lib/CodeGen/TargetLoweringBase.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -961,7 +961,7 @@ void TargetLoweringBase::initActions() {
961961
setOperationAction(
962962
{ISD::FCOPYSIGN, ISD::SIGN_EXTEND_INREG, ISD::ANY_EXTEND_VECTOR_INREG,
963963
ISD::SIGN_EXTEND_VECTOR_INREG, ISD::ZERO_EXTEND_VECTOR_INREG,
964-
ISD::SPLAT_VECTOR, ISD::LRINT, ISD::LLRINT, ISD::FTAN},
964+
ISD::SPLAT_VECTOR, ISD::LRINT, ISD::LLRINT},
965965
VT, Expand);
966966

967967
// Constrained floating-point operations default to expand.
@@ -1020,7 +1020,6 @@ void TargetLoweringBase::initActions() {
10201020
ISD::FTAN},
10211021
{MVT::f32, MVT::f64, MVT::f128}, Expand);
10221022

1023-
setOperationAction(ISD::FTAN, MVT::f16, Promote);
10241023
// Default ISD::TRAP to expand (which turns it into abort).
10251024
setOperationAction(ISD::TRAP, MVT::Other, Expand);
10261025

‎llvm/test/CodeGen/RISCV/half-intrinsics.ll

Lines changed: 0 additions & 120 deletions
Original file line numberDiff line numberDiff line change
@@ -2862,123 +2862,3 @@ define i1 @isnan_d_fpclass(half %x) {
28622862
%1 = call i1 @llvm.is.fpclass.f16(half %x, i32 3) ; nan
28632863
ret i1 %1
28642864
}
2865-
2866-
declare half @llvm.tan.f16(half)
2867-
2868-
define half @tan_f16(half %a) nounwind {
2869-
; RV32IZFH-LABEL: tan_f16:
2870-
; RV32IZFH: # %bb.0:
2871-
; RV32IZFH-NEXT: addi sp, sp, -16
2872-
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2873-
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
2874-
; RV32IZFH-NEXT: call tanf
2875-
; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
2876-
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2877-
; RV32IZFH-NEXT: addi sp, sp, 16
2878-
; RV32IZFH-NEXT: ret
2879-
;
2880-
; RV64IZFH-LABEL: tan_f16:
2881-
; RV64IZFH: # %bb.0:
2882-
; RV64IZFH-NEXT: addi sp, sp, -16
2883-
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
2884-
; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
2885-
; RV64IZFH-NEXT: call tanf
2886-
; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
2887-
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
2888-
; RV64IZFH-NEXT: addi sp, sp, 16
2889-
; RV64IZFH-NEXT: ret
2890-
;
2891-
; RV32IZHINX-LABEL: tan_f16:
2892-
; RV32IZHINX: # %bb.0:
2893-
; RV32IZHINX-NEXT: addi sp, sp, -16
2894-
; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2895-
; RV32IZHINX-NEXT: fcvt.s.h a0, a0
2896-
; RV32IZHINX-NEXT: call tanf
2897-
; RV32IZHINX-NEXT: fcvt.h.s a0, a0
2898-
; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2899-
; RV32IZHINX-NEXT: addi sp, sp, 16
2900-
; RV32IZHINX-NEXT: ret
2901-
;
2902-
; RV64IZHINX-LABEL: tan_f16:
2903-
; RV64IZHINX: # %bb.0:
2904-
; RV64IZHINX-NEXT: addi sp, sp, -16
2905-
; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
2906-
; RV64IZHINX-NEXT: fcvt.s.h a0, a0
2907-
; RV64IZHINX-NEXT: call tanf
2908-
; RV64IZHINX-NEXT: fcvt.h.s a0, a0
2909-
; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
2910-
; RV64IZHINX-NEXT: addi sp, sp, 16
2911-
; RV64IZHINX-NEXT: ret
2912-
;
2913-
; RV32I-LABEL: tan_f16:
2914-
; RV32I: # %bb.0:
2915-
; RV32I-NEXT: addi sp, sp, -16
2916-
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2917-
; RV32I-NEXT: slli a0, a0, 16
2918-
; RV32I-NEXT: srli a0, a0, 16
2919-
; RV32I-NEXT: call __extendhfsf2
2920-
; RV32I-NEXT: call tanf
2921-
; RV32I-NEXT: call __truncsfhf2
2922-
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2923-
; RV32I-NEXT: addi sp, sp, 16
2924-
; RV32I-NEXT: ret
2925-
;
2926-
; RV64I-LABEL: tan_f16:
2927-
; RV64I: # %bb.0:
2928-
; RV64I-NEXT: addi sp, sp, -16
2929-
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
2930-
; RV64I-NEXT: slli a0, a0, 48
2931-
; RV64I-NEXT: srli a0, a0, 48
2932-
; RV64I-NEXT: call __extendhfsf2
2933-
; RV64I-NEXT: call tanf
2934-
; RV64I-NEXT: call __truncsfhf2
2935-
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
2936-
; RV64I-NEXT: addi sp, sp, 16
2937-
; RV64I-NEXT: ret
2938-
;
2939-
; RV32IZFHMIN-LABEL: tan_f16:
2940-
; RV32IZFHMIN: # %bb.0:
2941-
; RV32IZFHMIN-NEXT: addi sp, sp, -16
2942-
; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2943-
; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0
2944-
; RV32IZFHMIN-NEXT: call tanf
2945-
; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0
2946-
; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2947-
; RV32IZFHMIN-NEXT: addi sp, sp, 16
2948-
; RV32IZFHMIN-NEXT: ret
2949-
;
2950-
; RV64IZFHMIN-LABEL: tan_f16:
2951-
; RV64IZFHMIN: # %bb.0:
2952-
; RV64IZFHMIN-NEXT: addi sp, sp, -16
2953-
; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
2954-
; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0
2955-
; RV64IZFHMIN-NEXT: call tanf
2956-
; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0
2957-
; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
2958-
; RV64IZFHMIN-NEXT: addi sp, sp, 16
2959-
; RV64IZFHMIN-NEXT: ret
2960-
;
2961-
; RV32IZHINXMIN-LABEL: tan_f16:
2962-
; RV32IZHINXMIN: # %bb.0:
2963-
; RV32IZHINXMIN-NEXT: addi sp, sp, -16
2964-
; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2965-
; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
2966-
; RV32IZHINXMIN-NEXT: call tanf
2967-
; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
2968-
; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2969-
; RV32IZHINXMIN-NEXT: addi sp, sp, 16
2970-
; RV32IZHINXMIN-NEXT: ret
2971-
;
2972-
; RV64IZHINXMIN-LABEL: tan_f16:
2973-
; RV64IZHINXMIN: # %bb.0:
2974-
; RV64IZHINXMIN-NEXT: addi sp, sp, -16
2975-
; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
2976-
; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
2977-
; RV64IZHINXMIN-NEXT: call tanf
2978-
; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
2979-
; RV64IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
2980-
; RV64IZHINXMIN-NEXT: addi sp, sp, 16
2981-
; RV64IZHINXMIN-NEXT: ret
2982-
%1 = call half @llvm.tan.f16(half %a)
2983-
ret half %1
2984-
}

‎llvm/test/CodeGen/WebAssembly/simd-unsupported.ll

Lines changed: 0 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -377,14 +377,6 @@ define <4 x float> @cos_v4f32(<4 x float> %x) {
377377
ret <4 x float> %v
378378
}
379379

380-
; CHECK-LABEL: tan_v4f32:
381-
; CHECK: call $push[[L:[0-9]+]]=, tanf
382-
declare <4 x float> @llvm.tan.v4f32(<4 x float>)
383-
define <4 x float> @tan_v4f32(<4 x float> %x) {
384-
%v = call <4 x float> @llvm.tan.v4f32(<4 x float> %x)
385-
ret <4 x float> %v
386-
}
387-
388380
; CHECK-LABEL: powi_v4f32:
389381
; CHECK: call $push[[L:[0-9]+]]=, __powisf2
390382
declare <4 x float> @llvm.powi.v4f32.i32(<4 x float>, i32)
@@ -477,14 +469,6 @@ define <2 x double> @cos_v2f64(<2 x double> %x) {
477469
ret <2 x double> %v
478470
}
479471

480-
; CHECK-LABEL: tan_v2f64:
481-
; CHECK: call $push[[L:[0-9]+]]=, tan
482-
declare <2 x double> @llvm.tan.v2f64(<2 x double>)
483-
define <2 x double> @tan_v2f64(<2 x double> %x) {
484-
%v = call <2 x double> @llvm.tan.v2f64(<2 x double> %x)
485-
ret <2 x double> %v
486-
}
487-
488472
; CHECK-LABEL: powi_v2f64:
489473
; CHECK: call $push[[L:[0-9]+]]=, __powidf2
490474
declare <2 x double> @llvm.powi.v2f64.i32(<2 x double>, i32)

‎llvm/test/Transforms/LoopVectorize/intrinsic.ll

Lines changed: 0 additions & 54 deletions
Original file line numberDiff line numberDiff line change
@@ -162,60 +162,6 @@ for.end: ; preds = %for.body, %entry
162162

163163
declare double @llvm.cos.f64(double)
164164

165-
define void @tan_f32(i32 %n, ptr %y, ptr %x) {
166-
; CHECK-LABEL: @tan_f32(
167-
; CHECK: llvm.tan.v4f32
168-
; CHECK: ret void
169-
;
170-
entry:
171-
%cmp6 = icmp sgt i32 %n, 0
172-
br i1 %cmp6, label %for.body, label %for.end
173-
174-
for.body: ; preds = %entry, %for.body
175-
%indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
176-
%arrayidx = getelementptr inbounds float, ptr %y, i64 %indvars.iv
177-
%0 = load float, ptr %arrayidx, align 4
178-
%call = tail call float @llvm.tan.f32(float %0)
179-
%arrayidx2 = getelementptr inbounds float, ptr %x, i64 %indvars.iv
180-
store float %call, ptr %arrayidx2, align 4
181-
%indvars.iv.next = add i64 %indvars.iv, 1
182-
%lftr.wideiv = trunc i64 %indvars.iv.next to i32
183-
%exitcond = icmp eq i32 %lftr.wideiv, %n
184-
br i1 %exitcond, label %for.end, label %for.body
185-
186-
for.end: ; preds = %for.body, %entry
187-
ret void
188-
}
189-
190-
declare float @llvm.tan.f32(float)
191-
192-
define void @tan_f64(i32 %n, ptr %y, ptr %x) {
193-
; CHECK-LABEL: @tan_f64(
194-
; CHECK: llvm.tan.v4f64
195-
; CHECK: ret void
196-
;
197-
entry:
198-
%cmp6 = icmp sgt i32 %n, 0
199-
br i1 %cmp6, label %for.body, label %for.end
200-
201-
for.body: ; preds = %entry, %for.body
202-
%indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
203-
%arrayidx = getelementptr inbounds double, ptr %y, i64 %indvars.iv
204-
%0 = load double, ptr %arrayidx, align 8
205-
%call = tail call double @llvm.tan.f64(double %0)
206-
%arrayidx2 = getelementptr inbounds double, ptr %x, i64 %indvars.iv
207-
store double %call, ptr %arrayidx2, align 8
208-
%indvars.iv.next = add i64 %indvars.iv, 1
209-
%lftr.wideiv = trunc i64 %indvars.iv.next to i32
210-
%exitcond = icmp eq i32 %lftr.wideiv, %n
211-
br i1 %exitcond, label %for.end, label %for.body
212-
213-
for.end: ; preds = %for.body, %entry
214-
ret void
215-
}
216-
217-
declare double @llvm.tan.f64(double)
218-
219165
define void @exp_f32(i32 %n, ptr %y, ptr %x) {
220166
; CHECK-LABEL: @exp_f32(
221167
; CHECK: llvm.exp.v4f32

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