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SpencerAbsonSpencerAbson
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[LLVM][AArch64] Add assembly/disassembly for FTMOPA and BFTMOPA (#113230)
This patch adds assembly/disassembly for the following SME2p2 instructions (part of the 2024 AArch64 ISA update) - BFTMOPA (widening) - FEAT_SME2p2 - BFTMOPA (non-widening) - FEAT_SME2p2 & FEAT_SME_B16B16 - FTMOPA (4-way) - FEAT_SME2p2 & FEAT_SME_F8F32 - FTMOPA (2-way, 8-to-16) - FEAT_SME2p2 & FEAT_SME_F8F16 - FTMOPA (2-way, 16-to-32) - FEAT_SME2p2 - FTMOPA (non-widening, f16) - FEAT_SME2p2 & FEAT_SME_F16F16 - FTMOPA (non-widening, f32) - FEAT_SME2p2 - Add new ZPR_K register class and ZK register operand - Introduce assembler extension tests for the new sme2p2 feature In accordance with: https://developer.arm.com/documentation/ddi0602/latest/ Co-authored-by: Marian Lukac [email protected]
1 parent f18c3e4 commit 629d980

21 files changed

+673
-13
lines changed

‎llvm/lib/Target/AArch64/AArch64RegisterInfo.td

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1210,6 +1210,15 @@ def ZPRMul2AsmOp32_Hi : ZPRAsmOperand<"VectorS_Hi", 32, "Mul2_Hi">;
12101210
def ZPRMul2AsmOp64_Lo : ZPRAsmOperand<"VectorD_Lo", 64, "Mul2_Lo">;
12111211
def ZPRMul2AsmOp64_Hi : ZPRAsmOperand<"VectorD_Hi", 64, "Mul2_Hi">;
12121212

1213+
def ZPR_K : RegisterClass<"AArch64", [untyped], 128,
1214+
(add Z20, Z21, Z22, Z23, Z28, Z29, Z30, Z31)>;
1215+
1216+
def ZK : RegisterOperand<ZPR_K, "printSVERegOp<>">{
1217+
let EncoderMethod = "EncodeZK";
1218+
let DecoderMethod = "DecodeZK";
1219+
let ParserMatchClass = ZPRAsmOperand<"Vector_20to23or28to31", 0, "_K">;
1220+
}
1221+
12131222
def ZPR8Mul2_Lo : ZPRMul2_MinToMaxRegOp<"b", ZPRMul2AsmOp8_Lo, 0, 14, ElementSizeB, ZPRMul2_Lo>;
12141223
def ZPR8Mul2_Hi : ZPRMul2_MinToMaxRegOp<"b", ZPRMul2AsmOp8_Hi, 16, 30, ElementSizeB, ZPRMul2_Hi>;
12151224
def ZPR16Mul2_Lo : ZPRMul2_MinToMaxRegOp<"h", ZPRMul2AsmOp16_Lo, 0, 14, ElementSizeH, ZPRMul2_Lo>;

‎llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1000,3 +1000,24 @@ defm FMOPA_MPPZZ_BtoS : sme_outer_product_fp32<0b0, 0b01, ZPR8, "fmopa", null_fr
10001000

10011001
} //[HasSMEF8F32]
10021002

1003+
let Predicates = [HasSME2p2] in {
1004+
def FTMOPA_M2ZZZI_HtoS : sme_tmopa_32b<0b11000, ZZ_h_mul_r, ZPR16, "ftmopa">;
1005+
def FTMOPA_M2ZZZI_StoS : sme_tmopa_32b<0b00000, ZZ_s_mul_r, ZPR32, "ftmopa">;
1006+
def BFTMOPA_M2ZZZI_HtoS : sme_tmopa_32b<0b10000, ZZ_h_mul_r, ZPR16, "bftmopa">;
1007+
} // [HasSME2p2]
1008+
1009+
let Predicates = [HasSME2p2, HasSMEB16B16] in {
1010+
def BFTMOPA_M2ZZZI_HtoH : sme_tmopa_16b<0b11001, ZZ_h_mul_r, ZPR16, "bftmopa">;
1011+
} // [HasSME2p2, HasSMEB16B16]
1012+
1013+
let Predicates = [HasSME2p2, HasSMEF8F32], Uses = [FPMR, FPCR] in {
1014+
def FTMOPA_M2ZZZI_BtoS : sme_tmopa_32b<0b01000, ZZ_b_mul_r, ZPR8, "ftmopa">;
1015+
} // [HasSME2p2, HasSMEF8F32], Uses = [FPMR, FPCR]
1016+
1017+
let Predicates = [HasSME2p2, HasSMEF8F16], Uses = [FPMR, FPCR] in {
1018+
def FTMOPA_M2ZZZI_BtoH : sme_tmopa_16b<0b01001, ZZ_b_mul_r, ZPR8, "ftmopa">;
1019+
} // [HasSME2p2, HasSMEF8F16], Uses = [FPMR, FPCR]
1020+
1021+
let Predicates = [HasSME2p2, HasSMEF16F16] in {
1022+
def FTMOPA_M2ZZZI_HtoH : sme_tmopa_16b<0b10001, ZZ_h_mul_r, ZPR16, "ftmopa">;
1023+
} // [HasSME2p2, HasSMEF16F16]

‎llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1285,6 +1285,7 @@ class AArch64Operand : public MCParsedAsmOperand {
12851285
case AArch64::ZPR_4bRegClassID:
12861286
case AArch64::ZPRMul2_LoRegClassID:
12871287
case AArch64::ZPRMul2_HiRegClassID:
1288+
case AArch64::ZPR_KRegClassID:
12881289
RK = RegKind::SVEDataVector;
12891290
break;
12901291
case AArch64::PPRRegClassID:
@@ -6179,6 +6180,9 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
61796180
case Match_InvalidZPRMul2_Hi64:
61806181
return Error(Loc, "Invalid restricted vector register, expected even "
61816182
"register in z16.d..z30.d");
6183+
case Match_InvalidZPR_K0:
6184+
return Error(Loc, "invalid restricted vector register, expected register "
6185+
"in z20..z23 or z28..z31");
61826186
case Match_InvalidSVEPattern:
61836187
return Error(Loc, "invalid predicate pattern");
61846188
case Match_InvalidSVEPPRorPNRAnyReg:
@@ -6888,6 +6892,7 @@ bool AArch64AsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
68886892
case Match_InvalidZPRMul2_Hi32:
68896893
case Match_InvalidZPRMul2_Lo64:
68906894
case Match_InvalidZPRMul2_Hi64:
6895+
case Match_InvalidZPR_K0:
68916896
case Match_InvalidSVEVectorList2x8Mul2:
68926897
case Match_InvalidSVEVectorList2x16Mul2:
68936898
case Match_InvalidSVEVectorList2x32Mul2:

‎llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -49,6 +49,8 @@ template <unsigned Min, unsigned Max>
4949
static DecodeStatus DecodeZPRMul2_MinMax(MCInst &Inst, unsigned RegNo,
5050
uint64_t Address,
5151
const MCDisassembler *Decoder);
52+
static DecodeStatus DecodeZK(MCInst &Inst, unsigned RegNo, uint64_t Address,
53+
const MCDisassembler *Decoder);
5254
template <unsigned Min, unsigned Max>
5355
static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
5456
uint64_t Address,
@@ -387,6 +389,17 @@ static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
387389
return Success;
388390
}
389391

392+
static DecodeStatus DecodeZK(MCInst &Inst, unsigned RegNo, uint64_t Address,
393+
const MCDisassembler *Decoder) {
394+
if (RegNo > 7)
395+
return Fail;
396+
397+
unsigned Register =
398+
AArch64MCRegisterClasses[AArch64::ZPR_KRegClassID].getRegister(RegNo);
399+
Inst.addOperand(MCOperand::createReg(Register));
400+
return Success;
401+
}
402+
390403
static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo,
391404
uint64_t Address,
392405
const void *Decoder) {

‎llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -195,6 +195,9 @@ class AArch64MCCodeEmitter : public MCCodeEmitter {
195195
uint32_t EncodeRegMul_MinMax(const MCInst &MI, unsigned OpIdx,
196196
SmallVectorImpl<MCFixup> &Fixups,
197197
const MCSubtargetInfo &STI) const;
198+
uint32_t EncodeZK(const MCInst &MI, unsigned OpIdx,
199+
SmallVectorImpl<MCFixup> &Fixups,
200+
const MCSubtargetInfo &STI) const;
198201
uint32_t EncodePNR_p8to15(const MCInst &MI, unsigned OpIdx,
199202
SmallVectorImpl<MCFixup> &Fixups,
200203
const MCSubtargetInfo &STI) const;
@@ -573,6 +576,25 @@ AArch64MCCodeEmitter::EncodeRegMul_MinMax(const MCInst &MI, unsigned OpIdx,
573576
return (RegVal - Min) / Multiple;
574577
}
575578

579+
// Zk Is the name of the control vector register Z20-Z23 or Z28-Z31, encoded in
580+
// the "K:Zk" fields. Z20-Z23 = 000, 001,010, 011 and Z28-Z31 = 100, 101, 110,
581+
// 111
582+
uint32_t AArch64MCCodeEmitter::EncodeZK(const MCInst &MI, unsigned OpIdx,
583+
SmallVectorImpl<MCFixup> &Fixups,
584+
const MCSubtargetInfo &STI) const {
585+
auto RegOpnd = MI.getOperand(OpIdx).getReg();
586+
unsigned RegVal = Ctx.getRegisterInfo()->getEncodingValue(RegOpnd);
587+
588+
// ZZ8-Z31 => Reg is in 3..7 (offset 24)
589+
if (RegOpnd > AArch64::Z27)
590+
return (RegVal - 24);
591+
592+
assert((RegOpnd > AArch64::Z19 && RegOpnd < AArch64::Z24) &&
593+
"Expected ZK in Z20..Z23 or Z28..Z31");
594+
// Z20-Z23 => Reg is in 0..3 (offset 20)
595+
return (RegVal - 20);
596+
}
597+
576598
uint32_t
577599
AArch64MCCodeEmitter::EncodePNR_p8to15(const MCInst &MI, unsigned OpIdx,
578600
SmallVectorImpl<MCFixup> &Fixups,

‎llvm/lib/Target/AArch64/SMEInstrFormats.td

Lines changed: 62 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3192,6 +3192,68 @@ multiclass sme2_int_bmopx_tile<string mnemonic, bits<3> op, SDPatternOperator i
31923192
def : SME_ZA_Tile_TwoPred_TwoVec_Pat<NAME, intrinsic, timm32_0_3, nxv4i1, nxv4i32>;
31933193
}
31943194

3195+
//===----------------------------------------------------------------------===//
3196+
// SME2 Sparse Outer Product and Accumulate
3197+
3198+
class sme_tmopa_16b<bits<5> opc, RegisterOperand zn_ty, RegisterOperand zm_ty, string mnemonic>
3199+
: I<(outs TileOp16:$ZAda),
3200+
(ins TileOp16:$_ZAda, zn_ty:$Zn, zm_ty:$Zm, ZK:$Zk, VectorIndexS32b:$imm),
3201+
mnemonic, "\t$ZAda, $Zn, $Zm, $Zk$imm",
3202+
"", []>,
3203+
Sched<[]> {
3204+
bit ZAda;
3205+
bits<4> Zn;
3206+
bits<5> Zm;
3207+
bits<3> Zk;
3208+
bits<2> imm;
3209+
let Inst{31-25} = 0b1000000;
3210+
let Inst{24} = opc{4};
3211+
let Inst{23-22} = 0b01;
3212+
let Inst{21} = opc{3};
3213+
let Inst{20-16} = Zm;
3214+
let Inst{15} = opc{2};
3215+
let Inst{14} = 0b0;
3216+
let Inst{13} = opc{1};
3217+
let Inst{12-10} = Zk;
3218+
let Inst{9-6} = Zn;
3219+
let Inst{5-4} = imm;
3220+
let Inst{3} = opc{0};
3221+
let Inst{2-1} = 0b00;
3222+
let Inst{0} = ZAda;
3223+
3224+
let Constraints = "$ZAda = $_ZAda";
3225+
}
3226+
3227+
class sme_tmopa_32b<bits<5> opc, RegisterOperand zn_ty, RegisterOperand zm_ty, string mnemonic>
3228+
: I<(outs TileOp32:$ZAda),
3229+
(ins TileOp32:$_ZAda, zn_ty:$Zn, zm_ty:$Zm, ZK:$Zk, VectorIndexS32b:$imm),
3230+
mnemonic, "\t$ZAda, $Zn, $Zm, $Zk$imm",
3231+
"", []>,
3232+
Sched<[]> {
3233+
bits<2> ZAda;
3234+
bits<4> Zn;
3235+
bits<5> Zm;
3236+
bits<3> Zk;
3237+
bits<2> imm;
3238+
let Inst{31-25} = 0b1000000;
3239+
let Inst{24} = opc{4};
3240+
let Inst{23-22} = 0b01;
3241+
let Inst{21} = opc{3};
3242+
let Inst{20-16} = Zm;
3243+
let Inst{15} = opc{2};
3244+
let Inst{14} = 0b0;
3245+
let Inst{13} = opc{1};
3246+
let Inst{12-10} = Zk;
3247+
let Inst{9-6} = Zn;
3248+
let Inst{5-4} = imm;
3249+
let Inst{3} = opc{0};
3250+
let Inst{2} = 0b0;
3251+
let Inst{1-0} = ZAda;
3252+
3253+
let Constraints = "$ZAda = $_ZAda";
3254+
}
3255+
3256+
31953257
//===----------------------------------------------------------------------===///
31963258
// SME2 Zero Lookup Table.
31973259
class sme2_zero_zt<string mnemonic, bits<4> opc>

‎llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,7 @@ tracksRegLiveness: true
5757
body: |
5858
bb.1:
5959
; CHECK-LABEL: name: inlineasm_virt_reg_output
60-
; CHECK: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 2490378 /* regdef:FPR32_with_hsub_in_FPR16_lo */, def %0
60+
; CHECK: INLINEASM &"mov ${0:w}, 7", 0 /* attdialect */, 2490378 /* regdef:GPR32common */, def %0
6161
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY %0
6262
; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
6363
; CHECK-NEXT: RET_ReallyLR implicit $w0
@@ -75,7 +75,7 @@ tracksRegLiveness: true
7575
body: |
7676
bb.1:
7777
; CHECK-LABEL: name: inlineasm_virt_mixed_types
78-
; CHECK: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 2490378 /* regdef:FPR32_with_hsub_in_FPR16_lo */, def %0, 3342346 /* regdef:GPR64 */, def %1
78+
; CHECK: INLINEASM &"mov $0, #0; mov $1, #0", 0 /* attdialect */, 2490378 /* regdef:GPR32common */, def %0, 3342346 /* regdef:FPR64 */, def %1
7979
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY %0
8080
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr(s64) = COPY %1
8181
; CHECK-NEXT: $d0 = COPY [[COPY1]](s64)

‎llvm/test/CodeGen/AArch64/aarch64-sve-asm.ll

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ define <vscale x 16 x i8> @test_svadd_i8(<vscale x 16 x i8> %Zn, <vscale x 16 x
1313
; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
1414
; CHECK-NEXT: [[COPY2:%[0-9]+]]:zpr = COPY [[COPY1]]
1515
; CHECK-NEXT: [[COPY3:%[0-9]+]]:zpr_3b = COPY [[COPY]]
16-
; CHECK-NEXT: INLINEASM &"add $0.b, $1.b, $2.b", 0 /* attdialect */, 5701642 /* regdef:ZPR */, def %2, 5701641 /* reguse:ZPR */, [[COPY2]], 6291465 /* reguse:ZPR_3b */, [[COPY3]]
16+
; CHECK-NEXT: INLINEASM &"add $0.b, $1.b, $2.b", 0 /* attdialect */, 5767178 /* regdef:ZPR */, def %2, 5767177 /* reguse:ZPR */, [[COPY2]], 6357001 /* reguse:ZPR_3b */, [[COPY3]]
1717
; CHECK-NEXT: $z0 = COPY %2
1818
; CHECK-NEXT: RET_ReallyLR implicit $z0
1919
%1 = tail call <vscale x 16 x i8> asm "add $0.b, $1.b, $2.b", "=w,w,y"(<vscale x 16 x i8> %Zn, <vscale x 16 x i8> %Zm)
@@ -29,7 +29,7 @@ define <vscale x 2 x i64> @test_svsub_i64(<vscale x 2 x i64> %Zn, <vscale x 2 x
2929
; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
3030
; CHECK-NEXT: [[COPY2:%[0-9]+]]:zpr = COPY [[COPY1]]
3131
; CHECK-NEXT: [[COPY3:%[0-9]+]]:zpr_4b = COPY [[COPY]]
32-
; CHECK-NEXT: INLINEASM &"sub $0.d, $1.d, $2.d", 0 /* attdialect */, 5701642 /* regdef:ZPR */, def %2, 5701641 /* reguse:ZPR */, [[COPY2]], 5963785 /* reguse:ZPR_4b */, [[COPY3]]
32+
; CHECK-NEXT: INLINEASM &"sub $0.d, $1.d, $2.d", 0 /* attdialect */, 5767178 /* regdef:ZPR */, def %2, 5767177 /* reguse:ZPR */, [[COPY2]], 6029321 /* reguse:ZPR_4b */, [[COPY3]]
3333
; CHECK-NEXT: $z0 = COPY %2
3434
; CHECK-NEXT: RET_ReallyLR implicit $z0
3535
%1 = tail call <vscale x 2 x i64> asm "sub $0.d, $1.d, $2.d", "=w,w,x"(<vscale x 2 x i64> %Zn, <vscale x 2 x i64> %Zm)
@@ -45,7 +45,7 @@ define <vscale x 8 x half> @test_svfmul_f16(<vscale x 8 x half> %Zn, <vscale x 8
4545
; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
4646
; CHECK-NEXT: [[COPY2:%[0-9]+]]:zpr = COPY [[COPY1]]
4747
; CHECK-NEXT: [[COPY3:%[0-9]+]]:zpr_3b = COPY [[COPY]]
48-
; CHECK-NEXT: INLINEASM &"fmul $0.h, $1.h, $2.h", 0 /* attdialect */, 5701642 /* regdef:ZPR */, def %2, 5701641 /* reguse:ZPR */, [[COPY2]], 6291465 /* reguse:ZPR_3b */, [[COPY3]]
48+
; CHECK-NEXT: INLINEASM &"fmul $0.h, $1.h, $2.h", 0 /* attdialect */, 5767178 /* regdef:ZPR */, def %2, 5767177 /* reguse:ZPR */, [[COPY2]], 6357001 /* reguse:ZPR_3b */, [[COPY3]]
4949
; CHECK-NEXT: $z0 = COPY %2
5050
; CHECK-NEXT: RET_ReallyLR implicit $z0
5151
%1 = tail call <vscale x 8 x half> asm "fmul $0.h, $1.h, $2.h", "=w,w,y"(<vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
@@ -61,7 +61,7 @@ define <vscale x 4 x float> @test_svfmul_f(<vscale x 4 x float> %Zn, <vscale x 4
6161
; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
6262
; CHECK-NEXT: [[COPY2:%[0-9]+]]:zpr = COPY [[COPY1]]
6363
; CHECK-NEXT: [[COPY3:%[0-9]+]]:zpr_4b = COPY [[COPY]]
64-
; CHECK-NEXT: INLINEASM &"fmul $0.s, $1.s, $2.s", 0 /* attdialect */, 5701642 /* regdef:ZPR */, def %2, 5701641 /* reguse:ZPR */, [[COPY2]], 5963785 /* reguse:ZPR_4b */, [[COPY3]]
64+
; CHECK-NEXT: INLINEASM &"fmul $0.s, $1.s, $2.s", 0 /* attdialect */, 5767178 /* regdef:ZPR */, def %2, 5767177 /* reguse:ZPR */, [[COPY2]], 6029321 /* reguse:ZPR_4b */, [[COPY3]]
6565
; CHECK-NEXT: $z0 = COPY %2
6666
; CHECK-NEXT: RET_ReallyLR implicit $z0
6767
%1 = tail call <vscale x 4 x float> asm "fmul $0.s, $1.s, $2.s", "=w,w,x"(<vscale x 4 x float> %Zn, <vscale x 4 x float> %Zm)
@@ -79,7 +79,7 @@ define <vscale x 8 x half> @test_svfadd_f16(<vscale x 16 x i1> %Pg, <vscale x 8
7979
; CHECK-NEXT: [[COPY3:%[0-9]+]]:ppr_3b = COPY [[COPY2]]
8080
; CHECK-NEXT: [[COPY4:%[0-9]+]]:zpr = COPY [[COPY1]]
8181
; CHECK-NEXT: [[COPY5:%[0-9]+]]:zpr = COPY [[COPY]]
82-
; CHECK-NEXT: INLINEASM &"fadd $0.h, $1/m, $2.h, $3.h", 0 /* attdialect */, 5701642 /* regdef:ZPR */, def %3, 655369 /* reguse:PPR_3b */, [[COPY3]], 5701641 /* reguse:ZPR */, [[COPY4]], 5701641 /* reguse:ZPR */, [[COPY5]]
82+
; CHECK-NEXT: INLINEASM &"fadd $0.h, $1/m, $2.h, $3.h", 0 /* attdialect */, 5767178 /* regdef:ZPR */, def %3, 720905 /* reguse:PPR_3b */, [[COPY3]], 5767177 /* reguse:ZPR */, [[COPY4]], 5767177 /* reguse:ZPR */, [[COPY5]]
8383
; CHECK-NEXT: $z0 = COPY %3
8484
; CHECK-NEXT: RET_ReallyLR implicit $z0
8585
%1 = tail call <vscale x 8 x half> asm "fadd $0.h, $1/m, $2.h, $3.h", "=w,@3Upl,w,w"(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)
@@ -95,7 +95,7 @@ define <vscale x 4 x i32> @test_incp(<vscale x 16 x i1> %Pg, <vscale x 4 x i32>
9595
; CHECK-NEXT: [[COPY1:%[0-9]+]]:ppr = COPY $p0
9696
; CHECK-NEXT: [[COPY2:%[0-9]+]]:ppr = COPY [[COPY1]]
9797
; CHECK-NEXT: [[COPY3:%[0-9]+]]:zpr = COPY [[COPY]]
98-
; CHECK-NEXT: INLINEASM &"incp $0.s, $1", 0 /* attdialect */, 5701642 /* regdef:ZPR */, def %2, 393225 /* reguse:PPR */, [[COPY2]], 2147483657 /* reguse tiedto:$0 */, [[COPY3]](tied-def 3)
98+
; CHECK-NEXT: INLINEASM &"incp $0.s, $1", 0 /* attdialect */, 5767178 /* regdef:ZPR */, def %2, 458761 /* reguse:PPR */, [[COPY2]], 2147483657 /* reguse tiedto:$0 */, [[COPY3]](tied-def 3)
9999
; CHECK-NEXT: $z0 = COPY %2
100100
; CHECK-NEXT: RET_ReallyLR implicit $z0
101101
%1 = tail call <vscale x 4 x i32> asm "incp $0.s, $1", "=w,@3Upa,0"(<vscale x 16 x i1> %Pg, <vscale x 4 x i32> %Zn)
@@ -113,7 +113,7 @@ define <vscale x 8 x half> @test_svfadd_f16_Uph_constraint(<vscale x 16 x i1> %P
113113
; CHECK-NEXT: [[COPY3:%[0-9]+]]:ppr_p8to15 = COPY [[COPY2]]
114114
; CHECK-NEXT: [[COPY4:%[0-9]+]]:zpr = COPY [[COPY1]]
115115
; CHECK-NEXT: [[COPY5:%[0-9]+]]:zpr = COPY [[COPY]]
116-
; CHECK-NEXT: INLINEASM &"fadd $0.h, $1/m, $2.h, $3.h", 0 /* attdialect */, 5701642 /* regdef:ZPR */, def %3, 720905 /* reguse:PPR_p8to15 */, [[COPY3]], 5701641 /* reguse:ZPR */, [[COPY4]], 5701641 /* reguse:ZPR */, [[COPY5]]
116+
; CHECK-NEXT: INLINEASM &"fadd $0.h, $1/m, $2.h, $3.h", 0 /* attdialect */, 5767178 /* regdef:ZPR */, def %3, 786441 /* reguse:PPR_p8to15 */, [[COPY3]], 5767177 /* reguse:ZPR */, [[COPY4]], 5767177 /* reguse:ZPR */, [[COPY5]]
117117
; CHECK-NEXT: $z0 = COPY %3
118118
; CHECK-NEXT: RET_ReallyLR implicit $z0
119119
%1 = tail call <vscale x 8 x half> asm "fadd $0.h, $1/m, $2.h, $3.h", "=w,@3Uph,w,w"(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm)

‎llvm/test/CodeGen/AArch64/emit_fneg_with_non_register_operand.mir

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -91,10 +91,10 @@ body: |
9191
; CHECK-NEXT: {{ $}}
9292
; CHECK-NEXT: [[LOADgot:%[0-9]+]]:gpr64common = LOADgot target-flags(aarch64-got) @c
9393
; CHECK-NEXT: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[LOADgot]], 0 :: (dereferenceable load (s64) from @c)
94-
; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 3342346 /* regdef:GPR64 */, def %2, 2147483657 /* reguse tiedto:$0 */, [[LDRDui]](tied-def 3)
94+
; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 3342346 /* regdef:FPR64 */, def %2, 2147483657 /* reguse tiedto:$0 */, [[LDRDui]](tied-def 3)
9595
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY %2
9696
; CHECK-NEXT: [[LDRDui1:%[0-9]+]]:fpr64 = LDRDui [[LOADgot]], 0 :: (dereferenceable load (s64) from @c)
97-
; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 3342346 /* regdef:GPR64 */, def %4, 2147483657 /* reguse tiedto:$0 */, [[LDRDui1]](tied-def 3)
97+
; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, 3342346 /* regdef:FPR64 */, def %4, 2147483657 /* reguse tiedto:$0 */, [[LDRDui1]](tied-def 3)
9898
; CHECK-NEXT: [[FNEGDr:%[0-9]+]]:fpr64 = FNEGDr %2
9999
; CHECK-NEXT: nofpexcept FCMPDrr %4, killed [[FNEGDr]], implicit-def $nzcv, implicit $fpcr
100100
; CHECK-NEXT: Bcc 1, %bb.2, implicit $nzcv

‎llvm/test/CodeGen/AArch64/fmlal-loreg.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,8 +11,8 @@ define <4 x float> @test(ptr %lhs_panel, ptr %rhs_panel, <4 x float> %a) {
1111
; CHECK-NEXT: .cfi_def_cfa_offset 16
1212
; CHECK-NEXT: .cfi_offset b8, -16
1313
; CHECK-NEXT: fmov x8, d0
14-
; CHECK-NEXT: ldr q8, [x0]
1514
; CHECK-NEXT: ldr q16, [x1]
15+
; CHECK-NEXT: ldr q8, [x0]
1616
; CHECK-NEXT: lsr x9, x8, #32
1717
; CHECK-NEXT: //APP
1818
; CHECK-NEXT: nop

‎llvm/test/CodeGen/AArch64/peephole-insvigpr.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -487,7 +487,7 @@ body: |
487487
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
488488
; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF
489489
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[DEF]]
490-
; CHECK-NEXT: INLINEASM &"ldr ${0:s}, $1", 8 /* mayload attdialect */, 3342346 /* regdef:GPR64 */, def %1, 262158 /* mem:m */, killed [[COPY1]]
490+
; CHECK-NEXT: INLINEASM &"ldr ${0:s}, $1", 8 /* mayload attdialect */, 3342346 /* regdef:FPR64 */, def %1, 262158 /* mem:m */, killed [[COPY1]]
491491
; CHECK-NEXT: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0
492492
; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[MOVIv2d_ns]].dsub
493493
; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF

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