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| 1 | +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py |
| 2 | +; RUN: opt -S -passes=instcombine < %s | FileCheck %s |
| 3 | + |
| 4 | +target triple = "aarch64-unknown-linux-gnu" |
| 5 | + |
| 6 | +define <vscale x 16 x i8> @insr_val_into_splatted_val_int(i8 %a) #0 { |
| 7 | +; CHECK-LABEL: @insr_val_into_splatted_val_int( |
| 8 | +; CHECK-NEXT: [[T0:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[A:%.*]], i64 0 |
| 9 | +; CHECK-NEXT: [[T1:%.*]] = shufflevector <vscale x 16 x i8> [[T0]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer |
| 10 | +; CHECK-NEXT: ret <vscale x 16 x i8> [[T1]] |
| 11 | +; |
| 12 | + %t0 = insertelement <vscale x 16 x i8> poison, i8 %a, i64 0 |
| 13 | + %t1 = shufflevector <vscale x 16 x i8> %t0, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer |
| 14 | + %t2 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.insr.nxv16i8(<vscale x 16 x i8> %t1, i8 %a) |
| 15 | + ret <vscale x 16 x i8> %t2 |
| 16 | +} |
| 17 | + |
| 18 | +define <vscale x 8 x i16> @insr_five_into_fives() #0 { |
| 19 | +; CHECK-LABEL: @insr_five_into_fives( |
| 20 | +; CHECK-NEXT: ret <vscale x 8 x i16> shufflevector (<vscale x 8 x i16> insertelement (<vscale x 8 x i16> poison, i16 5, i64 0), <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer) |
| 21 | +; |
| 22 | + %t1 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.insr.nxv8i16(<vscale x 8 x i16> splat (i16 5), i16 5) |
| 23 | + ret <vscale x 8 x i16> %t1 |
| 24 | +} |
| 25 | + |
| 26 | +define <vscale x 4 x float> @insr_val_into_splatted_val_fp(float %a) #0 { |
| 27 | +; CHECK-LABEL: @insr_val_into_splatted_val_fp( |
| 28 | +; CHECK-NEXT: [[T0:%.*]] = insertelement <vscale x 4 x float> poison, float [[A:%.*]], i64 0 |
| 29 | +; CHECK-NEXT: [[T1:%.*]] = shufflevector <vscale x 4 x float> [[T0]], <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer |
| 30 | +; CHECK-NEXT: ret <vscale x 4 x float> [[T1]] |
| 31 | +; |
| 32 | + %t0 = insertelement <vscale x 4 x float> poison, float %a, i64 0 |
| 33 | + %t1 = shufflevector <vscale x 4 x float> %t0, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer |
| 34 | + %t2 = tail call <vscale x 4 x float> @llvm.aarch64.sve.insr.nxv4f32(<vscale x 4 x float> %t1, float %a) |
| 35 | + ret <vscale x 4 x float> %t2 |
| 36 | +} |
| 37 | + |
| 38 | +define <vscale x 2 x double> @insr_zero_into_zero() #0 { |
| 39 | +; CHECK-LABEL: @insr_zero_into_zero( |
| 40 | +; CHECK-NEXT: ret <vscale x 2 x double> zeroinitializer |
| 41 | +; |
| 42 | + %t1 = tail call <vscale x 2 x double> @llvm.aarch64.sve.insr.nxv2f64(<vscale x 2 x double> zeroinitializer, double zeroinitializer) |
| 43 | + ret <vscale x 2 x double> %t1 |
| 44 | +} |
| 45 | + |
| 46 | +define <vscale x 16 x i8> @insr_val_into_splatted_other(i8 %a, i8 %b) #0 { |
| 47 | +; CHECK-LABEL: @insr_val_into_splatted_other( |
| 48 | +; CHECK-NEXT: [[T0:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[B:%.*]], i64 0 |
| 49 | +; CHECK-NEXT: [[T1:%.*]] = shufflevector <vscale x 16 x i8> [[T0]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer |
| 50 | +; CHECK-NEXT: [[T2:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.insr.nxv16i8(<vscale x 16 x i8> [[T1]], i8 [[A:%.*]]) |
| 51 | +; CHECK-NEXT: ret <vscale x 16 x i8> [[T2]] |
| 52 | +; |
| 53 | + %t0 = insertelement <vscale x 16 x i8> poison, i8 %b, i64 0 |
| 54 | + %t1 = shufflevector <vscale x 16 x i8> %t0, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer |
| 55 | + %t2 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.insr.nxv16i8(<vscale x 16 x i8> %t1, i8 %a) |
| 56 | + ret <vscale x 16 x i8> %t2 |
| 57 | +} |
| 58 | + |
| 59 | +define <vscale x 8 x i16> @insr_three_into_fives() #0 { |
| 60 | +; CHECK-LABEL: @insr_three_into_fives( |
| 61 | +; CHECK-NEXT: [[T1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.insr.nxv8i16(<vscale x 8 x i16> shufflevector (<vscale x 8 x i16> insertelement (<vscale x 8 x i16> poison, i16 5, i64 0), <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer), i16 3) |
| 62 | +; CHECK-NEXT: ret <vscale x 8 x i16> [[T1]] |
| 63 | +; |
| 64 | + %t1 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.insr.nxv8i16(<vscale x 8 x i16> splat (i16 5), i16 3) |
| 65 | + ret <vscale x 8 x i16> %t1 |
| 66 | +} |
| 67 | + |
| 68 | +declare <vscale x 16 x i8> @llvm.aarch64.sve.insr.nxv16i8(<vscale x 16 x i8>, i8) |
| 69 | +declare <vscale x 8 x i16> @llvm.aarch64.sve.insr.nxv8i16(<vscale x 8 x i16>, i16) |
| 70 | +declare <vscale x 4 x float> @llvm.aarch64.sve.insr.nxv4f32(<vscale x 4 x float>, float) |
| 71 | +declare <vscale x 2 x double> @llvm.aarch64.sve.insr.nxv2f64(<vscale x 2 x double>, double) |
| 72 | + |
| 73 | +attributes #0 = { "target-features"="+sve" } |
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