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Revert "[ARM] Stop gluing FP comparisons to FMSTAT" (#117175)
Reverts #116676 Reverting per post-commit feedback (causes miscompilation errors and/or assertion failures).
1 parent 0cb1cca commit 5d32a14

17 files changed

+4600
-2683
lines changed

‎llvm/lib/Target/ARM/ARMISelLowering.cpp

Lines changed: 15 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -4971,14 +4971,14 @@ SDValue ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS,
49714971
SelectionDAG &DAG, const SDLoc &dl,
49724972
bool Signaling) const {
49734973
assert(Subtarget->hasFP64() || RHS.getValueType() != MVT::f64);
4974-
SDValue Flags;
4974+
SDValue Cmp;
49754975
if (!isFloatingPointZero(RHS))
4976-
Flags = DAG.getNode(Signaling ? ARMISD::CMPFPE : ARMISD::CMPFP, dl, FlagsVT,
4977-
LHS, RHS);
4976+
Cmp = DAG.getNode(Signaling ? ARMISD::CMPFPE : ARMISD::CMPFP,
4977+
dl, MVT::Glue, LHS, RHS);
49784978
else
4979-
Flags = DAG.getNode(Signaling ? ARMISD::CMPFPEw0 : ARMISD::CMPFPw0, dl,
4980-
FlagsVT, LHS);
4981-
return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Flags);
4979+
Cmp = DAG.getNode(Signaling ? ARMISD::CMPFPEw0 : ARMISD::CMPFPw0,
4980+
dl, MVT::Glue, LHS);
4981+
return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
49824982
}
49834983

49844984
/// duplicateCmp - Glue values can have only one use, so this function
@@ -4991,11 +4991,15 @@ ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
49914991
return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
49924992

49934993
assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
4994-
SDValue Flags = Cmp.getOperand(0);
4995-
assert((Flags.getOpcode() == ARMISD::CMPFP ||
4996-
Flags.getOpcode() == ARMISD::CMPFPw0) &&
4997-
"unexpected operand of FMSTAT");
4998-
return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Flags);
4994+
Cmp = Cmp.getOperand(0);
4995+
Opc = Cmp.getOpcode();
4996+
if (Opc == ARMISD::CMPFP)
4997+
Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
4998+
else {
4999+
assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
5000+
Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
5001+
}
5002+
return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
49995003
}
50005004

50015005
// This function returns three things: the arithmetic computation itself

‎llvm/lib/Target/ARM/ARMInstrVFP.td

Lines changed: 19 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -10,36 +10,19 @@
1010
//
1111
//===----------------------------------------------------------------------===//
1212

13-
def SDT_CMPFP : SDTypeProfile<1, 2, [
14-
SDTCisVT<0, FlagsVT>, // out flags
15-
SDTCisFP<1>, // lhs
16-
SDTCisSameAs<2, 1> // rhs
17-
]>;
18-
19-
def SDT_CMPFP0 : SDTypeProfile<1, 1, [
20-
SDTCisVT<0, FlagsVT>, // out flags
21-
SDTCisFP<1> // operand
22-
]>;
23-
13+
def SDT_CMPFP0 : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
2414
def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
2515
SDTCisSameAs<1, 2>]>;
2616
def SDT_VMOVRRD : SDTypeProfile<2, 1, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
2717
SDTCisVT<2, f64>]>;
2818

2919
def SDT_VMOVSR : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisVT<1, i32>]>;
3020

31-
def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_CMPFP>;
32-
def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0>;
33-
def arm_cmpfpe : SDNode<"ARMISD::CMPFPE", SDT_CMPFP>;
34-
def arm_cmpfpe0 : SDNode<"ARMISD::CMPFPEw0", SDT_CMPFP0>;
35-
36-
def arm_fmstat : SDNode<"ARMISD::FMSTAT",
37-
SDTypeProfile<0, 1, [
38-
SDTCisVT<0, FlagsVT> // in flags
39-
]>,
40-
[SDNPOutGlue] // TODO: Change Glue to a normal result.
41-
>;
42-
21+
def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInGlue, SDNPOutGlue]>;
22+
def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutGlue]>;
23+
def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutGlue]>;
24+
def arm_cmpfpe : SDNode<"ARMISD::CMPFPE", SDT_ARMCmp, [SDNPOutGlue]>;
25+
def arm_cmpfpe0: SDNode<"ARMISD::CMPFPEw0",SDT_CMPFP0, [SDNPOutGlue]>;
4326
def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
4427
def arm_fmrrd : SDNode<"ARMISD::VMOVRRD", SDT_VMOVRRD>;
4528
def arm_vmovsr : SDNode<"ARMISD::VMOVSR", SDT_VMOVSR>;
@@ -623,12 +606,12 @@ let Defs = [FPSCR_NZCV] in {
623606
def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0,
624607
(outs), (ins DPR:$Dd, DPR:$Dm),
625608
IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm", "",
626-
[(set FPSCR_NZCV, (arm_cmpfpe DPR:$Dd, (f64 DPR:$Dm)))]>;
609+
[(arm_cmpfpe DPR:$Dd, (f64 DPR:$Dm))]>;
627610

628611
def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0,
629612
(outs), (ins SPR:$Sd, SPR:$Sm),
630613
IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm", "",
631-
[(set FPSCR_NZCV, (arm_cmpfpe SPR:$Sd, SPR:$Sm))]> {
614+
[(arm_cmpfpe SPR:$Sd, SPR:$Sm)]> {
632615
// Some single precision VFP instructions may be executed on both NEON and
633616
// VFP pipelines on A8.
634617
let D = VFPNeonA8Domain;
@@ -637,17 +620,17 @@ def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0,
637620
def VCMPEH : AHuI<0b11101, 0b11, 0b0100, 0b11, 0,
638621
(outs), (ins HPR:$Sd, HPR:$Sm),
639622
IIC_fpCMP16, "vcmpe", ".f16\t$Sd, $Sm",
640-
[(set FPSCR_NZCV, (arm_cmpfpe (f16 HPR:$Sd), (f16 HPR:$Sm)))]>;
623+
[(arm_cmpfpe (f16 HPR:$Sd), (f16 HPR:$Sm))]>;
641624

642625
def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0,
643626
(outs), (ins DPR:$Dd, DPR:$Dm),
644627
IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm", "",
645-
[(set FPSCR_NZCV, (arm_cmpfp DPR:$Dd, (f64 DPR:$Dm)))]>;
628+
[(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>;
646629

647630
def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0,
648631
(outs), (ins SPR:$Sd, SPR:$Sm),
649632
IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm", "",
650-
[(set FPSCR_NZCV, (arm_cmpfp SPR:$Sd, SPR:$Sm))]> {
633+
[(arm_cmpfp SPR:$Sd, SPR:$Sm)]> {
651634
// Some single precision VFP instructions may be executed on both NEON and
652635
// VFP pipelines on A8.
653636
let D = VFPNeonA8Domain;
@@ -656,7 +639,7 @@ def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0,
656639
def VCMPH : AHuI<0b11101, 0b11, 0b0100, 0b01, 0,
657640
(outs), (ins HPR:$Sd, HPR:$Sm),
658641
IIC_fpCMP16, "vcmp", ".f16\t$Sd, $Sm",
659-
[(set FPSCR_NZCV, (arm_cmpfp (f16 HPR:$Sd), (f16 HPR:$Sm)))]>;
642+
[(arm_cmpfp (f16 HPR:$Sd), (f16 HPR:$Sm))]>;
660643
} // Defs = [FPSCR_NZCV]
661644

662645
//===----------------------------------------------------------------------===//
@@ -686,15 +669,15 @@ let Defs = [FPSCR_NZCV] in {
686669
def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0,
687670
(outs), (ins DPR:$Dd),
688671
IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0", "",
689-
[(set FPSCR_NZCV, (arm_cmpfpe0 (f64 DPR:$Dd)))]> {
672+
[(arm_cmpfpe0 (f64 DPR:$Dd))]> {
690673
let Inst{3-0} = 0b0000;
691674
let Inst{5} = 0;
692675
}
693676

694677
def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0,
695678
(outs), (ins SPR:$Sd),
696679
IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0", "",
697-
[(set FPSCR_NZCV, (arm_cmpfpe0 SPR:$Sd))]> {
680+
[(arm_cmpfpe0 SPR:$Sd)]> {
698681
let Inst{3-0} = 0b0000;
699682
let Inst{5} = 0;
700683

@@ -706,23 +689,23 @@ def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0,
706689
def VCMPEZH : AHuI<0b11101, 0b11, 0b0101, 0b11, 0,
707690
(outs), (ins HPR:$Sd),
708691
IIC_fpCMP16, "vcmpe", ".f16\t$Sd, #0",
709-
[(set FPSCR_NZCV, (arm_cmpfpe0 (f16 HPR:$Sd)))]> {
692+
[(arm_cmpfpe0 (f16 HPR:$Sd))]> {
710693
let Inst{3-0} = 0b0000;
711694
let Inst{5} = 0;
712695
}
713696

714697
def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0,
715698
(outs), (ins DPR:$Dd),
716699
IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0", "",
717-
[(set FPSCR_NZCV, (arm_cmpfp0 (f64 DPR:$Dd)))]> {
700+
[(arm_cmpfp0 (f64 DPR:$Dd))]> {
718701
let Inst{3-0} = 0b0000;
719702
let Inst{5} = 0;
720703
}
721704

722705
def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0,
723706
(outs), (ins SPR:$Sd),
724707
IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0", "",
725-
[(set FPSCR_NZCV, (arm_cmpfp0 SPR:$Sd))]> {
708+
[(arm_cmpfp0 SPR:$Sd)]> {
726709
let Inst{3-0} = 0b0000;
727710
let Inst{5} = 0;
728711

@@ -734,7 +717,7 @@ def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0,
734717
def VCMPZH : AHuI<0b11101, 0b11, 0b0101, 0b01, 0,
735718
(outs), (ins HPR:$Sd),
736719
IIC_fpCMP16, "vcmp", ".f16\t$Sd, #0",
737-
[(set FPSCR_NZCV, (arm_cmpfp0 (f16 HPR:$Sd)))]> {
720+
[(arm_cmpfp0 (f16 HPR:$Sd))]> {
738721
let Inst{3-0} = 0b0000;
739722
let Inst{5} = 0;
740723
}
@@ -2509,8 +2492,7 @@ let DecoderMethod = "DecodeForVMRSandVMSR" in {
25092492
let Defs = [CPSR], Uses = [FPSCR_NZCV], Predicates = [HasFPRegs],
25102493
Rt = 0b1111 /* apsr_nzcv */ in
25112494
def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
2512-
"vmrs", "\tAPSR_nzcv, fpscr",
2513-
[(arm_fmstat FPSCR_NZCV)]>;
2495+
"vmrs", "\tAPSR_nzcv, fpscr", [(arm_fmstat)]>;
25142496

25152497
// Application level FPSCR -> GPR
25162498
let hasSideEffects = 1, Uses = [FPSCR], Predicates = [HasFPRegs] in

‎llvm/lib/Target/ARM/ARMRegisterInfo.td

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -413,9 +413,7 @@ def VCCR : RegisterClass<"ARM", [i32, v16i1, v8i1, v4i1, v2i1], 32, (add VPR)> {
413413

414414
// FPSCR, when the flags at the top of it are used as the input or
415415
// output to an instruction such as MVE VADC.
416-
def cl_FPSCR_NZCV : RegisterClass<"ARM", [i32], 32, (add FPSCR_NZCV)> {
417-
let CopyCost = -1;
418-
}
416+
def cl_FPSCR_NZCV : RegisterClass<"ARM", [i32], 32, (add FPSCR_NZCV)>;
419417

420418
// Scalar single precision floating point register class..
421419
// FIXME: Allocation order changed to s0, s2, ... or s0, s4, ... as a quick hack

‎llvm/test/CodeGen/ARM/fcmp-xo.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -54,12 +54,12 @@ define arm_aapcs_vfpcc float @float128(float %a0) local_unnamed_addr {
5454
; NEON-LABEL: float128:
5555
; NEON: @ %bb.0:
5656
; NEON-NEXT: mov.w r0, #1124073472
57-
; NEON-NEXT: vmov.f32 s4, #5.000000e-01
58-
; NEON-NEXT: vmov d1, r0, r0
59-
; NEON-NEXT: vmov.f32 s6, #-5.000000e-01
60-
; NEON-NEXT: vcmp.f32 s2, s0
57+
; NEON-NEXT: vmov.f32 s2, #5.000000e-01
58+
; NEON-NEXT: vmov d3, r0, r0
59+
; NEON-NEXT: vmov.f32 s4, #-5.000000e-01
60+
; NEON-NEXT: vcmp.f32 s6, s0
6161
; NEON-NEXT: vmrs APSR_nzcv, fpscr
62-
; NEON-NEXT: vselgt.f32 s0, s6, s4
62+
; NEON-NEXT: vselgt.f32 s0, s4, s2
6363
; NEON-NEXT: bx lr
6464
%1 = fcmp nsz olt float %a0, 128.000000e+00
6565
%2 = select i1 %1, float -5.000000e-01, float 5.000000e-01

‎llvm/test/CodeGen/ARM/fp16-instructions.ll

Lines changed: 29 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -700,9 +700,9 @@ define half @select_cc1(ptr %a0) {
700700

701701
; CHECK-LABEL: select_cc1:
702702

703-
; CHECK-HARDFP-FULLFP16: vcmp.f16
704-
; CHECK-HARDFP-FULLFP16: vmrs APSR_nzcv, fpscr
705-
; CHECK-HARDFP-FULLFP16: vseleq.f16 s0,
703+
; CHECK-HARDFP-FULLFP16: vcmp.f16
704+
; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
705+
; CHECK-HARDFP-FULLFP16-NEXT: vseleq.f16 s0,
706706

707707
; CHECK-SOFTFP-FP16-A32: vcmp.f32
708708
; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
@@ -728,9 +728,9 @@ define half @select_cc_ge1(ptr %a0) {
728728

729729
; CHECK-LABEL: select_cc_ge1:
730730

731-
; CHECK-HARDFP-FULLFP16: vcmp.f16
732-
; CHECK-HARDFP-FULLFP16: vmrs APSR_nzcv, fpscr
733-
; CHECK-HARDFP-FULLFP16: vselge.f16 s0,
731+
; CHECK-HARDFP-FULLFP16: vcmp.f16
732+
; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
733+
; CHECK-HARDFP-FULLFP16-NEXT: vselge.f16 s0,
734734

735735
; CHECK-SOFTFP-FP16-A32: vcmp.f32
736736
; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
@@ -751,9 +751,9 @@ define half @select_cc_ge2(ptr %a0) {
751751

752752
; CHECK-LABEL: select_cc_ge2:
753753

754-
; CHECK-HARDFP-FULLFP16: vcmp.f16
755-
; CHECK-HARDFP-FULLFP16: vmrs APSR_nzcv, fpscr
756-
; CHECK-HARDFP-FULLFP16: vselge.f16 s0,
754+
; CHECK-HARDFP-FULLFP16: vcmp.f16
755+
; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
756+
; CHECK-HARDFP-FULLFP16-NEXT: vselge.f16 s0,
757757

758758
; CHECK-SOFTFP-FP16-A32: vcmp.f32
759759
; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
@@ -774,9 +774,9 @@ define half @select_cc_ge3(ptr %a0) {
774774

775775
; CHECK-LABEL: select_cc_ge3:
776776

777-
; CHECK-HARDFP-FULLFP16: vcmp.f16
778-
; CHECK-HARDFP-FULLFP16: vmrs APSR_nzcv, fpscr
779-
; CHECK-HARDFP-FULLFP16: vselge.f16 s0,
777+
; CHECK-HARDFP-FULLFP16: vcmp.f16
778+
; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
779+
; CHECK-HARDFP-FULLFP16-NEXT: vselge.f16 s0,
780780

781781
; CHECK-SOFTFP-FP16-A32: vcmp.f32
782782
; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
@@ -797,9 +797,9 @@ define half @select_cc_ge4(ptr %a0) {
797797

798798
; CHECK-LABEL: select_cc_ge4:
799799

800-
; CHECK-HARDFP-FULLFP16: vcmp.f16
801-
; CHECK-HARDFP-FULLFP16: vmrs APSR_nzcv, fpscr
802-
; CHECK-HARDFP-FULLFP16: vselge.f16 s0, s{{.}}, s{{.}}
800+
; CHECK-HARDFP-FULLFP16: vcmp.f16
801+
; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
802+
; CHECK-HARDFP-FULLFP16-NEXT: vselge.f16 s0, s{{.}}, s{{.}}
803803

804804
; CHECK-SOFTFP-FP16-A32: vcmp.f32
805805
; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
@@ -821,9 +821,9 @@ define half @select_cc_gt1(ptr %a0) {
821821

822822
; CHECK-LABEL: select_cc_gt1:
823823

824-
; CHECK-HARDFP-FULLFP16: vcmp.f16
825-
; CHECK-HARDFP-FULLFP16: vmrs APSR_nzcv, fpscr
826-
; CHECK-HARDFP-FULLFP16: vselgt.f16 s0, s{{.}}, s{{.}}
824+
; CHECK-HARDFP-FULLFP16: vcmp.f16
825+
; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
826+
; CHECK-HARDFP-FULLFP16-NEXT: vselgt.f16 s0, s{{.}}, s{{.}}
827827

828828
; CHECK-SOFTFP-FP16-A32: vcmp.f32
829829
; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
@@ -844,9 +844,9 @@ define half @select_cc_gt2(ptr %a0) {
844844

845845
; CHECK-LABEL: select_cc_gt2:
846846

847-
; CHECK-HARDFP-FULLFP16: vcmp.f16
848-
; CHECK-HARDFP-FULLFP16: vmrs APSR_nzcv, fpscr
849-
; CHECK-HARDFP-FULLFP16: vselgt.f16 s0, s{{.}}, s{{.}}
847+
; CHECK-HARDFP-FULLFP16: vcmp.f16
848+
; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
849+
; CHECK-HARDFP-FULLFP16-NEXT: vselgt.f16 s0, s{{.}}, s{{.}}
850850

851851
; CHECK-SOFTFP-FP16-A32: vcmp.f32
852852
; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
@@ -867,9 +867,9 @@ define half @select_cc_gt3(ptr %a0) {
867867

868868
; CHECK-LABEL: select_cc_gt3:
869869

870-
; CHECK-HARDFP-FULLFP16: vcmp.f16
871-
; CHECK-HARDFP-FULLFP16: vmrs APSR_nzcv, fpscr
872-
; CHECK-HARDFP-FULLFP16: vselgt.f16 s0, s{{.}}, s{{.}}
870+
; CHECK-HARDFP-FULLFP16: vcmp.f16
871+
; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
872+
; CHECK-HARDFP-FULLFP16-NEXT: vselgt.f16 s0, s{{.}}, s{{.}}
873873

874874
; CHECK-SOFTFP-FP16-A32: vcmp.f32
875875
; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
@@ -890,9 +890,9 @@ define half @select_cc_gt4(ptr %a0) {
890890

891891
; CHECK-LABEL: select_cc_gt4:
892892

893-
; CHECK-HARDFP-FULLFP16: vcmp.f16
894-
; CHECK-HARDFP-FULLFP16: vmrs APSR_nzcv, fpscr
895-
; CHECK-HARDFP-FULLFP16: vselgt.f16 s0, s{{.}}, s{{.}}
893+
; CHECK-HARDFP-FULLFP16: vcmp.f16
894+
; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
895+
; CHECK-HARDFP-FULLFP16-NEXT: vselgt.f16 s0, s{{.}}, s{{.}}
896896

897897
; CHECK-SOFTFP-FP16-A32: vcmp.f32
898898
; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
@@ -923,10 +923,10 @@ entry:
923923
; CHECK-LABEL: select_cc4:
924924

925925
; CHECK-HARDFP-FULLFP16: vldr.16 [[S2:s[0-9]]], .LCPI{{.*}}
926-
; CHECK-HARDFP-FULLFP16: vcmp.f16 s0, [[S2]]
927926
; CHECK-HARDFP-FULLFP16: vldr.16 [[S4:s[0-9]]], .LCPI{{.*}}
928-
; CHECK-HARDFP-FULLFP16: vmrs APSR_nzcv, fpscr
929927
; CHECK-HARDFP-FULLFP16: vmov.f16 [[S6:s[0-9]]], #-2.000000e+00
928+
; CHECK-HARDFP-FULLFP16: vcmp.f16 s0, [[S2]]
929+
; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
930930
; CHECK-HARDFP-FULLFP16-NEXT: vseleq.f16 [[S0:s[0-9]]], [[S6]], [[S4]]
931931
; CHECK-HARDFP-FULLFP16-NEXT: vselvs.f16 s0, [[S6]], [[S0]]
932932

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