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[AMDGPU] Use a generic printer for NamedIntOperands. (#100399)
This includes simplifying printing dmask modifiers where we don't need to mask the value to print. Part of <#62629>.
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+34
-123
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4 files changed

+34
-123
lines changed

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

Lines changed: 7 additions & 93 deletions
Original file line numberDiff line numberDiff line change
@@ -119,20 +119,6 @@ void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo,
119119
}
120120
}
121121

122-
void AMDGPUInstPrinter::printOffset0(const MCInst *MI, unsigned OpNo,
123-
const MCSubtargetInfo &STI,
124-
raw_ostream &O) {
125-
if (int64_t Offset = MI->getOperand(OpNo).getImm())
126-
O << " offset0:" << formatDec(Offset);
127-
}
128-
129-
void AMDGPUInstPrinter::printOffset1(const MCInst *MI, unsigned OpNo,
130-
const MCSubtargetInfo &STI,
131-
raw_ostream &O) {
132-
if (int64_t Offset = MI->getOperand(OpNo).getImm())
133-
O << " offset1:" << formatDec(Offset);
134-
}
135-
136122
void AMDGPUInstPrinter::printSMRDOffset8(const MCInst *MI, unsigned OpNo,
137123
const MCSubtargetInfo &STI,
138124
raw_ostream &O) {
@@ -145,13 +131,6 @@ void AMDGPUInstPrinter::printSMEMOffset(const MCInst *MI, unsigned OpNo,
145131
O << formatHex(MI->getOperand(OpNo).getImm());
146132
}
147133

148-
void AMDGPUInstPrinter::printSMEMOffsetMod(const MCInst *MI, unsigned OpNo,
149-
const MCSubtargetInfo &STI,
150-
raw_ostream &O) {
151-
O << " offset:";
152-
printSMEMOffset(MI, OpNo, STI, O);
153-
}
154-
155134
void AMDGPUInstPrinter::printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
156135
const MCSubtargetInfo &STI,
157136
raw_ostream &O) {
@@ -269,14 +248,6 @@ void AMDGPUInstPrinter::printScope(int64_t Scope, raw_ostream &O) {
269248
return;
270249
}
271250

272-
void AMDGPUInstPrinter::printDMask(const MCInst *MI, unsigned OpNo,
273-
const MCSubtargetInfo &STI, raw_ostream &O) {
274-
if (MI->getOperand(OpNo).getImm()) {
275-
O << " dmask:";
276-
printU16ImmOperand(MI, OpNo, STI, O);
277-
}
278-
}
279-
280251
void AMDGPUInstPrinter::printDim(const MCInst *MI, unsigned OpNo,
281252
const MCSubtargetInfo &STI, raw_ostream &O) {
282253
unsigned Dim = MI->getOperand(OpNo).getImm();
@@ -678,26 +649,6 @@ void AMDGPUInstPrinter::printBLGP(const MCInst *MI, unsigned OpNo,
678649
O << " blgp:" << Imm;
679650
}
680651

681-
void AMDGPUInstPrinter::printCBSZ(const MCInst *MI, unsigned OpNo,
682-
const MCSubtargetInfo &STI,
683-
raw_ostream &O) {
684-
unsigned Imm = MI->getOperand(OpNo).getImm();
685-
if (!Imm)
686-
return;
687-
688-
O << " cbsz:" << Imm;
689-
}
690-
691-
void AMDGPUInstPrinter::printABID(const MCInst *MI, unsigned OpNo,
692-
const MCSubtargetInfo &STI,
693-
raw_ostream &O) {
694-
unsigned Imm = MI->getOperand(OpNo).getImm();
695-
if (!Imm)
696-
return;
697-
698-
O << " abid:" << Imm;
699-
}
700-
701652
void AMDGPUInstPrinter::printDefaultVccOperand(bool FirstOperand,
702653
const MCSubtargetInfo &STI,
703654
raw_ostream &O) {
@@ -711,30 +662,6 @@ void AMDGPUInstPrinter::printDefaultVccOperand(bool FirstOperand,
711662
O << ", ";
712663
}
713664

714-
void AMDGPUInstPrinter::printWaitVDST(const MCInst *MI, unsigned OpNo,
715-
const MCSubtargetInfo &STI,
716-
raw_ostream &O) {
717-
O << " wait_vdst:" << formatDec(MI->getOperand(OpNo).getImm());
718-
}
719-
720-
void AMDGPUInstPrinter::printWaitVAVDst(const MCInst *MI, unsigned OpNo,
721-
const MCSubtargetInfo &STI,
722-
raw_ostream &O) {
723-
O << " wait_va_vdst:" << formatDec(MI->getOperand(OpNo).getImm());
724-
}
725-
726-
void AMDGPUInstPrinter::printWaitVMVSrc(const MCInst *MI, unsigned OpNo,
727-
const MCSubtargetInfo &STI,
728-
raw_ostream &O) {
729-
O << " wait_vm_vsrc:" << formatDec(MI->getOperand(OpNo).getImm());
730-
}
731-
732-
void AMDGPUInstPrinter::printWaitEXP(const MCInst *MI, unsigned OpNo,
733-
const MCSubtargetInfo &STI,
734-
raw_ostream &O) {
735-
O << " wait_exp:" << formatDec(MI->getOperand(OpNo).getImm());
736-
}
737-
738665
bool AMDGPUInstPrinter::needsImpliedVcc(const MCInstrDesc &Desc,
739666
unsigned OpNo) const {
740667
return OpNo == 0 && (Desc.TSFlags & SIInstrFlags::DPP) &&
@@ -1127,18 +1054,6 @@ void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo,
11271054
}
11281055
}
11291056

1130-
void AMDGPUInstPrinter::printDppRowMask(const MCInst *MI, unsigned OpNo,
1131-
const MCSubtargetInfo &STI,
1132-
raw_ostream &O) {
1133-
O << " row_mask:" << formatHex(MI->getOperand(OpNo).getImm());
1134-
}
1135-
1136-
void AMDGPUInstPrinter::printDppBankMask(const MCInst *MI, unsigned OpNo,
1137-
const MCSubtargetInfo &STI,
1138-
raw_ostream &O) {
1139-
O << " bank_mask:" << formatHex(MI->getOperand(OpNo).getImm());
1140-
}
1141-
11421057
void AMDGPUInstPrinter::printDppBoundCtrl(const MCInst *MI, unsigned OpNo,
11431058
const MCSubtargetInfo &STI,
11441059
raw_ostream &O) {
@@ -1782,14 +1697,13 @@ void AMDGPUInstPrinter::printEndpgm(const MCInst *MI, unsigned OpNo,
17821697
O << ' ' << formatDec(Imm);
17831698
}
17841699

1785-
void AMDGPUInstPrinter::printByteSel(const MCInst *MI, unsigned OpNo,
1786-
const MCSubtargetInfo &STI,
1787-
raw_ostream &O) {
1788-
uint8_t Imm = MI->getOperand(OpNo).getImm();
1789-
if (!Imm)
1790-
return;
1791-
1792-
O << " byte_sel:" << formatDec(Imm);
1700+
void AMDGPUInstPrinter::printNamedInt(const MCInst *MI, unsigned OpNo,
1701+
const MCSubtargetInfo &STI,
1702+
raw_ostream &O, StringRef Prefix,
1703+
bool PrintInHex, bool AlwaysPrint) {
1704+
int64_t V = MI->getOperand(OpNo).getImm();
1705+
if (AlwaysPrint || V != 0)
1706+
O << ' ' << Prefix << ':' << (PrintInHex ? formatHex(V) : formatDec(V));
17931707
}
17941708

17951709
#include "AMDGPUGenAsmWriter.inc"

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h

Lines changed: 3 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -48,24 +48,16 @@ class AMDGPUInstPrinter : public MCInstPrinter {
4848
void printFlatOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
4949
raw_ostream &O);
5050

51-
void printOffset0(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
52-
raw_ostream &O);
53-
void printOffset1(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
54-
raw_ostream &O);
5551
void printSMRDOffset8(const MCInst *MI, unsigned OpNo,
5652
const MCSubtargetInfo &STI, raw_ostream &O);
5753
void printSMEMOffset(const MCInst *MI, unsigned OpNo,
5854
const MCSubtargetInfo &STI, raw_ostream &O);
59-
void printSMEMOffsetMod(const MCInst *MI, unsigned OpNo,
60-
const MCSubtargetInfo &STI, raw_ostream &O);
6155
void printSMRDLiteralOffset(const MCInst *MI, unsigned OpNo,
6256
const MCSubtargetInfo &STI, raw_ostream &O);
6357
void printCPol(const MCInst *MI, unsigned OpNo,
6458
const MCSubtargetInfo &STI, raw_ostream &O);
6559
void printTH(const MCInst *MI, int64_t TH, int64_t Scope, raw_ostream &O);
6660
void printScope(int64_t Scope, raw_ostream &O);
67-
void printDMask(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
68-
raw_ostream &O);
6961
void printDim(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
7062
raw_ostream &O);
7163
void printR128A16(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
@@ -110,10 +102,6 @@ class AMDGPUInstPrinter : public MCInstPrinter {
110102
raw_ostream &O);
111103
void printDPPCtrl(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
112104
raw_ostream &O);
113-
void printDppRowMask(const MCInst *MI, unsigned OpNo,
114-
const MCSubtargetInfo &STI, raw_ostream &O);
115-
void printDppBankMask(const MCInst *MI, unsigned OpNo,
116-
const MCSubtargetInfo &STI, raw_ostream &O);
117105
void printDppBoundCtrl(const MCInst *MI, unsigned OpNo,
118106
const MCSubtargetInfo &STI, raw_ostream &O);
119107
void printDppFI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
@@ -154,21 +142,9 @@ class AMDGPUInstPrinter : public MCInstPrinter {
154142
const MCSubtargetInfo &STI, raw_ostream &O);
155143
void printBLGP(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
156144
raw_ostream &O);
157-
void printCBSZ(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
158-
raw_ostream &O);
159-
void printABID(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
160-
raw_ostream &O);
161145
bool needsImpliedVcc(const MCInstrDesc &Desc, unsigned OpNo) const;
162146
void printDefaultVccOperand(bool FirstOperand, const MCSubtargetInfo &STI,
163147
raw_ostream &O);
164-
void printWaitVDST(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
165-
raw_ostream &O);
166-
void printWaitEXP(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
167-
raw_ostream &O);
168-
void printWaitVAVDst(const MCInst *MI, unsigned OpNo,
169-
const MCSubtargetInfo &STI, raw_ostream &O);
170-
void printWaitVMVSrc(const MCInst *MI, unsigned OpNo,
171-
const MCSubtargetInfo &STI, raw_ostream &O);
172148

173149
void printExpSrcN(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
174150
raw_ostream &O, unsigned N);
@@ -182,8 +158,9 @@ class AMDGPUInstPrinter : public MCInstPrinter {
182158
const MCSubtargetInfo &STI, raw_ostream &O);
183159
void printExpTgt(const MCInst *MI, unsigned OpNo,
184160
const MCSubtargetInfo &STI, raw_ostream &O);
185-
void printByteSel(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
186-
raw_ostream &O);
161+
void printNamedInt(const MCInst *MI, unsigned OpNo,
162+
const MCSubtargetInfo &STI, raw_ostream &O,
163+
StringRef Prefix, bool PrintInHex, bool AlwaysPrint);
187164

188165
public:
189166
static void printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O,

‎llvm/lib/Target/AMDGPU/SIInstrInfo.td

Lines changed: 20 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1015,18 +1015,29 @@ def SDWAVopcDst : BoolRC {
10151015
let PrintMethod = "printVOPDst";
10161016
}
10171017

1018-
class NamedIntOperand<ValueType Type, string Prefix, bit Optional = 1,
1018+
class NamedIntOperand<ValueType Type, string prefix, bit Optional = 1,
10191019
string name = NAME>
10201020
: CustomOperand<Type, Optional, name> {
1021+
string Prefix = prefix;
1022+
10211023
let PredicateMethod =
10221024
"getPredicate([](const AMDGPUOperand &Op) -> bool { "#
10231025
"return Op.isImmTy(AMDGPUOperand::"#ImmTy#"); })";
1026+
10241027
string Validator = "[](int64_t V) { return true; }";
10251028
string ConvertMethod = "[](int64_t &V) { return "#Validator#"(V); }";
10261029
let ParserMethod =
10271030
"[this](OperandVector &Operands) -> ParseStatus { "#
10281031
"return parseIntWithPrefix(\""#Prefix#"\", Operands, "#
10291032
"AMDGPUOperand::"#ImmTy#", "#ConvertMethod#"); }";
1033+
1034+
bit PrintInHex = 0;
1035+
bit AlwaysPrint = 0;
1036+
let PrintMethod = "[this](const MCInst *MI, unsigned OpNo, "
1037+
"const MCSubtargetInfo &STI, raw_ostream &O) { "
1038+
"printNamedInt(MI, OpNo, STI, O, \""#Prefix#"\", "#
1039+
!if(PrintInHex, "true", "false")#", "#
1040+
!if(AlwaysPrint, "true", "false")#"); }";
10301041
}
10311042

10321043
class NamedBitOperand<string Id, string Name = NAME>
@@ -1065,6 +1076,7 @@ class ArrayOperand0<string Id, string Name = NAME>
10651076

10661077
let ImmTy = "ImmTyOffset" in
10671078
def flat_offset : CustomOperand<i32, 1, "FlatOffset">;
1079+
let PrintMethod = "printOffset" in
10681080
def Offset : NamedIntOperand<i32, "offset">;
10691081
let Validator = "isUInt<8>" in {
10701082
def Offset0 : NamedIntOperand<i32, "offset0">;
@@ -1103,6 +1115,7 @@ def exp_vm : NamedBitOperand<"vm", "ExpVM">;
11031115

11041116
def FORMAT : CustomOperand<i8>;
11051117

1118+
let PrintInHex = 1 in
11061119
def DMask : NamedIntOperand<i16, "dmask">;
11071120

11081121
def Dim : CustomOperand<i8, /*optional=*/1>;
@@ -1123,16 +1136,18 @@ def IndexKey8bit : CustomOperand<i32, 1>;
11231136
def dpp8 : CustomOperand<i32, 0, "DPP8">;
11241137
def dpp_ctrl : CustomOperand<i32, 0, "DPPCtrl">;
11251138

1126-
let DefaultValue = "0xf" in {
1139+
let DefaultValue = "0xf", PrintInHex = 1, AlwaysPrint = 1 in {
11271140
def DppRowMask : NamedIntOperand<i32, "row_mask">;
11281141
def DppBankMask : NamedIntOperand<i32, "bank_mask">;
11291142
}
11301143
def DppBoundCtrl : NamedIntOperand<i1, "bound_ctrl"> {
11311144
let ConvertMethod = "[this] (int64_t &BC) -> bool { return convertDppBoundCtrl(BC); }";
1145+
let PrintMethod = "printDppBoundCtrl";
11321146
}
11331147

1134-
let DecoderMethod = "decodeDpp8FI" in
1148+
let DecoderMethod = "decodeDpp8FI", PrintMethod = "printDppFI" in
11351149
def Dpp8FI : NamedIntOperand<i32, "fi", 1, "DppFI">;
1150+
let PrintMethod = "printDppFI" in
11361151
def Dpp16FI : NamedIntOperand<i32, "fi", 1, "DppFI">;
11371152

11381153
def blgp : CustomOperand<i32, 1, "BLGP">;
@@ -1146,6 +1161,7 @@ def hwreg : CustomOperand<i32, 0, "Hwreg">;
11461161

11471162
def exp_tgt : CustomOperand<i32, 0, "ExpTgt">;
11481163

1164+
let AlwaysPrint = 1 in {
11491165
def WaitVDST : NamedIntOperand<i8, "wait_vdst"> {
11501166
let Validator = "isUInt<4>";
11511167
}
@@ -1158,6 +1174,7 @@ def WaitVAVDst : NamedIntOperand<i8, "wait_va_vdst"> {
11581174
def WaitVMVSrc : NamedIntOperand<i8, "wait_vm_vsrc"> {
11591175
let Validator = "isUInt<1>";
11601176
}
1177+
} // End AlwaysPrint = 1
11611178

11621179
def ByteSel : NamedIntOperand<i8, "byte_sel"> {
11631180
let Validator = "isUInt<2>";

‎llvm/lib/Target/AMDGPU/SMInstructions.td

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,10 @@ def smrd_offset_8 : ImmOperand<i32, "SMRDOffset8", 1>;
1111
let EncoderMethod = "getSMEMOffsetEncoding",
1212
DecoderMethod = "decodeSMEMOffset" in {
1313
def SMEMOffset : ImmOperand<i32, "SMEMOffset", 1>;
14-
def SMEMOffsetMod : NamedIntOperand<i32, "offset", 0>;
14+
def SMEMOffsetMod : NamedIntOperand<i32, "offset", 0> {
15+
let AlwaysPrint = 1;
16+
let PrintInHex = 1;
17+
}
1518
def OptSMEMOffsetMod : NamedIntOperand<i32, "offset"> {
1619
let ImmTy = SMEMOffsetMod.ImmTy;
1720
let PredicateMethod = SMEMOffsetMod.PredicateMethod;

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