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[X86] Fold (v2i64 (scalar_to_vector (i64 (bitcast (double))))) -> (bitcast (v2f64 scalar_to_vector))
This can occur more frequently after the MMX retirement if anyone is still using MMX intrinsics that now wrap to SSE
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2 files changed

+11
-6
lines changed

2 files changed

+11
-6
lines changed

llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 10 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -58359,10 +58359,16 @@ static SDValue combineScalarToVector(SDNode *N, SelectionDAG &DAG,
5835958359
DAG.getZExtOrTrunc(ZeroExt, DL, MVT::i32))));
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}
5836158361

58362-
// Combine (v2i64 (scalar_to_vector (i64 (bitconvert (mmx))))) to MOVQ2DQ.
58363-
if (VT == MVT::v2i64 && Src.getOpcode() == ISD::BITCAST &&
58364-
Src.getOperand(0).getValueType() == MVT::x86mmx)
58365-
return DAG.getNode(X86ISD::MOVQ2DQ, DL, VT, Src.getOperand(0));
58362+
if (VT == MVT::v2i64 && Src.getOpcode() == ISD::BITCAST) {
58363+
SDValue SrcOp = Src.getOperand(0);
58364+
// Combine (v2i64 (scalar_to_vector (i64 (bitcast (double))))) to MOVQ.
58365+
if (SrcOp.getValueType() == MVT::f64)
58366+
return DAG.getBitcast(
58367+
VT, DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, SrcOp));
58368+
// Combine (v2i64 (scalar_to_vector (i64 (bitcast (mmx))))) to MOVQ2DQ.
58369+
if (SrcOp.getValueType() == MVT::x86mmx)
58370+
return DAG.getNode(X86ISD::MOVQ2DQ, DL, VT, SrcOp);
58371+
}
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5836758373
// See if we're broadcasting the scalar value, in which case just reuse that.
5836858374
// Ensure the same SDValue from the SDNode use is being used.

llvm/test/CodeGen/X86/mmx-cvt.ll

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -287,8 +287,7 @@ define noundef <2 x i64> @cvt_f64_v2i64(double %a0) {
287287
;
288288
; X64-LABEL: cvt_f64_v2i64:
289289
; X64: # %bb.0:
290-
; X64-NEXT: movq %xmm0, %rax
291-
; X64-NEXT: movq %rax, %xmm0
290+
; X64-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
292291
; X64-NEXT: retq
293292
%bc = bitcast double %a0 to <1 x i64>
294293
%r = shufflevector <1 x i64> %bc, <1 x i64> zeroinitializer, <2 x i32> <i32 0, i32 1>

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