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davemgreendavemgreen
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[VectorCombine] Add Cmp and Select for shuffleToIdentity (#92794)
Other than some additional checks needed for compare predicates and selects with scalar condition operands, these are relatively simple additions to what already exists.
1 parent 17ecd23 commit 516a9f5

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2 files changed

+21
-28
lines changed

2 files changed

+21
-28
lines changed

‎llvm/lib/Transforms/Vectorize/VectorCombine.cpp

Lines changed: 17 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1742,6 +1742,10 @@ static Value *generateNewInstTree(ArrayRef<InstLane> Item, FixedVectorType *Ty,
17421742
if (auto *BI = dyn_cast<BinaryOperator>(I))
17431743
return Builder.CreateBinOp((Instruction::BinaryOps)BI->getOpcode(), Ops[0],
17441744
Ops[1]);
1745+
if (auto *CI = dyn_cast<CmpInst>(I))
1746+
return Builder.CreateCmp(CI->getPredicate(), Ops[0], Ops[1]);
1747+
if (auto *SI = dyn_cast<SelectInst>(I))
1748+
return Builder.CreateSelect(Ops[0], Ops[1], Ops[2], "", SI);
17451749
if (II)
17461750
return Builder.CreateIntrinsic(DstTy, II->getIntrinsicID(), Ops);
17471751
assert(isa<UnaryInstruction>(I) && "Unexpected instruction type in Generate");
@@ -1821,6 +1825,12 @@ bool VectorCombine::foldShuffleToIdentity(Instruction &I) {
18211825
return false;
18221826
if (V->getValueID() != FrontV->getValueID())
18231827
return false;
1828+
if (auto *CI = dyn_cast<CmpInst>(V))
1829+
if (CI->getPredicate() != cast<CmpInst>(FrontV)->getPredicate())
1830+
return false;
1831+
if (auto *SI = dyn_cast<SelectInst>(V))
1832+
if (!isa<VectorType>(SI->getOperand(0)->getType()))
1833+
return false;
18241834
if (isa<CallInst>(V) && !isa<IntrinsicInst>(V))
18251835
return false;
18261836
auto *II = dyn_cast<IntrinsicInst>(V);
@@ -1832,12 +1842,17 @@ bool VectorCombine::foldShuffleToIdentity(Instruction &I) {
18321842

18331843
// Check the operator is one that we support. We exclude div/rem in case
18341844
// they hit UB from poison lanes.
1835-
if (isa<BinaryOperator>(FrontV) &&
1836-
!cast<BinaryOperator>(FrontV)->isIntDivRem()) {
1845+
if ((isa<BinaryOperator>(FrontV) &&
1846+
!cast<BinaryOperator>(FrontV)->isIntDivRem()) ||
1847+
isa<CmpInst>(FrontV)) {
18371848
Worklist.push_back(generateInstLaneVectorFromOperand(Item, 0));
18381849
Worklist.push_back(generateInstLaneVectorFromOperand(Item, 1));
18391850
} else if (isa<UnaryOperator>(FrontV)) {
18401851
Worklist.push_back(generateInstLaneVectorFromOperand(Item, 0));
1852+
} else if (isa<SelectInst>(FrontV)) {
1853+
Worklist.push_back(generateInstLaneVectorFromOperand(Item, 0));
1854+
Worklist.push_back(generateInstLaneVectorFromOperand(Item, 1));
1855+
Worklist.push_back(generateInstLaneVectorFromOperand(Item, 2));
18411856
} else if (auto *II = dyn_cast<IntrinsicInst>(FrontV);
18421857
II && isTriviallyVectorizable(II->getIntrinsicID())) {
18431858
for (unsigned Op = 0, E = II->getNumOperands() - 1; Op < E; Op++) {

‎llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll

Lines changed: 4 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -419,19 +419,8 @@ define <8 x i8> @extrause_shuffle(<8 x i8> %a, <8 x i8> %b) {
419419

420420
define <8 x i8> @icmpsel(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c, <8 x i8> %d) {
421421
; CHECK-LABEL: @icmpsel(
422-
; CHECK-NEXT: [[AB:%.*]] = shufflevector <8 x i8> [[A:%.*]], <8 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
423-
; CHECK-NEXT: [[AT:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> poison, <4 x i32> <i32 7, i32 6, i32 5, i32 4>
424-
; CHECK-NEXT: [[BB:%.*]] = shufflevector <8 x i8> [[B:%.*]], <8 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
425-
; CHECK-NEXT: [[BT:%.*]] = shufflevector <8 x i8> [[B]], <8 x i8> poison, <4 x i32> <i32 7, i32 6, i32 5, i32 4>
426-
; CHECK-NEXT: [[CB:%.*]] = shufflevector <8 x i8> [[C:%.*]], <8 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
427-
; CHECK-NEXT: [[CT:%.*]] = shufflevector <8 x i8> [[C]], <8 x i8> poison, <4 x i32> <i32 7, i32 6, i32 5, i32 4>
428-
; CHECK-NEXT: [[DB:%.*]] = shufflevector <8 x i8> [[D:%.*]], <8 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
429-
; CHECK-NEXT: [[DT:%.*]] = shufflevector <8 x i8> [[D]], <8 x i8> poison, <4 x i32> <i32 7, i32 6, i32 5, i32 4>
430-
; CHECK-NEXT: [[ABT1:%.*]] = icmp slt <4 x i8> [[AT]], [[BT]]
431-
; CHECK-NEXT: [[ABB1:%.*]] = icmp slt <4 x i8> [[AB]], [[BB]]
432-
; CHECK-NEXT: [[ABT:%.*]] = select <4 x i1> [[ABT1]], <4 x i8> [[CT]], <4 x i8> [[DT]]
433-
; CHECK-NEXT: [[ABB:%.*]] = select <4 x i1> [[ABB1]], <4 x i8> [[CB]], <4 x i8> [[DB]]
434-
; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i8> [[ABT]], <4 x i8> [[ABB]], <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
422+
; CHECK-NEXT: [[TMP1:%.*]] = icmp slt <8 x i8> [[A:%.*]], [[B:%.*]]
423+
; CHECK-NEXT: [[R:%.*]] = select <8 x i1> [[TMP1]], <8 x i8> [[C:%.*]], <8 x i8> [[D:%.*]]
435424
; CHECK-NEXT: ret <8 x i8> [[R]]
436425
;
437426
%ab = shufflevector <8 x i8> %a, <8 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
@@ -485,19 +474,8 @@ define <8 x i8> @icmpsel_diffentcond(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c, <8 x
485474

486475
define <8 x i8> @fcmpsel(<8 x half> %a, <8 x half> %b, <8 x i8> %c, <8 x i8> %d) {
487476
; CHECK-LABEL: @fcmpsel(
488-
; CHECK-NEXT: [[AB:%.*]] = shufflevector <8 x half> [[A:%.*]], <8 x half> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
489-
; CHECK-NEXT: [[AT:%.*]] = shufflevector <8 x half> [[A]], <8 x half> poison, <4 x i32> <i32 7, i32 6, i32 5, i32 4>
490-
; CHECK-NEXT: [[BB:%.*]] = shufflevector <8 x half> [[B:%.*]], <8 x half> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
491-
; CHECK-NEXT: [[BT:%.*]] = shufflevector <8 x half> [[B]], <8 x half> poison, <4 x i32> <i32 7, i32 6, i32 5, i32 4>
492-
; CHECK-NEXT: [[CB:%.*]] = shufflevector <8 x i8> [[C:%.*]], <8 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
493-
; CHECK-NEXT: [[CT:%.*]] = shufflevector <8 x i8> [[C]], <8 x i8> poison, <4 x i32> <i32 7, i32 6, i32 5, i32 4>
494-
; CHECK-NEXT: [[DB:%.*]] = shufflevector <8 x i8> [[D:%.*]], <8 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
495-
; CHECK-NEXT: [[DT:%.*]] = shufflevector <8 x i8> [[D]], <8 x i8> poison, <4 x i32> <i32 7, i32 6, i32 5, i32 4>
496-
; CHECK-NEXT: [[ABT1:%.*]] = fcmp olt <4 x half> [[AT]], [[BT]]
497-
; CHECK-NEXT: [[ABB1:%.*]] = fcmp olt <4 x half> [[AB]], [[BB]]
498-
; CHECK-NEXT: [[ABT:%.*]] = select <4 x i1> [[ABT1]], <4 x i8> [[CT]], <4 x i8> [[DT]]
499-
; CHECK-NEXT: [[ABB:%.*]] = select <4 x i1> [[ABB1]], <4 x i8> [[CB]], <4 x i8> [[DB]]
500-
; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i8> [[ABT]], <4 x i8> [[ABB]], <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
477+
; CHECK-NEXT: [[TMP1:%.*]] = fcmp olt <8 x half> [[A:%.*]], [[B:%.*]]
478+
; CHECK-NEXT: [[R:%.*]] = select <8 x i1> [[TMP1]], <8 x i8> [[C:%.*]], <8 x i8> [[D:%.*]]
501479
; CHECK-NEXT: ret <8 x i8> [[R]]
502480
;
503481
%ab = shufflevector <8 x half> %a, <8 x half> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>

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