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‎llvm/test/CodeGen/X86/tail-dup-pred-size-limit.ll

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; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -mtriple=x86_64-unknown-linux-gnu -stop-after=early-tailduplication < %s | FileCheck %s -check-prefix=LIMIT
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; RUN: llc -mtriple=x86_64-unknown-linux-gnu -stop-after=early-tailduplication < %s | FileCheck %s -check-prefix=NOLIMIT
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define i32 @foo(ptr %0, i32 %1) {
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; LIMIT-LABEL: name: foo
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; LIMIT: bb.0 (%ir-block.2):
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; LIMIT-NEXT: successors: %bb.1(0x20000000), %bb.2(0x20000000), %bb.3(0x20000000), %bb.4(0x20000000)
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; LIMIT-NEXT: liveins: $rdi, $esi
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; LIMIT-NEXT: {{ $}}
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; LIMIT-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $esi
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; LIMIT-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
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; LIMIT-NEXT: [[SHR32ri:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 1, implicit-def dead $eflags
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; LIMIT-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[SHR32ri]], 7, implicit-def dead $eflags
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; LIMIT-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, killed [[AND32ri]], %subreg.sub_32bit
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; LIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG]], %jump-table.0, $noreg :: (load (s64) from jump-table)
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; LIMIT-NEXT: {{ $}}
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; LIMIT-NEXT: bb.1 (%ir-block.5):
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; LIMIT-NEXT: successors: %bb.7(0x20000000), %bb.8(0x20000000), %bb.9(0x20000000), %bb.10(0x20000000)
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; LIMIT-NEXT: {{ $}}
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; LIMIT-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY1]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.0)
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; LIMIT-NEXT: [[SHR32ri1:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags
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; LIMIT-NEXT: [[AND32ri1:%[0-9]+]]:gr32 = AND32ri [[SHR32ri1]], 7, implicit-def dead $eflags
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; LIMIT-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri1]], %subreg.sub_32bit
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; LIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG1]], %jump-table.1, $noreg :: (load (s64) from jump-table)
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; LIMIT-NEXT: {{ $}}
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; LIMIT-NEXT: bb.2 (%ir-block.7):
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; LIMIT-NEXT: successors: %bb.7(0x20000000), %bb.8(0x20000000), %bb.9(0x20000000), %bb.10(0x20000000)
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; LIMIT-NEXT: {{ $}}
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; LIMIT-NEXT: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm [[COPY1]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.0)
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; LIMIT-NEXT: [[SHR32ri2:%[0-9]+]]:gr32 = SHR32ri [[MOV32rm1]], 1, implicit-def dead $eflags
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; LIMIT-NEXT: [[SHR32ri3:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags
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; LIMIT-NEXT: [[AND32ri2:%[0-9]+]]:gr32 = AND32ri [[SHR32ri3]], 7, implicit-def dead $eflags
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; LIMIT-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri2]], %subreg.sub_32bit
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; LIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG2]], %jump-table.1, $noreg :: (load (s64) from jump-table)
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; LIMIT-NEXT: {{ $}}
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; LIMIT-NEXT: bb.3 (%ir-block.10):
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; LIMIT-NEXT: successors: %bb.7(0x20000000), %bb.8(0x20000000), %bb.9(0x20000000), %bb.10(0x20000000)
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; LIMIT-NEXT: {{ $}}
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; LIMIT-NEXT: [[MOV32rm2:%[0-9]+]]:gr32 = MOV32rm [[COPY1]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.0)
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; LIMIT-NEXT: [[SHR32ri4:%[0-9]+]]:gr32 = SHR32ri [[MOV32rm2]], 2, implicit-def dead $eflags
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; LIMIT-NEXT: [[SHR32ri5:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags
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; LIMIT-NEXT: [[AND32ri3:%[0-9]+]]:gr32 = AND32ri [[SHR32ri5]], 7, implicit-def dead $eflags
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; LIMIT-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri3]], %subreg.sub_32bit
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; LIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG3]], %jump-table.1, $noreg :: (load (s64) from jump-table)
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; LIMIT-NEXT: {{ $}}
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; LIMIT-NEXT: bb.4 (%ir-block.13):
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; LIMIT-NEXT: successors: %bb.7(0x20000000), %bb.8(0x20000000), %bb.9(0x20000000), %bb.10(0x20000000)
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; LIMIT-NEXT: {{ $}}
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; LIMIT-NEXT: [[MOV32rm3:%[0-9]+]]:gr32 = MOV32rm [[COPY1]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.0)
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; LIMIT-NEXT: [[SHR32ri6:%[0-9]+]]:gr32 = SHR32ri [[MOV32rm3]], 3, implicit-def dead $eflags
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; LIMIT-NEXT: [[SHR32ri7:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags
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; LIMIT-NEXT: [[AND32ri4:%[0-9]+]]:gr32 = AND32ri [[SHR32ri7]], 7, implicit-def dead $eflags
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; LIMIT-NEXT: [[SUBREG_TO_REG4:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri4]], %subreg.sub_32bit
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; LIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG4]], %jump-table.1, $noreg :: (load (s64) from jump-table)
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; LIMIT-NEXT: {{ $}}
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; LIMIT-NEXT: bb.5.default.unreachable2:
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; LIMIT-NEXT: successors:
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; LIMIT-NEXT: {{ $}}
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; LIMIT-NEXT: {{ $}}
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; LIMIT-NEXT: bb.7 (%ir-block.20):
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; LIMIT-NEXT: successors: %bb.11(0x80000000)
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; LIMIT-NEXT: {{ $}}
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; LIMIT-NEXT: [[PHI:%[0-9]+]]:gr32 = PHI [[SHR32ri6]], %bb.4, [[SHR32ri4]], %bb.3, [[SHR32ri2]], %bb.2, [[MOV32rm]], %bb.1
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; LIMIT-NEXT: [[MOV32rm4:%[0-9]+]]:gr32 = MOV32rm [[COPY1]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.0)
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; LIMIT-NEXT: JMP_1 %bb.11
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; LIMIT-NEXT: {{ $}}
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; LIMIT-NEXT: bb.8 (%ir-block.22):
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; LIMIT-NEXT: successors: %bb.11(0x80000000)
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; LIMIT-NEXT: {{ $}}
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; LIMIT-NEXT: [[PHI1:%[0-9]+]]:gr32 = PHI [[SHR32ri6]], %bb.4, [[SHR32ri4]], %bb.3, [[SHR32ri2]], %bb.2, [[MOV32rm]], %bb.1
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; LIMIT-NEXT: [[MOV32rm5:%[0-9]+]]:gr32 = MOV32rm [[COPY1]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.0)
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; LIMIT-NEXT: [[SHR32ri8:%[0-9]+]]:gr32 = SHR32ri [[MOV32rm5]], 1, implicit-def dead $eflags
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; LIMIT-NEXT: JMP_1 %bb.11
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; LIMIT-NEXT: {{ $}}
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; LIMIT-NEXT: bb.9 (%ir-block.25):
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; LIMIT-NEXT: successors: %bb.11(0x80000000)
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; LIMIT-NEXT: {{ $}}
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; LIMIT-NEXT: [[PHI2:%[0-9]+]]:gr32 = PHI [[SHR32ri6]], %bb.4, [[SHR32ri4]], %bb.3, [[SHR32ri2]], %bb.2, [[MOV32rm]], %bb.1
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; LIMIT-NEXT: [[MOV32rm6:%[0-9]+]]:gr32 = MOV32rm [[COPY1]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.0)
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; LIMIT-NEXT: [[SHR32ri9:%[0-9]+]]:gr32 = SHR32ri [[MOV32rm6]], 2, implicit-def dead $eflags
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; LIMIT-NEXT: JMP_1 %bb.11
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; LIMIT-NEXT: {{ $}}
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; LIMIT-NEXT: bb.10 (%ir-block.28):
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; LIMIT-NEXT: successors: %bb.11(0x80000000)
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; LIMIT-NEXT: {{ $}}
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; LIMIT-NEXT: [[PHI3:%[0-9]+]]:gr32 = PHI [[SHR32ri6]], %bb.4, [[SHR32ri4]], %bb.3, [[SHR32ri2]], %bb.2, [[MOV32rm]], %bb.1
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; LIMIT-NEXT: [[MOV32rm7:%[0-9]+]]:gr32 = MOV32rm [[COPY1]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.0)
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; LIMIT-NEXT: [[SHR32ri10:%[0-9]+]]:gr32 = SHR32ri [[MOV32rm7]], 6, implicit-def dead $eflags
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; LIMIT-NEXT: {{ $}}
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; LIMIT-NEXT: bb.11 (%ir-block.31):
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; LIMIT-NEXT: [[PHI4:%[0-9]+]]:gr32 = PHI [[PHI3]], %bb.10, [[PHI2]], %bb.9, [[PHI1]], %bb.8, [[PHI]], %bb.7
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; LIMIT-NEXT: [[PHI5:%[0-9]+]]:gr32 = PHI [[SHR32ri10]], %bb.10, [[SHR32ri9]], %bb.9, [[SHR32ri8]], %bb.8, [[MOV32rm4]], %bb.7
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; LIMIT-NEXT: [[OR32rr:%[0-9]+]]:gr32 = OR32rr [[PHI5]], [[PHI4]], implicit-def dead $eflags
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; LIMIT-NEXT: $eax = COPY [[OR32rr]]
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; LIMIT-NEXT: RET 0, $eax
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;
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; NOLIMIT-LABEL: name: foo
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; NOLIMIT: bb.0 (%ir-block.2):
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; NOLIMIT-NEXT: successors: %bb.1(0x20000000), %bb.2(0x20000000), %bb.3(0x20000000), %bb.4(0x20000000)
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; NOLIMIT-NEXT: liveins: $rdi, $esi
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; NOLIMIT-NEXT: {{ $}}
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; NOLIMIT-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $esi
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; NOLIMIT-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
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; NOLIMIT-NEXT: [[SHR32ri:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 1, implicit-def dead $eflags
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; NOLIMIT-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[SHR32ri]], 7, implicit-def dead $eflags
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; NOLIMIT-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, killed [[AND32ri]], %subreg.sub_32bit
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; NOLIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG]], %jump-table.0, $noreg :: (load (s64) from jump-table)
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; NOLIMIT-NEXT: {{ $}}
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; NOLIMIT-NEXT: bb.1 (%ir-block.5):
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; NOLIMIT-NEXT: successors: %bb.7(0x20000000), %bb.8(0x20000000), %bb.9(0x20000000), %bb.10(0x20000000)
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; NOLIMIT-NEXT: {{ $}}
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; NOLIMIT-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[COPY1]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.0)
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; NOLIMIT-NEXT: [[SHR32ri1:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags
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; NOLIMIT-NEXT: [[AND32ri1:%[0-9]+]]:gr32 = AND32ri [[SHR32ri1]], 7, implicit-def dead $eflags
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; NOLIMIT-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri1]], %subreg.sub_32bit
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; NOLIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG1]], %jump-table.1, $noreg :: (load (s64) from jump-table)
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; NOLIMIT-NEXT: {{ $}}
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; NOLIMIT-NEXT: bb.2 (%ir-block.7):
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; NOLIMIT-NEXT: successors: %bb.7(0x20000000), %bb.8(0x20000000), %bb.9(0x20000000), %bb.10(0x20000000)
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; NOLIMIT-NEXT: {{ $}}
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; NOLIMIT-NEXT: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm [[COPY1]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.0)
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; NOLIMIT-NEXT: [[SHR32ri2:%[0-9]+]]:gr32 = SHR32ri [[MOV32rm1]], 1, implicit-def dead $eflags
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; NOLIMIT-NEXT: [[SHR32ri3:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags
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; NOLIMIT-NEXT: [[AND32ri2:%[0-9]+]]:gr32 = AND32ri [[SHR32ri3]], 7, implicit-def dead $eflags
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; NOLIMIT-NEXT: [[SUBREG_TO_REG2:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri2]], %subreg.sub_32bit
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; NOLIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG2]], %jump-table.1, $noreg :: (load (s64) from jump-table)
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; NOLIMIT-NEXT: {{ $}}
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; NOLIMIT-NEXT: bb.3 (%ir-block.10):
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; NOLIMIT-NEXT: successors: %bb.7(0x20000000), %bb.8(0x20000000), %bb.9(0x20000000), %bb.10(0x20000000)
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; NOLIMIT-NEXT: {{ $}}
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; NOLIMIT-NEXT: [[MOV32rm2:%[0-9]+]]:gr32 = MOV32rm [[COPY1]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.0)
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; NOLIMIT-NEXT: [[SHR32ri4:%[0-9]+]]:gr32 = SHR32ri [[MOV32rm2]], 2, implicit-def dead $eflags
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; NOLIMIT-NEXT: [[SHR32ri5:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags
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; NOLIMIT-NEXT: [[AND32ri3:%[0-9]+]]:gr32 = AND32ri [[SHR32ri5]], 7, implicit-def dead $eflags
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; NOLIMIT-NEXT: [[SUBREG_TO_REG3:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri3]], %subreg.sub_32bit
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; NOLIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG3]], %jump-table.1, $noreg :: (load (s64) from jump-table)
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; NOLIMIT-NEXT: {{ $}}
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; NOLIMIT-NEXT: bb.4 (%ir-block.13):
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; NOLIMIT-NEXT: successors: %bb.7(0x20000000), %bb.8(0x20000000), %bb.9(0x20000000), %bb.10(0x20000000)
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; NOLIMIT-NEXT: {{ $}}
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; NOLIMIT-NEXT: [[MOV32rm3:%[0-9]+]]:gr32 = MOV32rm [[COPY1]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.0)
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; NOLIMIT-NEXT: [[SHR32ri6:%[0-9]+]]:gr32 = SHR32ri [[MOV32rm3]], 3, implicit-def dead $eflags
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; NOLIMIT-NEXT: [[SHR32ri7:%[0-9]+]]:gr32 = SHR32ri [[COPY]], 2, implicit-def dead $eflags
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; NOLIMIT-NEXT: [[AND32ri4:%[0-9]+]]:gr32 = AND32ri [[SHR32ri7]], 7, implicit-def dead $eflags
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; NOLIMIT-NEXT: [[SUBREG_TO_REG4:%[0-9]+]]:gr64_nosp = SUBREG_TO_REG 0, [[AND32ri4]], %subreg.sub_32bit
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; NOLIMIT-NEXT: JMP64m $noreg, 8, [[SUBREG_TO_REG4]], %jump-table.1, $noreg :: (load (s64) from jump-table)
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; NOLIMIT-NEXT: {{ $}}
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; NOLIMIT-NEXT: bb.5.default.unreachable2:
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; NOLIMIT-NEXT: successors:
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; NOLIMIT-NEXT: {{ $}}
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; NOLIMIT-NEXT: {{ $}}
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; NOLIMIT-NEXT: bb.7 (%ir-block.20):
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; NOLIMIT-NEXT: successors: %bb.11(0x80000000)
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; NOLIMIT-NEXT: {{ $}}
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; NOLIMIT-NEXT: [[PHI:%[0-9]+]]:gr32 = PHI [[SHR32ri6]], %bb.4, [[SHR32ri4]], %bb.3, [[SHR32ri2]], %bb.2, [[MOV32rm]], %bb.1
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; NOLIMIT-NEXT: [[MOV32rm4:%[0-9]+]]:gr32 = MOV32rm [[COPY1]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.0)
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; NOLIMIT-NEXT: JMP_1 %bb.11
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; NOLIMIT-NEXT: {{ $}}
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; NOLIMIT-NEXT: bb.8 (%ir-block.22):
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; NOLIMIT-NEXT: successors: %bb.11(0x80000000)
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; NOLIMIT-NEXT: {{ $}}
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; NOLIMIT-NEXT: [[PHI1:%[0-9]+]]:gr32 = PHI [[SHR32ri6]], %bb.4, [[SHR32ri4]], %bb.3, [[SHR32ri2]], %bb.2, [[MOV32rm]], %bb.1
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; NOLIMIT-NEXT: [[MOV32rm5:%[0-9]+]]:gr32 = MOV32rm [[COPY1]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.0)
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; NOLIMIT-NEXT: [[SHR32ri8:%[0-9]+]]:gr32 = SHR32ri [[MOV32rm5]], 1, implicit-def dead $eflags
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; NOLIMIT-NEXT: JMP_1 %bb.11
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; NOLIMIT-NEXT: {{ $}}
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; NOLIMIT-NEXT: bb.9 (%ir-block.25):
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; NOLIMIT-NEXT: successors: %bb.11(0x80000000)
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; NOLIMIT-NEXT: {{ $}}
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; NOLIMIT-NEXT: [[PHI2:%[0-9]+]]:gr32 = PHI [[SHR32ri6]], %bb.4, [[SHR32ri4]], %bb.3, [[SHR32ri2]], %bb.2, [[MOV32rm]], %bb.1
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; NOLIMIT-NEXT: [[MOV32rm6:%[0-9]+]]:gr32 = MOV32rm [[COPY1]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.0)
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; NOLIMIT-NEXT: [[SHR32ri9:%[0-9]+]]:gr32 = SHR32ri [[MOV32rm6]], 2, implicit-def dead $eflags
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; NOLIMIT-NEXT: JMP_1 %bb.11
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; NOLIMIT-NEXT: {{ $}}
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; NOLIMIT-NEXT: bb.10 (%ir-block.28):
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; NOLIMIT-NEXT: successors: %bb.11(0x80000000)
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; NOLIMIT-NEXT: {{ $}}
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; NOLIMIT-NEXT: [[PHI3:%[0-9]+]]:gr32 = PHI [[SHR32ri6]], %bb.4, [[SHR32ri4]], %bb.3, [[SHR32ri2]], %bb.2, [[MOV32rm]], %bb.1
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; NOLIMIT-NEXT: [[MOV32rm7:%[0-9]+]]:gr32 = MOV32rm [[COPY1]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.0)
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; NOLIMIT-NEXT: [[SHR32ri10:%[0-9]+]]:gr32 = SHR32ri [[MOV32rm7]], 6, implicit-def dead $eflags
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; NOLIMIT-NEXT: {{ $}}
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; NOLIMIT-NEXT: bb.11 (%ir-block.31):
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; NOLIMIT-NEXT: [[PHI4:%[0-9]+]]:gr32 = PHI [[PHI3]], %bb.10, [[PHI2]], %bb.9, [[PHI1]], %bb.8, [[PHI]], %bb.7
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; NOLIMIT-NEXT: [[PHI5:%[0-9]+]]:gr32 = PHI [[SHR32ri10]], %bb.10, [[SHR32ri9]], %bb.9, [[SHR32ri8]], %bb.8, [[MOV32rm4]], %bb.7
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; NOLIMIT-NEXT: [[OR32rr:%[0-9]+]]:gr32 = OR32rr [[PHI5]], [[PHI4]], implicit-def dead $eflags
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; NOLIMIT-NEXT: $eax = COPY [[OR32rr]]
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; NOLIMIT-NEXT: RET 0, $eax
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%3 = lshr i32 %1, 1
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%4 = and i32 %3, 7
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switch i32 %4, label %default.unreachable2 [
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i32 0, label %5
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i32 1, label %7
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i32 2, label %10
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i32 3, label %13
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]
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5: ; preds = %2
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%6 = load i32, ptr %0, align 4
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br label %16
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7: ; preds = %2
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%8 = load i32, ptr %0, align 4
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%9 = lshr i32 %8, 1
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br label %16
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10: ; preds = %2
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%11 = load i32, ptr %0, align 4
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%12 = lshr i32 %11, 2
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br label %16
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13: ; preds = %2
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%14 = load i32, ptr %0, align 4
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%15 = lshr i32 %14, 3
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br label %16
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default.unreachable2: ; preds = %16, %2
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unreachable
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16: ; preds = %13, %10, %7, %5
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%17 = phi i32 [ %15, %13 ], [ %12, %10 ], [ %9, %7 ], [ %6, %5 ]
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%18 = lshr i32 %1, 2
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%19 = and i32 %18, 7
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switch i32 %19, label %default.unreachable2 [
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i32 0, label %20
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i32 1, label %22
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i32 2, label %25
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i32 3, label %28
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]
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20: ; preds = %16
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%21 = load i32, ptr %0, align 4
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br label %31
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22: ; preds = %16
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%23 = load i32, ptr %0, align 4
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%24 = lshr i32 %23, 1
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br label %31
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25: ; preds = %16
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%26 = load i32, ptr %0, align 4
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%27 = lshr i32 %26, 2
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br label %31
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28: ; preds = %16
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%29 = load i32, ptr %0, align 4
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%30 = lshr i32 %29, 6
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br label %31
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31: ; preds = %28, %25, %22, %20
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%32 = phi i32 [ %30, %28 ], [ %27, %25 ], [ %24, %22 ], [ %21, %20 ]
252+
%33 = or i32 %32, %17
253+
ret i32 %33
254+
}

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