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[RISCV] Add tests for vwsll for extends > .vf2. NFC
These cannot be picked up by TableGen patterns alone and need to be handled by combineBinOp_VLToVWBinOp_VL
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‎llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll

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@@ -627,3 +627,259 @@ define <vscale x 8 x i16> @vwsll_vi_nxv8i16(<vscale x 8 x i8> %a) {
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%z = shl <vscale x 8 x i16> %x, splat (i16 2)
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ret <vscale x 8 x i16> %z
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}
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; ==============================================================================
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; i8 -> i64
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; ==============================================================================
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define <vscale x 2 x i64> @vwsll_vv_nxv2i64_nxv2i8_sext(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) {
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; CHECK-LABEL: vwsll_vv_nxv2i64_nxv2i8_sext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
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; CHECK-NEXT: vzext.vf8 v10, v8
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; CHECK-NEXT: vsext.vf8 v12, v9
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; CHECK-NEXT: vsll.vv v8, v10, v12
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; CHECK-NEXT: ret
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;
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; CHECK-ZVBB-LABEL: vwsll_vv_nxv2i64_nxv2i8_sext:
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; CHECK-ZVBB: # %bb.0:
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; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma
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; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
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; CHECK-ZVBB-NEXT: vsext.vf8 v12, v9
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; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12
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; CHECK-ZVBB-NEXT: ret
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%x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
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%y = sext <vscale x 2 x i8> %b to <vscale x 2 x i64>
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%z = shl <vscale x 2 x i64> %x, %y
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ret <vscale x 2 x i64> %z
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}
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define <vscale x 2 x i64> @vwsll_vv_nxv2i64_nxv2i8_zext(<vscale x 2 x i8> %a, <vscale x 2 x i8> %b) {
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; CHECK-LABEL: vwsll_vv_nxv2i64_nxv2i8_zext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
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; CHECK-NEXT: vzext.vf8 v10, v8
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; CHECK-NEXT: vzext.vf8 v12, v9
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; CHECK-NEXT: vsll.vv v8, v10, v12
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; CHECK-NEXT: ret
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;
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; CHECK-ZVBB-LABEL: vwsll_vv_nxv2i64_nxv2i8_zext:
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; CHECK-ZVBB: # %bb.0:
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; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma
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; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
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; CHECK-ZVBB-NEXT: vzext.vf8 v12, v9
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; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12
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; CHECK-ZVBB-NEXT: ret
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%x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
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%y = zext <vscale x 2 x i8> %b to <vscale x 2 x i64>
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%z = shl <vscale x 2 x i64> %x, %y
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ret <vscale x 2 x i64> %z
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}
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define <vscale x 2 x i64> @vwsll_vx_i64_nxv2i64_nxv2i8(<vscale x 2 x i8> %a, i64 %b) {
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; CHECK-LABEL: vwsll_vx_i64_nxv2i64_nxv2i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma
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; CHECK-NEXT: vzext.vf8 v10, v8
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; CHECK-NEXT: vsll.vx v8, v10, a0
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; CHECK-NEXT: ret
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;
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; CHECK-ZVBB-LABEL: vwsll_vx_i64_nxv2i64_nxv2i8:
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; CHECK-ZVBB: # %bb.0:
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; CHECK-ZVBB-NEXT: vsetvli a1, zero, e64, m2, ta, ma
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; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
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; CHECK-ZVBB-NEXT: vsll.vx v8, v10, a0
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; CHECK-ZVBB-NEXT: ret
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%head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
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%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
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%x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
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%z = shl <vscale x 2 x i64> %x, %splat
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ret <vscale x 2 x i64> %z
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}
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define <vscale x 2 x i64> @vwsll_vx_i32_nxv2i64_nxv2i8_sext(<vscale x 2 x i8> %a, i32 %b) {
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; CHECK-LABEL: vwsll_vx_i32_nxv2i64_nxv2i8_sext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
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; CHECK-NEXT: vmv.v.x v9, a0
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; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
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; CHECK-NEXT: vzext.vf8 v10, v8
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; CHECK-NEXT: vsext.vf2 v12, v9
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; CHECK-NEXT: vsll.vv v8, v10, v12
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; CHECK-NEXT: ret
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;
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; CHECK-ZVBB-LABEL: vwsll_vx_i32_nxv2i64_nxv2i8_sext:
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; CHECK-ZVBB: # %bb.0:
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; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma
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; CHECK-ZVBB-NEXT: vmv.v.x v9, a0
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; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
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; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
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; CHECK-ZVBB-NEXT: vsext.vf2 v12, v9
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; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12
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; CHECK-ZVBB-NEXT: ret
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%head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
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%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
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%x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
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%y = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
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%z = shl <vscale x 2 x i64> %x, %y
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ret <vscale x 2 x i64> %z
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}
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define <vscale x 2 x i64> @vwsll_vx_i32_nxv2i64_nxv2i8_zext(<vscale x 2 x i8> %a, i32 %b) {
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; CHECK-LABEL: vwsll_vx_i32_nxv2i64_nxv2i8_zext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
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; CHECK-NEXT: vmv.v.x v9, a0
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; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
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; CHECK-NEXT: vzext.vf8 v10, v8
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; CHECK-NEXT: vzext.vf2 v12, v9
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; CHECK-NEXT: vsll.vv v8, v10, v12
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; CHECK-NEXT: ret
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;
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; CHECK-ZVBB-LABEL: vwsll_vx_i32_nxv2i64_nxv2i8_zext:
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; CHECK-ZVBB: # %bb.0:
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; CHECK-ZVBB-NEXT: vsetvli a1, zero, e32, m1, ta, ma
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; CHECK-ZVBB-NEXT: vmv.v.x v9, a0
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; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
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; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
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; CHECK-ZVBB-NEXT: vzext.vf2 v12, v9
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; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12
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; CHECK-ZVBB-NEXT: ret
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%head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
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%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
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%x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
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%y = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
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%z = shl <vscale x 2 x i64> %x, %y
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ret <vscale x 2 x i64> %z
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}
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define <vscale x 2 x i64> @vwsll_vx_i16_nxv2i64_nxv2i8_sext(<vscale x 2 x i8> %a, i16 %b) {
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; CHECK-LABEL: vwsll_vx_i16_nxv2i64_nxv2i8_sext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vmv.v.x v9, a0
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; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
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; CHECK-NEXT: vzext.vf8 v10, v8
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; CHECK-NEXT: vsext.vf4 v12, v9
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; CHECK-NEXT: vsll.vv v8, v10, v12
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; CHECK-NEXT: ret
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;
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; CHECK-ZVBB-LABEL: vwsll_vx_i16_nxv2i64_nxv2i8_sext:
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; CHECK-ZVBB: # %bb.0:
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; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
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; CHECK-ZVBB-NEXT: vmv.v.x v9, a0
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; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
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; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
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; CHECK-ZVBB-NEXT: vsext.vf4 v12, v9
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; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12
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; CHECK-ZVBB-NEXT: ret
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%head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
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%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
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%x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
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%y = sext <vscale x 2 x i16> %splat to <vscale x 2 x i64>
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%z = shl <vscale x 2 x i64> %x, %y
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ret <vscale x 2 x i64> %z
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}
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define <vscale x 2 x i64> @vwsll_vx_i16_nxv2i64_nxv2i8_zext(<vscale x 2 x i8> %a, i16 %b) {
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; CHECK-LABEL: vwsll_vx_i16_nxv2i64_nxv2i8_zext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vmv.v.x v9, a0
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; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
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; CHECK-NEXT: vzext.vf8 v10, v8
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; CHECK-NEXT: vzext.vf4 v12, v9
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; CHECK-NEXT: vsll.vv v8, v10, v12
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; CHECK-NEXT: ret
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;
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; CHECK-ZVBB-LABEL: vwsll_vx_i16_nxv2i64_nxv2i8_zext:
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; CHECK-ZVBB: # %bb.0:
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; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
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; CHECK-ZVBB-NEXT: vmv.v.x v9, a0
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; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
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; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
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; CHECK-ZVBB-NEXT: vzext.vf4 v12, v9
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; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12
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; CHECK-ZVBB-NEXT: ret
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%head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
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%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
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%x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
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%y = zext <vscale x 2 x i16> %splat to <vscale x 2 x i64>
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%z = shl <vscale x 2 x i64> %x, %y
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ret <vscale x 2 x i64> %z
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}
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define <vscale x 2 x i64> @vwsll_vx_i8_nxv2i64_nxv2i8_sext(<vscale x 2 x i8> %a, i8 %b) {
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; CHECK-LABEL: vwsll_vx_i8_nxv2i64_nxv2i8_sext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
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; CHECK-NEXT: vmv.v.x v9, a0
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; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
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; CHECK-NEXT: vzext.vf8 v10, v8
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; CHECK-NEXT: vsext.vf8 v12, v9
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; CHECK-NEXT: vsll.vv v8, v10, v12
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; CHECK-NEXT: ret
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;
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; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv2i64_nxv2i8_sext:
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; CHECK-ZVBB: # %bb.0:
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; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
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; CHECK-ZVBB-NEXT: vmv.v.x v9, a0
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; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
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; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
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; CHECK-ZVBB-NEXT: vsext.vf8 v12, v9
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; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12
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; CHECK-ZVBB-NEXT: ret
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%head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
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%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
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%x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
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%y = sext <vscale x 2 x i8> %splat to <vscale x 2 x i64>
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%z = shl <vscale x 2 x i64> %x, %y
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ret <vscale x 2 x i64> %z
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}
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define <vscale x 2 x i64> @vwsll_vx_i8_nxv2i64_nxv2i8_zext(<vscale x 2 x i8> %a, i8 %b) {
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; CHECK-LABEL: vwsll_vx_i8_nxv2i64_nxv2i8_zext:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
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; CHECK-NEXT: vmv.v.x v9, a0
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; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
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; CHECK-NEXT: vzext.vf8 v10, v8
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; CHECK-NEXT: vzext.vf8 v12, v9
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; CHECK-NEXT: vsll.vv v8, v10, v12
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; CHECK-NEXT: ret
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;
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; CHECK-ZVBB-LABEL: vwsll_vx_i8_nxv2i64_nxv2i8_zext:
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; CHECK-ZVBB: # %bb.0:
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; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
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; CHECK-ZVBB-NEXT: vmv.v.x v9, a0
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; CHECK-ZVBB-NEXT: vsetvli zero, zero, e64, m2, ta, ma
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; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
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; CHECK-ZVBB-NEXT: vzext.vf8 v12, v9
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; CHECK-ZVBB-NEXT: vsll.vv v8, v10, v12
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; CHECK-ZVBB-NEXT: ret
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%head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
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%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
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%x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
863+
%y = zext <vscale x 2 x i8> %splat to <vscale x 2 x i64>
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%z = shl <vscale x 2 x i64> %x, %y
865+
ret <vscale x 2 x i64> %z
866+
}
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define <vscale x 2 x i64> @vwsll_vi_nxv2i64_nxv2i8(<vscale x 2 x i8> %a) {
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; CHECK-LABEL: vwsll_vi_nxv2i64_nxv2i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
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; CHECK-NEXT: vzext.vf8 v10, v8
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; CHECK-NEXT: vsll.vi v8, v10, 2
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; CHECK-NEXT: ret
875+
;
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; CHECK-ZVBB-LABEL: vwsll_vi_nxv2i64_nxv2i8:
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; CHECK-ZVBB: # %bb.0:
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; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma
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; CHECK-ZVBB-NEXT: vzext.vf8 v10, v8
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; CHECK-ZVBB-NEXT: vsll.vi v8, v10, 2
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; CHECK-ZVBB-NEXT: ret
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%x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
883+
%z = shl <vscale x 2 x i64> %x, splat (i64 2)
884+
ret <vscale x 2 x i64> %z
885+
}

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