Skip to content

Commit 4a39cff

Browse files
momchil-velikovmomchil-velikov
committed
[fixup] Rebase, update tests, add tests for the new all-true patterns, change undef to poison
1 parent bf851bd commit 4a39cff

File tree

2 files changed

+121
-9
lines changed

2 files changed

+121
-9
lines changed

‎llvm/lib/Target/AArch64/SVEInstrFormats.td

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3321,9 +3321,9 @@ multiclass sve_fp_z2op_p_zd_d_flogb<string asm, SDPatternOperator op> {
33213321
def _S : sve_fp_z2op_p_zd<0b0011010, asm, ZPR32, ZPR32>;
33223322
def _D : sve_fp_z2op_p_zd<0b0011011, asm, ZPR64, ZPR64>;
33233323

3324-
def : SVE_3_Op_UndefZero_Pat<nxv8i16, op, nxv8i16, nxv8i1, nxv8f16, !cast<Instruction>(NAME # _H)>;
3325-
def : SVE_3_Op_UndefZero_Pat<nxv4i32, op, nxv4i32, nxv4i1, nxv4f32, !cast<Instruction>(NAME # _S)>;
3326-
def : SVE_3_Op_UndefZero_Pat<nxv2i64, op, nxv2i64, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _D)>;
3324+
defm : SVE_3_Op_UndefZero_Pat<nxv8i16, op, nxv8i16, nxv8i1, nxv8f16, !cast<Instruction>(NAME # _H)>;
3325+
defm : SVE_3_Op_UndefZero_Pat<nxv4i32, op, nxv4i32, nxv4i1, nxv4f32, !cast<Instruction>(NAME # _S)>;
3326+
defm : SVE_3_Op_UndefZero_Pat<nxv2i64, op, nxv2i64, nxv2i1, nxv2f64, !cast<Instruction>(NAME # _D)>;
33273327
}
33283328

33293329
multiclass sve_fp_z2op_p_zd_b_0<string asm, string op> {

‎llvm/test/CodeGen/AArch64/zeroing-forms-flogb.ll

Lines changed: 118 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ define <vscale x 8 x i16> @test_svlogb_f16_x_1(<vscale x 8 x i1> %pg, <vscale x
1818
; CHECK-2p2-NEXT: flogb z0.h, p0/z, z0.h
1919
; CHECK-2p2-NEXT: ret
2020
entry:
21-
%0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.flogb.nxv8f16(<vscale x 8 x i16> undef, <vscale x 8 x i1> %pg, <vscale x 8 x half> %x)
21+
%0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.flogb.nxv8f16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x half> %x)
2222
ret <vscale x 8 x i16> %0
2323
}
2424

@@ -33,7 +33,7 @@ define <vscale x 8 x i16> @test_svlogb_f16_x_2(<vscale x 8 x i1> %pg, double %z0
3333
; CHECK-2p2-NEXT: flogb z0.h, p0/z, z1.h
3434
; CHECK-2p2-NEXT: ret
3535
entry:
36-
%0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.flogb.nxv8f16(<vscale x 8 x i16> undef, <vscale x 8 x i1> %pg, <vscale x 8 x half> %x)
36+
%0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.flogb.nxv8f16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x half> %x)
3737
ret <vscale x 8 x i16> %0
3838
}
3939

@@ -64,7 +64,7 @@ define <vscale x 4 x i32> @test_svlogb_f32_x_1(<vscale x 4 x i1> %pg, <vscale x
6464
; CHECK-2p2-NEXT: flogb z0.s, p0/z, z0.s
6565
; CHECK-2p2-NEXT: ret
6666
entry:
67-
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.flogb.nxv4f32(<vscale x 4 x i32> undef, <vscale x 4 x i1> %pg, <vscale x 4 x float> %x)
67+
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.flogb.nxv4f32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x float> %x)
6868
ret <vscale x 4 x i32> %0
6969
}
7070

@@ -79,7 +79,7 @@ define <vscale x 4 x i32> @test_svlogb_f32_x_2(<vscale x 4 x i1> %pg, double %z0
7979
; CHECK-2p2-NEXT: flogb z0.s, p0/z, z1.s
8080
; CHECK-2p2-NEXT: ret
8181
entry:
82-
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.flogb.nxv4f32(<vscale x 4 x i32> undef, <vscale x 4 x i1> %pg, <vscale x 4 x float> %x)
82+
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.flogb.nxv4f32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x float> %x)
8383
ret <vscale x 4 x i32> %0
8484
}
8585

@@ -110,7 +110,7 @@ define <vscale x 2 x i64> @test_svlogb_f64_x_1(<vscale x 2 x i1> %pg, <vscale x
110110
; CHECK-2p2-NEXT: flogb z0.d, p0/z, z0.d
111111
; CHECK-2p2-NEXT: ret
112112
entry:
113-
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.flogb.nxv2f64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
113+
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.flogb.nxv2f64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
114114
ret <vscale x 2 x i64> %0
115115
}
116116

@@ -125,7 +125,7 @@ define <vscale x 2 x i64> @test_svlogb_f64_x_2(<vscale x 2 x i1> %pg, double %z0
125125
; CHECK-2p2-NEXT: flogb z0.d, p0/z, z1.d
126126
; CHECK-2p2-NEXT: ret
127127
entry:
128-
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.flogb.nxv2f64(<vscale x 2 x i64> undef, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
128+
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.flogb.nxv2f64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
129129
ret <vscale x 2 x i64> %0
130130
}
131131

@@ -144,3 +144,115 @@ entry:
144144
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.flogb.nxv2f64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
145145
ret <vscale x 2 x i64> %0
146146
}
147+
148+
define <vscale x 8 x i16> @test_svlogb_nxv8f16_ptrue_u(double %z0, <vscale x 8 x half> %x) {
149+
; CHECK-LABEL: test_svlogb_nxv8f16_ptrue_u:
150+
; CHECK: // %bb.0: // %entry
151+
; CHECK-NEXT: ptrue p0.h
152+
; CHECK-NEXT: flogb z0.h, p0/m, z1.h
153+
; CHECK-NEXT: ret
154+
;
155+
; CHECK-2p2-LABEL: test_svlogb_nxv8f16_ptrue_u:
156+
; CHECK-2p2: // %bb.0: // %entry
157+
; CHECK-2p2-NEXT: ptrue p0.h
158+
; CHECK-2p2-NEXT: flogb z0.h, p0/z, z1.h
159+
; CHECK-2p2-NEXT: ret
160+
entry:
161+
%pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
162+
%0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.flogb.nxv8f16(<vscale x 8 x i16> poison, <vscale x 8 x i1> %pg, <vscale x 8 x half> %x)
163+
ret <vscale x 8 x i16> %0
164+
}
165+
166+
define <vscale x 8 x i16> @test_svlogb_nxv8f16_ptrue(double %z0, <vscale x 8 x i16> %x, <vscale x 8 x half> %y) {
167+
; CHECK-LABEL: test_svlogb_nxv8f16_ptrue:
168+
; CHECK: // %bb.0: // %entry
169+
; CHECK-NEXT: mov z0.d, z1.d
170+
; CHECK-NEXT: ptrue p0.h
171+
; CHECK-NEXT: flogb z0.h, p0/m, z2.h
172+
; CHECK-NEXT: ret
173+
;
174+
; CHECK-2p2-LABEL: test_svlogb_nxv8f16_ptrue:
175+
; CHECK-2p2: // %bb.0: // %entry
176+
; CHECK-2p2-NEXT: ptrue p0.h
177+
; CHECK-2p2-NEXT: flogb z0.h, p0/z, z2.h
178+
; CHECK-2p2-NEXT: ret
179+
entry:
180+
%pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
181+
%0 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.flogb.nxv8f16(<vscale x 8 x i16> %x, <vscale x 8 x i1> %pg, <vscale x 8 x half> %y)
182+
ret <vscale x 8 x i16> %0
183+
}
184+
185+
define <vscale x 4 x i32> @test_svlogb_nxv4f32_ptrue_u(double %z0, <vscale x 4 x float> %x) {
186+
; CHECK-LABEL: test_svlogb_nxv4f32_ptrue_u:
187+
; CHECK: // %bb.0: // %entry
188+
; CHECK-NEXT: ptrue p0.s
189+
; CHECK-NEXT: flogb z0.s, p0/m, z1.s
190+
; CHECK-NEXT: ret
191+
;
192+
; CHECK-2p2-LABEL: test_svlogb_nxv4f32_ptrue_u:
193+
; CHECK-2p2: // %bb.0: // %entry
194+
; CHECK-2p2-NEXT: ptrue p0.s
195+
; CHECK-2p2-NEXT: flogb z0.s, p0/z, z1.s
196+
; CHECK-2p2-NEXT: ret
197+
entry:
198+
%pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
199+
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.flogb.nxv4f32(<vscale x 4 x i32> poison, <vscale x 4 x i1> %pg, <vscale x 4 x float> %x)
200+
ret <vscale x 4 x i32> %0
201+
}
202+
203+
define <vscale x 4 x i32> @test_svlogb_nxv4f32_ptrue(double %z0, <vscale x 4 x i32> %x, <vscale x 4 x float> %y) {
204+
; CHECK-LABEL: test_svlogb_nxv4f32_ptrue:
205+
; CHECK: // %bb.0: // %entry
206+
; CHECK-NEXT: mov z0.d, z1.d
207+
; CHECK-NEXT: ptrue p0.s
208+
; CHECK-NEXT: flogb z0.s, p0/m, z2.s
209+
; CHECK-NEXT: ret
210+
;
211+
; CHECK-2p2-LABEL: test_svlogb_nxv4f32_ptrue:
212+
; CHECK-2p2: // %bb.0: // %entry
213+
; CHECK-2p2-NEXT: ptrue p0.s
214+
; CHECK-2p2-NEXT: flogb z0.s, p0/z, z2.s
215+
; CHECK-2p2-NEXT: ret
216+
entry:
217+
%pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31)
218+
%0 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.flogb.nxv4f32(<vscale x 4 x i32> %x, <vscale x 4 x i1> %pg, <vscale x 4 x float> %y)
219+
ret <vscale x 4 x i32> %0
220+
}
221+
222+
define <vscale x 2 x i64> @test_svlogb_nxv2f64_ptrue_u(double %z0, <vscale x 2 x double> %x) {
223+
; CHECK-LABEL: test_svlogb_nxv2f64_ptrue_u:
224+
; CHECK: // %bb.0: // %entry
225+
; CHECK-NEXT: ptrue p0.d
226+
; CHECK-NEXT: flogb z0.d, p0/m, z1.d
227+
; CHECK-NEXT: ret
228+
;
229+
; CHECK-2p2-LABEL: test_svlogb_nxv2f64_ptrue_u:
230+
; CHECK-2p2: // %bb.0: // %entry
231+
; CHECK-2p2-NEXT: ptrue p0.d
232+
; CHECK-2p2-NEXT: flogb z0.d, p0/z, z1.d
233+
; CHECK-2p2-NEXT: ret
234+
entry:
235+
%pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
236+
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.flogb.nxv2f64(<vscale x 2 x i64> poison, <vscale x 2 x i1> %pg, <vscale x 2 x double> %x)
237+
ret <vscale x 2 x i64> %0
238+
}
239+
240+
define <vscale x 2 x i64> @test_svlogb_nxv2f64_ptrue(double %z0, <vscale x 2 x i64> %x, <vscale x 2 x double> %y) {
241+
; CHECK-LABEL: test_svlogb_nxv2f64_ptrue:
242+
; CHECK: // %bb.0: // %entry
243+
; CHECK-NEXT: mov z0.d, z1.d
244+
; CHECK-NEXT: ptrue p0.d
245+
; CHECK-NEXT: flogb z0.d, p0/m, z2.d
246+
; CHECK-NEXT: ret
247+
;
248+
; CHECK-2p2-LABEL: test_svlogb_nxv2f64_ptrue:
249+
; CHECK-2p2: // %bb.0: // %entry
250+
; CHECK-2p2-NEXT: ptrue p0.d
251+
; CHECK-2p2-NEXT: flogb z0.d, p0/z, z2.d
252+
; CHECK-2p2-NEXT: ret
253+
entry:
254+
%pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
255+
%0 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.flogb.nxv2f64(<vscale x 2 x i64> %x, <vscale x 2 x i1> %pg, <vscale x 2 x double> %y)
256+
ret <vscale x 2 x i64> %0
257+
}
258+

0 commit comments

Comments
 (0)