Add sign extend image operand.

Author: s-perron

clang/lib/CodeGen/Targets/SPIR.cpp

@@ -56,6 +56,8 @@ class CommonSPIRTargetCodeGenInfo : public TargetCodeGenInfo {
   llvm::Type *
   getHLSLType(CodeGenModule &CGM, const Type *Ty,
               const SmallVector<int32_t> *Packoffsets = nullptr) const override;
+  llvm::Type *getSampleType(clang::CodeGen::CodeGenModule &CGM,
+                            clang::QualType Ty, llvm::LLVMContext &Ctx) const;
   llvm::Type *getSPIRVImageTypeFromHLSLResource(
       const HLSLAttributedResourceType::Attributes &attributes,
       llvm::Type *ElementType, llvm::LLVMContext &Ctx) const;
@@ -483,12 +485,13 @@ llvm::Type *CommonSPIRTargetCodeGenInfo::getHLSLType(
     assert(!ResAttrs.IsROV &&
            "Rasterizer order views not implemented for SPIR-V yet");
 
-    llvm::Type *ElemType = CGM.getTypes().ConvertType(ContainedTy);
     if (!ResAttrs.RawBuffer) {
       // convert element type
+      llvm::Type *ElemType = getSampleType(CGM, ContainedTy, Ctx);
       return getSPIRVImageTypeFromHLSLResource(ResAttrs, ElemType, Ctx);
     }
 
+    llvm::Type *ElemType = CGM.getTypes().ConvertType(ContainedTy);
     llvm::ArrayType *RuntimeArrayType = llvm::ArrayType::get(ElemType, 0);
     uint32_t StorageClass = /* StorageBuffer storage class */ 12;
     bool IsWritable = ResAttrs.ResourceClass == llvm::dxil::ResourceClass::UAV;
@@ -515,16 +518,41 @@ llvm::Type *CommonSPIRTargetCodeGenInfo::getHLSLType(
   return nullptr;
 }
 
+llvm::Type *CommonSPIRTargetCodeGenInfo::getSampleType(
+    clang::CodeGen::CodeGenModule &CGM,
+    clang::QualType Ty, llvm::LLVMContext &Ctx) const {
+  Ty = Ty->getCanonicalTypeUnqualified();
+  if (const VectorType *V = dyn_cast<VectorType>(Ty))
+    Ty = V->getElementType();
+  assert(!Ty->isVectorType() && "We still have a vector type.");
+
+  if (!Ty->isSignedIntegerType())
+    return CGM.getTypes().ConvertType(Ty);
+
+  // We need to maintain signed integers as sign integers for the sampled type.
+  // See https://docs.vulkan.org/spec/latest/appendices/spirvenv.html#spirvenv-image-signedness.
+
+  uint32_t OpTypeInt = 21;
+  uint32_t BitWidth = CGM.getContext().getIntWidth(Ty);
+  uint32_t AlignmentInBytes = CGM.getContext().getTypeAlign(Ty)/8;
+  llvm::Type* BitWidthLitType = getInlineSpirvConstant(CGM, nullptr, llvm::APInt(32, BitWidth));
+  llvm::Type* SignLitType = getInlineSpirvConstant(CGM, nullptr, llvm::APInt(32, 1));
+
+  return llvm::TargetExtType::get(Ctx, "spirv.Type", {BitWidthLitType, SignLitType},
+                                  {OpTypeInt, BitWidth / 8, AlignmentInBytes});
+}
+
 llvm::Type *CommonSPIRTargetCodeGenInfo::getSPIRVImageTypeFromHLSLResource(
     const HLSLAttributedResourceType::Attributes &attributes,
-    llvm::Type *ElementType, llvm::LLVMContext &Ctx) const {
-
-  if (ElementType->isVectorTy())
-    ElementType = ElementType->getScalarType();
+    llvm::Type *SampledType, llvm::LLVMContext &Ctx) const {
 
-  assert((ElementType->isIntegerTy() || ElementType->isFloatingPointTy()) &&
-         "The element type for a SPIR-V resource must be a scalar integer or "
-         "floating point type.");
+  // assert((SampledType->isIntegerTy() || SampledType->isFloatingPointTy() ||
+  //         (SampledType->isTargetExtTy() &&
+  //          SampledType->getTargetExtName() == "spirv.Type" &&
+  //          cast<llvm::TargetExtType>(SampledType)->getIntParameter(0) ==
+  //              /* OpTypeInt */ 21)) &&
+  //        "The element type for a SPIR-V resource must be a scalar integer or "
+  //        "floating point type.");
 
   // These parameters correspond to the operands to the OpTypeImage SPIR-V
   // instruction. See
@@ -553,7 +581,7 @@ llvm::Type *CommonSPIRTargetCodeGenInfo::getSPIRVImageTypeFromHLSLResource(
   // Setting to unknown for now.
   IntParams[5] = 0;
 
-  return llvm::TargetExtType::get(Ctx, "spirv.Image", {ElementType}, IntParams);
+  return llvm::TargetExtType::get(Ctx, "spirv.Image", {SampledType}, IntParams);
 }
 
 std::unique_ptr<TargetCodeGenInfo>

llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

@@ -341,6 +341,16 @@ class SPIRVInstructionSelector : public InstructionSelector {
                                 GIntrinsic &HandleDef, MachineInstr &Pos) const;
 };
 
+bool sampledTypeIsSignedInteger(const llvm::Type* HandleType) {
+  const TargetExtType* TET = cast<TargetExtType>(HandleType);
+  assert(TET && TET->getTargetExtName() == "spirv.Image");
+
+  if (!TET->getTypeParameter(0)->isIntegerTy()) {
+    return false;
+  }
+
+  return true;
+}
 } // end anonymous namespace
 
 #define GET_GLOBALISEL_IMPL
@@ -1189,18 +1199,23 @@ bool SPIRVInstructionSelector::selectStore(MachineInstr &I) const {
         MRI->createVirtualRegister(MRI->getRegClass(HandleReg));
     auto *HandleDef = cast<GIntrinsic>(getVRegDef(*MRI, HandleReg));
     SPIRVType *HandleType = GR.getSPIRVTypeForVReg(HandleReg);
+    const llvm::Type* LLVMHandleType = GR.getTypeForSPIRVType(HandleType);
     if (!loadHandleBeforePosition(NewHandleReg, HandleType, *HandleDef, I)) {
       return false;
     }
 
     Register IdxReg = IntPtrDef->getOperand(3).getReg();
     if (HandleType->getOpcode() == SPIRV::OpTypeImage) {
-      return BuildMI(*I.getParent(), I, I.getDebugLoc(),
-                     TII.get(SPIRV::OpImageWrite))
-          .addUse(NewHandleReg)
-          .addUse(IdxReg)
-          .addUse(StoreVal)
-          .constrainAllUses(TII, TRI, RBI);
+      auto BMI = BuildMI(*I.getParent(), I, I.getDebugLoc(),
+                         TII.get(SPIRV::OpImageWrite))
+                     .addUse(NewHandleReg)
+                     .addUse(IdxReg)
+                     .addUse(StoreVal);
+
+      if (sampledTypeIsSignedInteger(LLVMHandleType))
+        BMI.addImm(0x1000); // SignExtend
+
+      return BMI.constrainAllUses(TII, TRI, RBI);
     }
   }
 
@@ -3246,25 +3261,32 @@ bool SPIRVInstructionSelector::generateImageRead(Register &ResVReg,
                                                  Register ImageReg,
                                                  Register IdxReg, DebugLoc Loc,
                                                  MachineInstr &Pos) const {
+  SPIRVType *ImageType = GR.getSPIRVTypeForVReg(ImageReg);
+  bool IsSignedInteger = sampledTypeIsSignedInteger(GR.getTypeForSPIRVType(ImageType));
+
   uint64_t ResultSize = GR.getScalarOrVectorComponentCount(ResType);
   if (ResultSize == 4) {
-    return BuildMI(*Pos.getParent(), Pos, Loc, TII.get(SPIRV::OpImageRead))
-        .addDef(ResVReg)
-        .addUse(GR.getSPIRVTypeID(ResType))
-        .addUse(ImageReg)
-        .addUse(IdxReg)
-        .constrainAllUses(TII, TRI, RBI);
+    auto BMI = BuildMI(*Pos.getParent(), Pos, Loc, TII.get(SPIRV::OpImageRead))
+                   .addDef(ResVReg)
+                   .addUse(GR.getSPIRVTypeID(ResType))
+                   .addUse(ImageReg)
+                   .addUse(IdxReg);
+
+    if (IsSignedInteger)
+      BMI.addImm(0x1000); // SignExtend
+    return BMI.constrainAllUses(TII, TRI, RBI);
   }
 
   SPIRVType *ReadType = widenTypeToVec4(ResType, Pos);
   Register ReadReg = MRI->createVirtualRegister(GR.getRegClass(ReadType));
-  bool Succeed =
-      BuildMI(*Pos.getParent(), Pos, Loc, TII.get(SPIRV::OpImageRead))
-          .addDef(ReadReg)
-          .addUse(GR.getSPIRVTypeID(ReadType))
-          .addUse(ImageReg)
-          .addUse(IdxReg)
-          .constrainAllUses(TII, TRI, RBI);
+  auto BMI = BuildMI(*Pos.getParent(), Pos, Loc, TII.get(SPIRV::OpImageRead))
+                 .addDef(ReadReg)
+                 .addUse(GR.getSPIRVTypeID(ReadType))
+                 .addUse(ImageReg)
+                 .addUse(IdxReg);
+  if (IsSignedInteger)
+    BMI.addImm(0x1000); // SignExtend
+  bool Succeed = BMI.constrainAllUses(TII, TRI, RBI);
   if (!Succeed)
     return false;
 

offload-test-suite

@@ -0,0 +1 @@
+Subproject commit ef40d70010f26bc3f385e948736e75a470c9aec8