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woruyuworuyu
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test: update other backend testcase
1 parent 4103b4c commit 45d1f82

17 files changed

+142
-176
lines changed

‎llvm/test/CodeGen/AArch64/arm64-zip.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -413,7 +413,7 @@ define <4 x float> @shuffle_zip1(<4 x float> %arg) {
413413
; CHECK-NEXT: fmov.4s v1, #1.00000000
414414
; CHECK-NEXT: zip1.4h v0, v0, v0
415415
; CHECK-NEXT: sshll.4s v0, v0, #0
416-
; CHECK-NEXT: and.16b v0, v1, v0
416+
; CHECK-NEXT: and.16b v0, v0, v1
417417
; CHECK-NEXT: ret
418418
bb:
419419
%inst = fcmp olt <4 x float> zeroinitializer, %arg

‎llvm/test/CodeGen/AArch64/cmp-select-sign.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -114,9 +114,10 @@ define i64 @not_sign_i64_4(i64 %a) {
114114
define <7 x i8> @sign_7xi8(<7 x i8> %a) {
115115
; CHECK-LABEL: sign_7xi8:
116116
; CHECK: // %bb.0:
117-
; CHECK-NEXT: movi v1.8b, #1
118-
; CHECK-NEXT: cmlt v0.8b, v0.8b, #0
119-
; CHECK-NEXT: orr v0.8b, v0.8b, v1.8b
117+
; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
118+
; CHECK-NEXT: movi v2.8b, #1
119+
; CHECK-NEXT: cmge v0.8b, v1.8b, v0.8b
120+
; CHECK-NEXT: orr v0.8b, v0.8b, v2.8b
120121
; CHECK-NEXT: ret
121122
%c = icmp sgt <7 x i8> %a, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
122123
%res = select <7 x i1> %c, <7 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, <7 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
@@ -150,7 +151,8 @@ define <16 x i8> @sign_16xi8(<16 x i8> %a) {
150151
define <3 x i32> @sign_3xi32(<3 x i32> %a) {
151152
; CHECK-LABEL: sign_3xi32:
152153
; CHECK: // %bb.0:
153-
; CHECK-NEXT: cmlt v0.4s, v0.4s, #0
154+
; CHECK-NEXT: movi v1.2d, #0xffffffffffffffff
155+
; CHECK-NEXT: cmge v0.4s, v1.4s, v0.4s
154156
; CHECK-NEXT: orr v0.4s, #1
155157
; CHECK-NEXT: ret
156158
%c = icmp sgt <3 x i32> %a, <i32 -1, i32 -1, i32 -1>
@@ -197,11 +199,9 @@ define <4 x i32> @not_sign_4xi32(<4 x i32> %a) {
197199
; CHECK-LABEL: not_sign_4xi32:
198200
; CHECK: // %bb.0:
199201
; CHECK-NEXT: adrp x8, .LCPI16_0
200-
; CHECK-NEXT: movi v2.4s, #1
201202
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI16_0]
202-
; CHECK-NEXT: cmgt v0.4s, v0.4s, v1.4s
203-
; CHECK-NEXT: and v1.16b, v0.16b, v2.16b
204-
; CHECK-NEXT: orn v0.16b, v1.16b, v0.16b
203+
; CHECK-NEXT: cmge v0.4s, v1.4s, v0.4s
204+
; CHECK-NEXT: orr v0.4s, #1
205205
; CHECK-NEXT: ret
206206
%c = icmp sgt <4 x i32> %a, <i32 1, i32 -1, i32 -1, i32 -1>
207207
%res = select <4 x i1> %c, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>

‎llvm/test/CodeGen/AArch64/concatbinop.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -179,7 +179,7 @@ define <16 x i8> @signOf_neon(ptr nocapture noundef readonly %a, ptr nocapture n
179179
; CHECK-NEXT: uzp1 v3.16b, v5.16b, v6.16b
180180
; CHECK-NEXT: uzp1 v1.16b, v1.16b, v2.16b
181181
; CHECK-NEXT: and v0.16b, v3.16b, v0.16b
182-
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
182+
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
183183
; CHECK-NEXT: ret
184184
entry:
185185
%0 = load <8 x i16>, ptr %a, align 2

‎llvm/test/CodeGen/AArch64/sat-add.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -530,7 +530,7 @@ define <16 x i8> @unsigned_sat_variable_v16i8_using_cmp_notval(<16 x i8> %x, <16
530530
; CHECK-NEXT: mvn v2.16b, v1.16b
531531
; CHECK-NEXT: add v1.16b, v0.16b, v1.16b
532532
; CHECK-NEXT: cmhi v0.16b, v0.16b, v2.16b
533-
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
533+
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
534534
; CHECK-NEXT: ret
535535
%noty = xor <16 x i8> %y, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
536536
%a = add <16 x i8> %x, %y
@@ -570,7 +570,7 @@ define <8 x i16> @unsigned_sat_variable_v8i16_using_cmp_notval(<8 x i16> %x, <8
570570
; CHECK-NEXT: mvn v2.16b, v1.16b
571571
; CHECK-NEXT: add v1.8h, v0.8h, v1.8h
572572
; CHECK-NEXT: cmhi v0.8h, v0.8h, v2.8h
573-
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
573+
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
574574
; CHECK-NEXT: ret
575575
%noty = xor <8 x i16> %y, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
576576
%a = add <8 x i16> %x, %y
@@ -610,7 +610,7 @@ define <4 x i32> @unsigned_sat_variable_v4i32_using_cmp_notval(<4 x i32> %x, <4
610610
; CHECK-NEXT: mvn v2.16b, v1.16b
611611
; CHECK-NEXT: add v1.4s, v0.4s, v1.4s
612612
; CHECK-NEXT: cmhi v0.4s, v0.4s, v2.4s
613-
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
613+
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
614614
; CHECK-NEXT: ret
615615
%noty = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1>
616616
%a = add <4 x i32> %x, %y
@@ -651,7 +651,7 @@ define <2 x i64> @unsigned_sat_variable_v2i64_using_cmp_notval(<2 x i64> %x, <2
651651
; CHECK-NEXT: mvn v2.16b, v1.16b
652652
; CHECK-NEXT: add v1.2d, v0.2d, v1.2d
653653
; CHECK-NEXT: cmhi v0.2d, v0.2d, v2.2d
654-
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
654+
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
655655
; CHECK-NEXT: ret
656656
%noty = xor <2 x i64> %y, <i64 -1, i64 -1>
657657
%a = add <2 x i64> %x, %y

‎llvm/test/CodeGen/AArch64/select_cc.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -88,7 +88,7 @@ define <2 x double> @select_olt_load_cmp(<2 x double> %a, ptr %src) {
8888
; CHECK-SD-NEXT: ldr d1, [x0]
8989
; CHECK-SD-NEXT: fcmgt v1.2s, v1.2s, #0.0
9090
; CHECK-SD-NEXT: sshll v1.2d, v1.2s, #0
91-
; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b
91+
; CHECK-SD-NEXT: and v0.16b, v1.16b, v0.16b
9292
; CHECK-SD-NEXT: ret
9393
;
9494
; CHECK-GI-LABEL: select_olt_load_cmp:

‎llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -249,9 +249,6 @@ define <16 x i8> @sel_shift_bool_v16i8(<16 x i1> %t) {
249249
; CHECK-SD-LABEL: sel_shift_bool_v16i8:
250250
; CHECK-SD: // %bb.0:
251251
; CHECK-SD-NEXT: shl v0.16b, v0.16b, #7
252-
; CHECK-SD-NEXT: movi v1.16b, #128
253-
; CHECK-SD-NEXT: cmlt v0.16b, v0.16b, #0
254-
; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b
255252
; CHECK-SD-NEXT: ret
256253
;
257254
; CHECK-GI-LABEL: sel_shift_bool_v16i8:

‎llvm/test/CodeGen/AArch64/tbl-loops.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -31,12 +31,12 @@ define void @loop1(ptr noalias nocapture noundef writeonly %dst, ptr nocapture n
3131
; CHECK-NEXT: add x13, x13, #32
3232
; CHECK-NEXT: fcmgt v3.4s, v1.4s, v0.4s
3333
; CHECK-NEXT: fcmgt v4.4s, v2.4s, v0.4s
34-
; CHECK-NEXT: fcmlt v5.4s, v1.4s, #0.0
35-
; CHECK-NEXT: fcmlt v6.4s, v2.4s, #0.0
36-
; CHECK-NEXT: bit v1.16b, v0.16b, v3.16b
37-
; CHECK-NEXT: bit v2.16b, v0.16b, v4.16b
38-
; CHECK-NEXT: bic v1.16b, v1.16b, v5.16b
39-
; CHECK-NEXT: bic v2.16b, v2.16b, v6.16b
34+
; CHECK-NEXT: bsl v3.16b, v0.16b, v1.16b
35+
; CHECK-NEXT: bsl v4.16b, v0.16b, v2.16b
36+
; CHECK-NEXT: fcmlt v1.4s, v1.4s, #0.0
37+
; CHECK-NEXT: fcmlt v2.4s, v2.4s, #0.0
38+
; CHECK-NEXT: bic v1.16b, v3.16b, v1.16b
39+
; CHECK-NEXT: bic v2.16b, v4.16b, v2.16b
4040
; CHECK-NEXT: fcvtzs v1.4s, v1.4s
4141
; CHECK-NEXT: fcvtzs v2.4s, v2.4s
4242
; CHECK-NEXT: xtn v1.4h, v1.4s

‎llvm/test/CodeGen/AArch64/vselect-constants.ll

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -146,10 +146,8 @@ define <4 x i32> @cmp_sel_0_or_minus1_vec(<4 x i32> %x, <4 x i32> %y) {
146146
define <4 x i32> @sel_1_or_0_vec(<4 x i1> %cond) {
147147
; CHECK-LABEL: sel_1_or_0_vec:
148148
; CHECK: // %bb.0:
149-
; CHECK-NEXT: ushll v0.4s, v0.4h, #0
150149
; CHECK-NEXT: movi v1.4s, #1
151-
; CHECK-NEXT: shl v0.4s, v0.4s, #31
152-
; CHECK-NEXT: cmlt v0.4s, v0.4s, #0
150+
; CHECK-NEXT: ushll v0.4s, v0.4h, #0
153151
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
154152
; CHECK-NEXT: ret
155153
%add = select <4 x i1> %cond, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>

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