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davemgreendavemgreen
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[Codegen] Make Width in getMemOperandsWithOffsetWidth a LocationSize. (#83875)
This is another part of #70452 which makes getMemOperandsWithOffsetWidth use a LocationSize for Width, as opposed to the unsigned it currently uses. The advantages on it's own are not super high if getMemOperandsWithOffsetWidth usually uses known sizes, but if the values can come from an MMO it can help be more accurate in case they are Unknown (and in the future, scalable).
1 parent 5dc5bfb commit 44be5a7

21 files changed

+73
-68
lines changed

‎llvm/include/llvm/CodeGen/TargetInstrInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1446,7 +1446,7 @@ class TargetInstrInfo : public MCInstrInfo {
14461446
/// abstraction that supports negative offsets.
14471447
virtual bool getMemOperandsWithOffsetWidth(
14481448
const MachineInstr &MI, SmallVectorImpl<const MachineOperand *> &BaseOps,
1449-
int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
1449+
int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width,
14501450
const TargetRegisterInfo *TRI) const {
14511451
return false;
14521452
}

‎llvm/lib/CodeGen/MachineScheduler.cpp

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1729,11 +1729,11 @@ class BaseMemOpClusterMutation : public ScheduleDAGMutation {
17291729
SUnit *SU;
17301730
SmallVector<const MachineOperand *, 4> BaseOps;
17311731
int64_t Offset;
1732-
unsigned Width;
1732+
LocationSize Width;
17331733
bool OffsetIsScalable;
17341734

17351735
MemOpInfo(SUnit *SU, ArrayRef<const MachineOperand *> BaseOps,
1736-
int64_t Offset, bool OffsetIsScalable, unsigned Width)
1736+
int64_t Offset, bool OffsetIsScalable, LocationSize Width)
17371737
: SU(SU), BaseOps(BaseOps.begin(), BaseOps.end()), Offset(Offset),
17381738
Width(Width), OffsetIsScalable(OffsetIsScalable) {}
17391739

@@ -1866,11 +1866,12 @@ void BaseMemOpClusterMutation::clusterNeighboringMemOps(
18661866

18671867
auto MemOpb = MemOpRecords[NextIdx];
18681868
unsigned ClusterLength = 2;
1869-
unsigned CurrentClusterBytes = MemOpa.Width + MemOpb.Width;
1869+
unsigned CurrentClusterBytes = MemOpa.Width.getValue().getKnownMinValue() +
1870+
MemOpb.Width.getValue().getKnownMinValue();
18701871
if (SUnit2ClusterInfo.count(MemOpa.SU->NodeNum)) {
18711872
ClusterLength = SUnit2ClusterInfo[MemOpa.SU->NodeNum].first + 1;
1872-
CurrentClusterBytes =
1873-
SUnit2ClusterInfo[MemOpa.SU->NodeNum].second + MemOpb.Width;
1873+
CurrentClusterBytes = SUnit2ClusterInfo[MemOpa.SU->NodeNum].second +
1874+
MemOpb.Width.getValue().getKnownMinValue();
18741875
}
18751876

18761877
if (!TII->shouldClusterMemOps(MemOpa.BaseOps, MemOpa.Offset,
@@ -1940,7 +1941,7 @@ void BaseMemOpClusterMutation::collectMemOpRecords(
19401941
SmallVector<const MachineOperand *, 4> BaseOps;
19411942
int64_t Offset;
19421943
bool OffsetIsScalable;
1943-
unsigned Width;
1944+
LocationSize Width = 0;
19441945
if (TII->getMemOperandsWithOffsetWidth(MI, BaseOps, Offset,
19451946
OffsetIsScalable, Width, TRI)) {
19461947
MemOpRecords.push_back(

‎llvm/lib/CodeGen/TargetInstrInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1365,7 +1365,7 @@ bool TargetInstrInfo::getMemOperandWithOffset(
13651365
const MachineInstr &MI, const MachineOperand *&BaseOp, int64_t &Offset,
13661366
bool &OffsetIsScalable, const TargetRegisterInfo *TRI) const {
13671367
SmallVector<const MachineOperand *, 4> BaseOps;
1368-
unsigned Width;
1368+
LocationSize Width = 0;
13691369
if (!getMemOperandsWithOffsetWidth(MI, BaseOps, Offset, OffsetIsScalable,
13701370
Width, TRI) ||
13711371
BaseOps.size() != 1)

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2675,7 +2675,7 @@ bool AArch64InstrInfo::isCandidateToMergeOrPair(const MachineInstr &MI) const {
26752675

26762676
bool AArch64InstrInfo::getMemOperandsWithOffsetWidth(
26772677
const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps,
2678-
int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
2678+
int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width,
26792679
const TargetRegisterInfo *TRI) const {
26802680
if (!LdSt.mayLoadOrStore())
26812681
return false;

‎llvm/lib/Target/AArch64/AArch64InstrInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -155,7 +155,7 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
155155

156156
bool getMemOperandsWithOffsetWidth(
157157
const MachineInstr &MI, SmallVectorImpl<const MachineOperand *> &BaseOps,
158-
int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
158+
int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width,
159159
const TargetRegisterInfo *TRI) const override;
160160

161161
/// If \p OffsetIsScalable is set to 'true', the offset is scaled by `vscale`.

‎llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -208,7 +208,7 @@ class SIInsertHardClauses : public MachineFunctionPass {
208208

209209
int64_t Dummy1;
210210
bool Dummy2;
211-
unsigned Dummy3;
211+
LocationSize Dummy3 = 0;
212212
SmallVector<const MachineOperand *, 4> BaseOps;
213213
if (Type <= LAST_REAL_HARDCLAUSE_TYPE) {
214214
if (!SII->getMemOperandsWithOffsetWidth(MI, BaseOps, Dummy1, Dummy2,

‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -360,7 +360,7 @@ static bool isStride64(unsigned Opc) {
360360

361361
bool SIInstrInfo::getMemOperandsWithOffsetWidth(
362362
const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps,
363-
int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
363+
int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width,
364364
const TargetRegisterInfo *TRI) const {
365365
if (!LdSt.mayLoadOrStore())
366366
return false;
@@ -424,7 +424,7 @@ bool SIInstrInfo::getMemOperandsWithOffsetWidth(
424424
DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
425425
Width = getOpSize(LdSt, DataOpIdx);
426426
DataOpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1);
427-
Width += getOpSize(LdSt, DataOpIdx);
427+
Width = Width.getValue() + getOpSize(LdSt, DataOpIdx);
428428
} else {
429429
Width = getOpSize(LdSt, DataOpIdx);
430430
}
@@ -3647,7 +3647,7 @@ bool SIInstrInfo::checkInstOffsetsDoNotOverlap(const MachineInstr &MIa,
36473647
const MachineInstr &MIb) const {
36483648
SmallVector<const MachineOperand *, 4> BaseOps0, BaseOps1;
36493649
int64_t Offset0, Offset1;
3650-
unsigned Dummy0, Dummy1;
3650+
LocationSize Dummy0 = 0, Dummy1 = 0;
36513651
bool Offset0IsScalable, Offset1IsScalable;
36523652
if (!getMemOperandsWithOffsetWidth(MIa, BaseOps0, Offset0, Offset0IsScalable,
36533653
Dummy0, &RI) ||

‎llvm/lib/Target/AMDGPU/SIInstrInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -240,7 +240,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
240240
bool getMemOperandsWithOffsetWidth(
241241
const MachineInstr &LdSt,
242242
SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
243-
bool &OffsetIsScalable, unsigned &Width,
243+
bool &OffsetIsScalable, LocationSize &Width,
244244
const TargetRegisterInfo *TRI) const final;
245245

246246
bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,

‎llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3070,7 +3070,7 @@ bool HexagonInstrInfo::addLatencyToSchedule(const MachineInstr &MI1,
30703070
/// Get the base register and byte offset of a load/store instr.
30713071
bool HexagonInstrInfo::getMemOperandsWithOffsetWidth(
30723072
const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps,
3073-
int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
3073+
int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width,
30743074
const TargetRegisterInfo *TRI) const {
30753075
OffsetIsScalable = false;
30763076
const MachineOperand *BaseOp = getBaseAndOffset(LdSt, Offset, Width);
@@ -3286,9 +3286,9 @@ unsigned HexagonInstrInfo::getAddrMode(const MachineInstr &MI) const {
32863286
// returned in Offset and the access size is returned in AccessSize.
32873287
// If the base operand has a subregister or the offset field does not contain
32883288
// an immediate value, return nullptr.
3289-
MachineOperand *HexagonInstrInfo::getBaseAndOffset(const MachineInstr &MI,
3290-
int64_t &Offset,
3291-
unsigned &AccessSize) const {
3289+
MachineOperand *
3290+
HexagonInstrInfo::getBaseAndOffset(const MachineInstr &MI, int64_t &Offset,
3291+
LocationSize &AccessSize) const {
32923292
// Return if it is not a base+offset type instruction or a MemOp.
32933293
if (getAddrMode(MI) != HexagonII::BaseImmOffset &&
32943294
getAddrMode(MI) != HexagonII::BaseLongOffset &&

‎llvm/lib/Target/Hexagon/HexagonInstrInfo.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -208,7 +208,7 @@ class HexagonInstrInfo : public HexagonGenInstrInfo {
208208
bool getMemOperandsWithOffsetWidth(
209209
const MachineInstr &LdSt,
210210
SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
211-
bool &OffsetIsScalable, unsigned &Width,
211+
bool &OffsetIsScalable, LocationSize &Width,
212212
const TargetRegisterInfo *TRI) const override;
213213

214214
/// Reverses the branch condition of the specified condition list,
@@ -437,7 +437,7 @@ class HexagonInstrInfo : public HexagonGenInstrInfo {
437437

438438
unsigned getAddrMode(const MachineInstr &MI) const;
439439
MachineOperand *getBaseAndOffset(const MachineInstr &MI, int64_t &Offset,
440-
unsigned &AccessSize) const;
440+
LocationSize &AccessSize) const;
441441
SmallVector<MachineInstr*,2> getBranchingInstrs(MachineBasicBlock& MBB) const;
442442
unsigned getCExtOpNum(const MachineInstr &MI) const;
443443
HexagonII::CompoundGroup

‎llvm/lib/Target/Hexagon/HexagonSubtarget.cpp

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -395,10 +395,11 @@ void HexagonSubtarget::BankConflictMutation::apply(ScheduleDAGInstrs *DAG) {
395395
HII.getAddrMode(L0) != HexagonII::BaseImmOffset)
396396
continue;
397397
int64_t Offset0;
398-
unsigned Size0;
398+
LocationSize Size0 = 0;
399399
MachineOperand *BaseOp0 = HII.getBaseAndOffset(L0, Offset0, Size0);
400400
// Is the access size is longer than the L1 cache line, skip the check.
401-
if (BaseOp0 == nullptr || !BaseOp0->isReg() || Size0 >= 32)
401+
if (BaseOp0 == nullptr || !BaseOp0->isReg() || !Size0.hasValue() ||
402+
Size0.getValue() >= 32)
402403
continue;
403404
// Scan only up to 32 instructions ahead (to avoid n^2 complexity).
404405
for (unsigned j = i+1, m = std::min(i+32, e); j != m; ++j) {
@@ -408,10 +409,10 @@ void HexagonSubtarget::BankConflictMutation::apply(ScheduleDAGInstrs *DAG) {
408409
HII.getAddrMode(L1) != HexagonII::BaseImmOffset)
409410
continue;
410411
int64_t Offset1;
411-
unsigned Size1;
412+
LocationSize Size1 = 0;
412413
MachineOperand *BaseOp1 = HII.getBaseAndOffset(L1, Offset1, Size1);
413-
if (BaseOp1 == nullptr || !BaseOp1->isReg() || Size1 >= 32 ||
414-
BaseOp0->getReg() != BaseOp1->getReg())
414+
if (BaseOp1 == nullptr || !BaseOp1->isReg() || !Size0.hasValue() ||
415+
Size1.getValue() >= 32 || BaseOp0->getReg() != BaseOp1->getReg())
415416
continue;
416417
// Check bits 3 and 4 of the offset: if they differ, a bank conflict
417418
// is unlikely.

‎llvm/lib/Target/Lanai/LanaiInstrInfo.cpp

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -102,14 +102,15 @@ bool LanaiInstrInfo::areMemAccessesTriviallyDisjoint(
102102
const TargetRegisterInfo *TRI = &getRegisterInfo();
103103
const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr;
104104
int64_t OffsetA = 0, OffsetB = 0;
105-
unsigned int WidthA = 0, WidthB = 0;
105+
LocationSize WidthA = 0, WidthB = 0;
106106
if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) &&
107107
getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) {
108108
if (BaseOpA->isIdenticalTo(*BaseOpB)) {
109109
int LowOffset = std::min(OffsetA, OffsetB);
110110
int HighOffset = std::max(OffsetA, OffsetB);
111-
int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
112-
if (LowOffset + LowWidth <= HighOffset)
111+
LocationSize LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
112+
if (LowWidth.hasValue() &&
113+
LowOffset + (int)LowWidth.getValue() <= HighOffset)
113114
return true;
114115
}
115116
}
@@ -752,7 +753,7 @@ Register LanaiInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
752753

753754
bool LanaiInstrInfo::getMemOperandWithOffsetWidth(
754755
const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset,
755-
unsigned &Width, const TargetRegisterInfo * /*TRI*/) const {
756+
LocationSize &Width, const TargetRegisterInfo * /*TRI*/) const {
756757
// Handle only loads/stores with base register followed by immediate offset
757758
// and with add as ALU op.
758759
if (LdSt.getNumOperands() != 4)
@@ -793,7 +794,7 @@ bool LanaiInstrInfo::getMemOperandWithOffsetWidth(
793794

794795
bool LanaiInstrInfo::getMemOperandsWithOffsetWidth(
795796
const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps,
796-
int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
797+
int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width,
797798
const TargetRegisterInfo *TRI) const {
798799
switch (LdSt.getOpcode()) {
799800
default:

‎llvm/lib/Target/Lanai/LanaiInstrInfo.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -70,12 +70,12 @@ class LanaiInstrInfo : public LanaiGenInstrInfo {
7070
bool getMemOperandsWithOffsetWidth(
7171
const MachineInstr &LdSt,
7272
SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
73-
bool &OffsetIsScalable, unsigned &Width,
73+
bool &OffsetIsScalable, LocationSize &Width,
7474
const TargetRegisterInfo *TRI) const override;
7575

7676
bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
7777
const MachineOperand *&BaseOp,
78-
int64_t &Offset, unsigned &Width,
78+
int64_t &Offset, LocationSize &Width,
7979
const TargetRegisterInfo *TRI) const;
8080

8181
std::pair<unsigned, unsigned>

‎llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2821,7 +2821,7 @@ bool PPCInstrInfo::optimizeCmpPostRA(MachineInstr &CmpMI) const {
28212821

28222822
bool PPCInstrInfo::getMemOperandsWithOffsetWidth(
28232823
const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps,
2824-
int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
2824+
int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width,
28252825
const TargetRegisterInfo *TRI) const {
28262826
const MachineOperand *BaseOp;
28272827
OffsetIsScalable = false;
@@ -2913,7 +2913,7 @@ bool PPCInstrInfo::shouldClusterMemOps(
29132913
return false;
29142914

29152915
int64_t Offset1 = 0, Offset2 = 0;
2916-
unsigned Width1 = 0, Width2 = 0;
2916+
LocationSize Width1 = 0, Width2 = 0;
29172917
const MachineOperand *Base1 = nullptr, *Base2 = nullptr;
29182918
if (!getMemOperandWithOffsetWidth(FirstLdSt, Base1, Offset1, Width1, TRI) ||
29192919
!getMemOperandWithOffsetWidth(SecondLdSt, Base2, Offset2, Width2, TRI) ||
@@ -2924,7 +2924,7 @@ bool PPCInstrInfo::shouldClusterMemOps(
29242924
"getMemOperandWithOffsetWidth return incorrect base op");
29252925
// The caller should already have ordered FirstMemOp/SecondMemOp by offset.
29262926
assert(Offset1 <= Offset2 && "Caller should have ordered offsets.");
2927-
return Offset1 + Width1 == Offset2;
2927+
return Offset1 + (int64_t)Width1.getValue() == Offset2;
29282928
}
29292929

29302930
/// GetInstSize - Return the number of bytes of code the specified
@@ -5504,7 +5504,7 @@ MachineInstr *PPCInstrInfo::findLoopInstr(
55045504
// memory width. Width is the size of memory that is being loaded/stored.
55055505
bool PPCInstrInfo::getMemOperandWithOffsetWidth(
55065506
const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset,
5507-
unsigned &Width, const TargetRegisterInfo *TRI) const {
5507+
LocationSize &Width, const TargetRegisterInfo *TRI) const {
55085508
if (!LdSt.mayLoadOrStore() || LdSt.getNumExplicitOperands() != 3)
55095509
return false;
55105510

@@ -5542,14 +5542,15 @@ bool PPCInstrInfo::areMemAccessesTriviallyDisjoint(
55425542
const TargetRegisterInfo *TRI = &getRegisterInfo();
55435543
const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr;
55445544
int64_t OffsetA = 0, OffsetB = 0;
5545-
unsigned int WidthA = 0, WidthB = 0;
5545+
LocationSize WidthA = 0, WidthB = 0;
55465546
if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) &&
55475547
getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) {
55485548
if (BaseOpA->isIdenticalTo(*BaseOpB)) {
55495549
int LowOffset = std::min(OffsetA, OffsetB);
55505550
int HighOffset = std::max(OffsetA, OffsetB);
5551-
int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
5552-
if (LowOffset + LowWidth <= HighOffset)
5551+
LocationSize LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
5552+
if (LowWidth.hasValue() &&
5553+
LowOffset + (int)LowWidth.getValue() <= HighOffset)
55535554
return true;
55545555
}
55555556
}

‎llvm/lib/Target/PowerPC/PPCInstrInfo.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -543,7 +543,7 @@ class PPCInstrInfo : public PPCGenInstrInfo {
543543
/// loaded/stored (e.g. 1, 2, 4, 8).
544544
bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
545545
const MachineOperand *&BaseOp,
546-
int64_t &Offset, unsigned &Width,
546+
int64_t &Offset, LocationSize &Width,
547547
const TargetRegisterInfo *TRI) const;
548548

549549
bool optimizeCmpPostRA(MachineInstr &MI) const;
@@ -553,7 +553,7 @@ class PPCInstrInfo : public PPCGenInstrInfo {
553553
bool getMemOperandsWithOffsetWidth(
554554
const MachineInstr &LdSt,
555555
SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
556-
bool &OffsetIsScalable, unsigned &Width,
556+
bool &OffsetIsScalable, LocationSize &Width,
557557
const TargetRegisterInfo *TRI) const override;
558558

559559
/// Returns true if the two given memory operations should be scheduled

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2195,7 +2195,7 @@ MachineInstr *RISCVInstrInfo::emitLdStWithAddr(MachineInstr &MemI,
21952195

21962196
bool RISCVInstrInfo::getMemOperandsWithOffsetWidth(
21972197
const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps,
2198-
int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
2198+
int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width,
21992199
const TargetRegisterInfo *TRI) const {
22002200
if (!LdSt.mayLoadOrStore())
22012201
return false;
@@ -2300,7 +2300,7 @@ bool RISCVInstrInfo::shouldClusterMemOps(
23002300
// function) and set it as appropriate.
23012301
bool RISCVInstrInfo::getMemOperandWithOffsetWidth(
23022302
const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset,
2303-
unsigned &Width, const TargetRegisterInfo *TRI) const {
2303+
LocationSize &Width, const TargetRegisterInfo *TRI) const {
23042304
if (!LdSt.mayLoadOrStore())
23052305
return false;
23062306

@@ -2339,14 +2339,15 @@ bool RISCVInstrInfo::areMemAccessesTriviallyDisjoint(
23392339
const TargetRegisterInfo *TRI = STI.getRegisterInfo();
23402340
const MachineOperand *BaseOpA = nullptr, *BaseOpB = nullptr;
23412341
int64_t OffsetA = 0, OffsetB = 0;
2342-
unsigned int WidthA = 0, WidthB = 0;
2342+
LocationSize WidthA = 0, WidthB = 0;
23432343
if (getMemOperandWithOffsetWidth(MIa, BaseOpA, OffsetA, WidthA, TRI) &&
23442344
getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) {
23452345
if (BaseOpA->isIdenticalTo(*BaseOpB)) {
23462346
int LowOffset = std::min(OffsetA, OffsetB);
23472347
int HighOffset = std::max(OffsetA, OffsetB);
2348-
int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
2349-
if (LowOffset + LowWidth <= HighOffset)
2348+
LocationSize LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;
2349+
if (LowWidth.hasValue() &&
2350+
LowOffset + (int)LowWidth.getValue() <= HighOffset)
23502351
return true;
23512352
}
23522353
}

‎llvm/lib/Target/RISCV/RISCVInstrInfo.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -156,7 +156,7 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
156156

157157
bool getMemOperandsWithOffsetWidth(
158158
const MachineInstr &MI, SmallVectorImpl<const MachineOperand *> &BaseOps,
159-
int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
159+
int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width,
160160
const TargetRegisterInfo *TRI) const override;
161161

162162
bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,
@@ -168,7 +168,7 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
168168

169169
bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
170170
const MachineOperand *&BaseOp,
171-
int64_t &Offset, unsigned &Width,
171+
int64_t &Offset, LocationSize &Width,
172172
const TargetRegisterInfo *TRI) const;
173173

174174
bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,

‎llvm/lib/Target/X86/X86InstrInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4519,7 +4519,7 @@ bool X86InstrInfo::preservesZeroValueInReg(
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bool X86InstrInfo::getMemOperandsWithOffsetWidth(
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const MachineInstr &MemOp, SmallVectorImpl<const MachineOperand *> &BaseOps,
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int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
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int64_t &Offset, bool &OffsetIsScalable, LocationSize &Width,
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const TargetRegisterInfo *TRI) const {
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const MCInstrDesc &Desc = MemOp.getDesc();
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int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);

‎llvm/lib/Target/X86/X86InstrInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -375,7 +375,7 @@ class X86InstrInfo final : public X86GenInstrInfo {
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bool getMemOperandsWithOffsetWidth(
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const MachineInstr &LdSt,
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SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset,
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bool &OffsetIsScalable, unsigned &Width,
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bool &OffsetIsScalable, LocationSize &Width,
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const TargetRegisterInfo *TRI) const override;
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bool analyzeBranchPredicate(MachineBasicBlock &MBB,
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TargetInstrInfo::MachineBranchPredicate &MBP,

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