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[CodeGen][LoongArch] Set FP_TO_SINT/FP_TO_UINT to legal for vector types (#79107)
Support the following conversions: v4f32->v4i32, v2f64->v2i64(LSX) v8f32->v8i32, v4f64->v4i64(LASX) v4f32->v4i64, v4f64->v4i32(LASX)
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7 files changed

+208
-4
lines changed

7 files changed

+208
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lines changed

‎llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -265,8 +265,10 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
265265
{ISD::SETNE, ISD::SETGE, ISD::SETGT, ISD::SETUGE, ISD::SETUGT}, VT,
266266
Expand);
267267
}
268-
setOperationAction({ISD::SINT_TO_FP, ISD::UINT_TO_FP},
269-
{MVT::v4i32, MVT::v2i64}, Legal);
268+
for (MVT VT : {MVT::v4i32, MVT::v2i64}) {
269+
setOperationAction({ISD::SINT_TO_FP, ISD::UINT_TO_FP}, VT, Legal);
270+
setOperationAction({ISD::FP_TO_SINT, ISD::FP_TO_UINT}, VT, Legal);
271+
}
270272
for (MVT VT : {MVT::v4f32, MVT::v2f64}) {
271273
setOperationAction({ISD::FADD, ISD::FSUB}, VT, Legal);
272274
setOperationAction({ISD::FMUL, ISD::FDIV}, VT, Legal);
@@ -309,8 +311,10 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
309311
{ISD::SETNE, ISD::SETGE, ISD::SETGT, ISD::SETUGE, ISD::SETUGT}, VT,
310312
Expand);
311313
}
312-
setOperationAction({ISD::SINT_TO_FP, ISD::UINT_TO_FP},
313-
{MVT::v8i32, MVT::v4i32, MVT::v4i64}, Legal);
314+
for (MVT VT : {MVT::v8i32, MVT::v4i32, MVT::v4i64}) {
315+
setOperationAction({ISD::SINT_TO_FP, ISD::UINT_TO_FP}, VT, Legal);
316+
setOperationAction({ISD::FP_TO_SINT, ISD::FP_TO_UINT}, VT, Legal);
317+
}
314318
for (MVT VT : {MVT::v8f32, MVT::v4f64}) {
315319
setOperationAction({ISD::FADD, ISD::FSUB}, VT, Legal);
316320
setOperationAction({ISD::FMUL, ISD::FDIV}, VT, Legal);

‎llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1637,6 +1637,28 @@ def : Pat<(v4f32 (uint_to_fp v4i64:$vj)),
16371637
(XVFFINT_D_LU v4i64:$vj)),
16381638
sub_128)>;
16391639

1640+
// XVFTINTRZ_{W_S/L_D}
1641+
def : Pat<(v8i32 (fp_to_sint v8f32:$vj)), (XVFTINTRZ_W_S v8f32:$vj)>;
1642+
def : Pat<(v4i64 (fp_to_sint v4f64:$vj)), (XVFTINTRZ_L_D v4f64:$vj)>;
1643+
def : Pat<(v4i64 (fp_to_sint v4f32:$vj)),
1644+
(VEXT2XV_D_W (SUBREG_TO_REG (i64 0), (VFTINTRZ_W_S v4f32:$vj),
1645+
sub_128))>;
1646+
def : Pat<(v4i32 (fp_to_sint (v4f64 LASX256:$vj))),
1647+
(EXTRACT_SUBREG (XVFTINTRZ_W_S (XVFCVT_S_D (XVPERMI_D v4f64:$vj, 238),
1648+
v4f64:$vj)),
1649+
sub_128)>;
1650+
1651+
// XVFTINTRZ_{W_SU/L_DU}
1652+
def : Pat<(v8i32 (fp_to_uint v8f32:$vj)), (XVFTINTRZ_WU_S v8f32:$vj)>;
1653+
def : Pat<(v4i64 (fp_to_uint v4f64:$vj)), (XVFTINTRZ_LU_D v4f64:$vj)>;
1654+
def : Pat<(v4i64 (fp_to_uint v4f32:$vj)),
1655+
(VEXT2XV_DU_WU (SUBREG_TO_REG (i64 0), (VFTINTRZ_WU_S v4f32:$vj),
1656+
sub_128))>;
1657+
def : Pat<(v4i32 (fp_to_uint (v4f64 LASX256:$vj))),
1658+
(EXTRACT_SUBREG (XVFTINTRZ_W_S (XVFCVT_S_D (XVPERMI_D v4f64:$vj, 238),
1659+
v4f64:$vj)),
1660+
sub_128)>;
1661+
16401662
} // Predicates = [HasExtLASX]
16411663

16421664
/// Intrinsic pattern

‎llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1754,6 +1754,14 @@ def : Pat<(v2f64 (sint_to_fp v2i64:$vj)), (VFFINT_D_L v2i64:$vj)>;
17541754
def : Pat<(v4f32 (uint_to_fp v4i32:$vj)), (VFFINT_S_WU v4i32:$vj)>;
17551755
def : Pat<(v2f64 (uint_to_fp v2i64:$vj)), (VFFINT_D_LU v2i64:$vj)>;
17561756

1757+
// VFTINTRZ_{W_S/L_D}
1758+
def : Pat<(v4i32 (fp_to_sint v4f32:$vj)), (VFTINTRZ_W_S v4f32:$vj)>;
1759+
def : Pat<(v2i64 (fp_to_sint v2f64:$vj)), (VFTINTRZ_L_D v2f64:$vj)>;
1760+
1761+
// VFTINTRZ_{W_SU/L_DU}
1762+
def : Pat<(v4i32 (fp_to_uint v4f32:$vj)), (VFTINTRZ_WU_S v4f32:$vj)>;
1763+
def : Pat<(v2i64 (fp_to_uint v2f64:$vj)), (VFTINTRZ_LU_D v2f64:$vj)>;
1764+
17571765
} // Predicates = [HasExtLSX]
17581766

17591767
/// Intrinsic pattern

‎llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptosi.ll

Lines changed: 57 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,57 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
2+
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
3+
4+
define void @fptosi_v8f32_v8i32(ptr %res, ptr %in){
5+
; CHECK-LABEL: fptosi_v8f32_v8i32:
6+
; CHECK: # %bb.0:
7+
; CHECK-NEXT: xvld $xr0, $a1, 0
8+
; CHECK-NEXT: xvftintrz.w.s $xr0, $xr0
9+
; CHECK-NEXT: xvst $xr0, $a0, 0
10+
; CHECK-NEXT: ret
11+
%v0 = load <8 x float>, ptr %in
12+
%v1 = fptosi <8 x float> %v0 to <8 x i32>
13+
store <8 x i32> %v1, ptr %res
14+
ret void
15+
}
16+
17+
define void @fptosi_v4f64_v4i64(ptr %res, ptr %in){
18+
; CHECK-LABEL: fptosi_v4f64_v4i64:
19+
; CHECK: # %bb.0:
20+
; CHECK-NEXT: xvld $xr0, $a1, 0
21+
; CHECK-NEXT: xvftintrz.l.d $xr0, $xr0
22+
; CHECK-NEXT: xvst $xr0, $a0, 0
23+
; CHECK-NEXT: ret
24+
%v0 = load <4 x double>, ptr %in
25+
%v1 = fptosi <4 x double> %v0 to <4 x i64>
26+
store <4 x i64> %v1, ptr %res
27+
ret void
28+
}
29+
30+
define void @fptosi_v4f64_v4i32(ptr %res, ptr %in){
31+
; CHECK-LABEL: fptosi_v4f64_v4i32:
32+
; CHECK: # %bb.0:
33+
; CHECK-NEXT: xvld $xr0, $a1, 0
34+
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 238
35+
; CHECK-NEXT: xvfcvt.s.d $xr0, $xr1, $xr0
36+
; CHECK-NEXT: xvftintrz.w.s $xr0, $xr0
37+
; CHECK-NEXT: vst $vr0, $a0, 0
38+
; CHECK-NEXT: ret
39+
%v0 = load <4 x double>, ptr %in
40+
%v1 = fptosi <4 x double> %v0 to <4 x i32>
41+
store <4 x i32> %v1, ptr %res
42+
ret void
43+
}
44+
45+
define void @fptosi_v4f32_v4i64(ptr %res, ptr %in){
46+
; CHECK-LABEL: fptosi_v4f32_v4i64:
47+
; CHECK: # %bb.0:
48+
; CHECK-NEXT: vld $vr0, $a1, 0
49+
; CHECK-NEXT: vftintrz.w.s $vr0, $vr0
50+
; CHECK-NEXT: vext2xv.d.w $xr0, $xr0
51+
; CHECK-NEXT: xvst $xr0, $a0, 0
52+
; CHECK-NEXT: ret
53+
%v0 = load <4 x float>, ptr %in
54+
%v1 = fptosi <4 x float> %v0 to <4 x i64>
55+
store <4 x i64> %v1, ptr %res
56+
ret void
57+
}

‎llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptoui.ll

Lines changed: 57 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,57 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
2+
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
3+
4+
define void @fptoui_v8f32_v8i32(ptr %res, ptr %in){
5+
; CHECK-LABEL: fptoui_v8f32_v8i32:
6+
; CHECK: # %bb.0:
7+
; CHECK-NEXT: xvld $xr0, $a1, 0
8+
; CHECK-NEXT: xvftintrz.wu.s $xr0, $xr0
9+
; CHECK-NEXT: xvst $xr0, $a0, 0
10+
; CHECK-NEXT: ret
11+
%v0 = load <8 x float>, ptr %in
12+
%v1 = fptoui <8 x float> %v0 to <8 x i32>
13+
store <8 x i32> %v1, ptr %res
14+
ret void
15+
}
16+
17+
define void @fptoui_v4f64_v4i64(ptr %res, ptr %in){
18+
; CHECK-LABEL: fptoui_v4f64_v4i64:
19+
; CHECK: # %bb.0:
20+
; CHECK-NEXT: xvld $xr0, $a1, 0
21+
; CHECK-NEXT: xvftintrz.lu.d $xr0, $xr0
22+
; CHECK-NEXT: xvst $xr0, $a0, 0
23+
; CHECK-NEXT: ret
24+
%v0 = load <4 x double>, ptr %in
25+
%v1 = fptoui <4 x double> %v0 to <4 x i64>
26+
store <4 x i64> %v1, ptr %res
27+
ret void
28+
}
29+
30+
define void @fptoui_v4f64_v4i32(ptr %res, ptr %in){
31+
; CHECK-LABEL: fptoui_v4f64_v4i32:
32+
; CHECK: # %bb.0:
33+
; CHECK-NEXT: xvld $xr0, $a1, 0
34+
; CHECK-NEXT: xvpermi.d $xr1, $xr0, 238
35+
; CHECK-NEXT: xvfcvt.s.d $xr0, $xr1, $xr0
36+
; CHECK-NEXT: xvftintrz.w.s $xr0, $xr0
37+
; CHECK-NEXT: vst $vr0, $a0, 0
38+
; CHECK-NEXT: ret
39+
%v0 = load <4 x double>, ptr %in
40+
%v1 = fptoui <4 x double> %v0 to <4 x i32>
41+
store <4 x i32> %v1, ptr %res
42+
ret void
43+
}
44+
45+
define void @fptoui_v4f32_v4i64(ptr %res, ptr %in){
46+
; CHECK-LABEL: fptoui_v4f32_v4i64:
47+
; CHECK: # %bb.0:
48+
; CHECK-NEXT: vld $vr0, $a1, 0
49+
; CHECK-NEXT: vftintrz.wu.s $vr0, $vr0
50+
; CHECK-NEXT: vext2xv.du.wu $xr0, $xr0
51+
; CHECK-NEXT: xvst $xr0, $a0, 0
52+
; CHECK-NEXT: ret
53+
%v0 = load <4 x float>, ptr %in
54+
%v1 = fptoui <4 x float> %v0 to <4 x i64>
55+
store <4 x i64> %v1, ptr %res
56+
ret void
57+
}

‎llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptosi.ll

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,28 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
2+
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
3+
4+
define void @fptosi_v4f32_v4i32(ptr %res, ptr %in){
5+
; CHECK-LABEL: fptosi_v4f32_v4i32:
6+
; CHECK: # %bb.0:
7+
; CHECK-NEXT: vld $vr0, $a1, 0
8+
; CHECK-NEXT: vftintrz.w.s $vr0, $vr0
9+
; CHECK-NEXT: vst $vr0, $a0, 0
10+
; CHECK-NEXT: ret
11+
%v0 = load <4 x float>, ptr %in
12+
%v1 = fptosi <4 x float> %v0 to <4 x i32>
13+
store <4 x i32> %v1, ptr %res
14+
ret void
15+
}
16+
17+
define void @fptosi_v2f64_v2i64(ptr %res, ptr %in){
18+
; CHECK-LABEL: fptosi_v2f64_v2i64:
19+
; CHECK: # %bb.0:
20+
; CHECK-NEXT: vld $vr0, $a1, 0
21+
; CHECK-NEXT: vftintrz.l.d $vr0, $vr0
22+
; CHECK-NEXT: vst $vr0, $a0, 0
23+
; CHECK-NEXT: ret
24+
%v0 = load <2 x double>, ptr %in
25+
%v1 = fptosi <2 x double> %v0 to <2 x i64>
26+
store <2 x i64> %v1, ptr %res
27+
ret void
28+
}

‎llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptoui.ll

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,28 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
2+
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
3+
4+
define void @fptoui_v4f32_v4i32(ptr %res, ptr %in){
5+
; CHECK-LABEL: fptoui_v4f32_v4i32:
6+
; CHECK: # %bb.0:
7+
; CHECK-NEXT: vld $vr0, $a1, 0
8+
; CHECK-NEXT: vftintrz.wu.s $vr0, $vr0
9+
; CHECK-NEXT: vst $vr0, $a0, 0
10+
; CHECK-NEXT: ret
11+
%v0 = load <4 x float>, ptr %in
12+
%v1 = fptoui <4 x float> %v0 to <4 x i32>
13+
store <4 x i32> %v1, ptr %res
14+
ret void
15+
}
16+
17+
define void @fptoui_v2f64_v2i64(ptr %res, ptr %in){
18+
; CHECK-LABEL: fptoui_v2f64_v2i64:
19+
; CHECK: # %bb.0:
20+
; CHECK-NEXT: vld $vr0, $a1, 0
21+
; CHECK-NEXT: vftintrz.lu.d $vr0, $vr0
22+
; CHECK-NEXT: vst $vr0, $a0, 0
23+
; CHECK-NEXT: ret
24+
%v0 = load <2 x double>, ptr %in
25+
%v1 = fptoui <2 x double> %v0 to <2 x i64>
26+
store <2 x i64> %v1, ptr %res
27+
ret void
28+
}

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