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[RISCV] Adjust sdloc when creating an extend for widening instructions (#82040)
We were using the SDLoc corresponding to the original arithmetic instruction, but here using the SDLoc corresponding to the original extend if we need to introduce a new narrower extend seems cleaner. As can be seen in the test diffs, this very minorly impacts scheduling and register allocation by given the scheduler a hint from original program order.
1 parent 46734aa commit 4265ad1

7 files changed

+46
-46
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -13374,7 +13374,7 @@ struct NodeExtensionHelper {
1337413374
unsigned ExtOpc = *SExt ? RISCVISD::VSEXT_VL : RISCVISD::VZEXT_VL;
1337513375

1337613376
// If we need an extension, we should be changing the type.
13377-
SDLoc DL(Root);
13377+
SDLoc DL(OrigOperand);
1337813378
auto [Mask, VL] = getMaskAndVL(Root, DAG, Subtarget);
1337913379
switch (OrigOperand.getOpcode()) {
1338013380
case ISD::ZERO_EXTEND:

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll

+12-12
Original file line numberDiff line numberDiff line change
@@ -386,11 +386,11 @@ define <2 x i32> @vwadd_v2i32_v2i8(ptr %x, ptr %y) {
386386
; CHECK-LABEL: vwadd_v2i32_v2i8:
387387
; CHECK: # %bb.0:
388388
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
389-
; CHECK-NEXT: vle8.v v8, (a1)
390-
; CHECK-NEXT: vle8.v v9, (a0)
389+
; CHECK-NEXT: vle8.v v8, (a0)
390+
; CHECK-NEXT: vle8.v v9, (a1)
391391
; CHECK-NEXT: vsext.vf2 v10, v8
392392
; CHECK-NEXT: vsext.vf2 v11, v9
393-
; CHECK-NEXT: vwadd.vv v8, v11, v10
393+
; CHECK-NEXT: vwadd.vv v8, v10, v11
394394
; CHECK-NEXT: ret
395395
%a = load <2 x i8>, ptr %x
396396
%b = load <2 x i8>, ptr %y
@@ -885,11 +885,11 @@ define <2 x i32> @vwadd_v2i32_of_v2i8(ptr %x, ptr %y) {
885885
; CHECK-LABEL: vwadd_v2i32_of_v2i8:
886886
; CHECK: # %bb.0:
887887
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
888-
; CHECK-NEXT: vle8.v v8, (a1)
889-
; CHECK-NEXT: vle8.v v9, (a0)
888+
; CHECK-NEXT: vle8.v v8, (a0)
889+
; CHECK-NEXT: vle8.v v9, (a1)
890890
; CHECK-NEXT: vsext.vf2 v10, v8
891891
; CHECK-NEXT: vsext.vf2 v11, v9
892-
; CHECK-NEXT: vwadd.vv v8, v11, v10
892+
; CHECK-NEXT: vwadd.vv v8, v10, v11
893893
; CHECK-NEXT: ret
894894
%a = load <2 x i8>, ptr %x
895895
%b = load <2 x i8>, ptr %y
@@ -903,11 +903,11 @@ define <2 x i64> @vwadd_v2i64_of_v2i8(ptr %x, ptr %y) {
903903
; CHECK-LABEL: vwadd_v2i64_of_v2i8:
904904
; CHECK: # %bb.0:
905905
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
906-
; CHECK-NEXT: vle8.v v8, (a1)
907-
; CHECK-NEXT: vle8.v v9, (a0)
906+
; CHECK-NEXT: vle8.v v8, (a0)
907+
; CHECK-NEXT: vle8.v v9, (a1)
908908
; CHECK-NEXT: vsext.vf4 v10, v8
909909
; CHECK-NEXT: vsext.vf4 v11, v9
910-
; CHECK-NEXT: vwadd.vv v8, v11, v10
910+
; CHECK-NEXT: vwadd.vv v8, v10, v11
911911
; CHECK-NEXT: ret
912912
%a = load <2 x i8>, ptr %x
913913
%b = load <2 x i8>, ptr %y
@@ -921,11 +921,11 @@ define <2 x i64> @vwadd_v2i64_of_v2i16(ptr %x, ptr %y) {
921921
; CHECK-LABEL: vwadd_v2i64_of_v2i16:
922922
; CHECK: # %bb.0:
923923
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
924-
; CHECK-NEXT: vle16.v v8, (a1)
925-
; CHECK-NEXT: vle16.v v9, (a0)
924+
; CHECK-NEXT: vle16.v v8, (a0)
925+
; CHECK-NEXT: vle16.v v9, (a1)
926926
; CHECK-NEXT: vsext.vf2 v10, v8
927927
; CHECK-NEXT: vsext.vf2 v11, v9
928-
; CHECK-NEXT: vwadd.vv v8, v11, v10
928+
; CHECK-NEXT: vwadd.vv v8, v10, v11
929929
; CHECK-NEXT: ret
930930
%a = load <2 x i16>, ptr %x
931931
%b = load <2 x i16>, ptr %y

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaddu.ll

+12-12
Original file line numberDiff line numberDiff line change
@@ -386,11 +386,11 @@ define <2 x i32> @vwaddu_v2i32_v2i8(ptr %x, ptr %y) {
386386
; CHECK-LABEL: vwaddu_v2i32_v2i8:
387387
; CHECK: # %bb.0:
388388
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
389-
; CHECK-NEXT: vle8.v v8, (a1)
390-
; CHECK-NEXT: vle8.v v9, (a0)
389+
; CHECK-NEXT: vle8.v v8, (a0)
390+
; CHECK-NEXT: vle8.v v9, (a1)
391391
; CHECK-NEXT: vzext.vf2 v10, v8
392392
; CHECK-NEXT: vzext.vf2 v11, v9
393-
; CHECK-NEXT: vwaddu.vv v8, v11, v10
393+
; CHECK-NEXT: vwaddu.vv v8, v10, v11
394394
; CHECK-NEXT: ret
395395
%a = load <2 x i8>, ptr %x
396396
%b = load <2 x i8>, ptr %y
@@ -913,11 +913,11 @@ define <2 x i32> @vwaddu_v2i32_of_v2i8(ptr %x, ptr %y) {
913913
; CHECK-LABEL: vwaddu_v2i32_of_v2i8:
914914
; CHECK: # %bb.0:
915915
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
916-
; CHECK-NEXT: vle8.v v8, (a1)
917-
; CHECK-NEXT: vle8.v v9, (a0)
916+
; CHECK-NEXT: vle8.v v8, (a0)
917+
; CHECK-NEXT: vle8.v v9, (a1)
918918
; CHECK-NEXT: vzext.vf2 v10, v8
919919
; CHECK-NEXT: vzext.vf2 v11, v9
920-
; CHECK-NEXT: vwaddu.vv v8, v11, v10
920+
; CHECK-NEXT: vwaddu.vv v8, v10, v11
921921
; CHECK-NEXT: ret
922922
%a = load <2 x i8>, ptr %x
923923
%b = load <2 x i8>, ptr %y
@@ -931,11 +931,11 @@ define <2 x i64> @vwaddu_v2i64_of_v2i8(ptr %x, ptr %y) {
931931
; CHECK-LABEL: vwaddu_v2i64_of_v2i8:
932932
; CHECK: # %bb.0:
933933
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
934-
; CHECK-NEXT: vle8.v v8, (a1)
935-
; CHECK-NEXT: vle8.v v9, (a0)
934+
; CHECK-NEXT: vle8.v v8, (a0)
935+
; CHECK-NEXT: vle8.v v9, (a1)
936936
; CHECK-NEXT: vzext.vf4 v10, v8
937937
; CHECK-NEXT: vzext.vf4 v11, v9
938-
; CHECK-NEXT: vwaddu.vv v8, v11, v10
938+
; CHECK-NEXT: vwaddu.vv v8, v10, v11
939939
; CHECK-NEXT: ret
940940
%a = load <2 x i8>, ptr %x
941941
%b = load <2 x i8>, ptr %y
@@ -949,11 +949,11 @@ define <2 x i64> @vwaddu_v2i64_of_v2i16(ptr %x, ptr %y) {
949949
; CHECK-LABEL: vwaddu_v2i64_of_v2i16:
950950
; CHECK: # %bb.0:
951951
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
952-
; CHECK-NEXT: vle16.v v8, (a1)
953-
; CHECK-NEXT: vle16.v v9, (a0)
952+
; CHECK-NEXT: vle16.v v8, (a0)
953+
; CHECK-NEXT: vle16.v v9, (a1)
954954
; CHECK-NEXT: vzext.vf2 v10, v8
955955
; CHECK-NEXT: vzext.vf2 v11, v9
956-
; CHECK-NEXT: vwaddu.vv v8, v11, v10
956+
; CHECK-NEXT: vwaddu.vv v8, v10, v11
957957
; CHECK-NEXT: ret
958958
%a = load <2 x i16>, ptr %x
959959
%b = load <2 x i16>, ptr %y

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll

+3-3
Original file line numberDiff line numberDiff line change
@@ -416,11 +416,11 @@ define <2 x i32> @vwmul_v2i32_v2i8(ptr %x, ptr %y) {
416416
; CHECK-LABEL: vwmul_v2i32_v2i8:
417417
; CHECK: # %bb.0:
418418
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
419-
; CHECK-NEXT: vle8.v v8, (a1)
420-
; CHECK-NEXT: vle8.v v9, (a0)
419+
; CHECK-NEXT: vle8.v v8, (a0)
420+
; CHECK-NEXT: vle8.v v9, (a1)
421421
; CHECK-NEXT: vsext.vf2 v10, v8
422422
; CHECK-NEXT: vsext.vf2 v11, v9
423-
; CHECK-NEXT: vwmul.vv v8, v11, v10
423+
; CHECK-NEXT: vwmul.vv v8, v10, v11
424424
; CHECK-NEXT: ret
425425
%a = load <2 x i8>, ptr %x
426426
%b = load <2 x i8>, ptr %y

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll

+3-3
Original file line numberDiff line numberDiff line change
@@ -392,11 +392,11 @@ define <2 x i32> @vwmulu_v2i32_v2i8(ptr %x, ptr %y) {
392392
; CHECK-LABEL: vwmulu_v2i32_v2i8:
393393
; CHECK: # %bb.0:
394394
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
395-
; CHECK-NEXT: vle8.v v8, (a1)
396-
; CHECK-NEXT: vle8.v v9, (a0)
395+
; CHECK-NEXT: vle8.v v8, (a0)
396+
; CHECK-NEXT: vle8.v v9, (a1)
397397
; CHECK-NEXT: vzext.vf2 v10, v8
398398
; CHECK-NEXT: vzext.vf2 v11, v9
399-
; CHECK-NEXT: vwmulu.vv v8, v11, v10
399+
; CHECK-NEXT: vwmulu.vv v8, v10, v11
400400
; CHECK-NEXT: ret
401401
%a = load <2 x i8>, ptr %x
402402
%b = load <2 x i8>, ptr %y

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub.ll

+3-3
Original file line numberDiff line numberDiff line change
@@ -386,11 +386,11 @@ define <2 x i32> @vwsub_v2i32_v2i8(ptr %x, ptr %y) {
386386
; CHECK-LABEL: vwsub_v2i32_v2i8:
387387
; CHECK: # %bb.0:
388388
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
389-
; CHECK-NEXT: vle8.v v8, (a1)
390-
; CHECK-NEXT: vle8.v v9, (a0)
389+
; CHECK-NEXT: vle8.v v8, (a0)
390+
; CHECK-NEXT: vle8.v v9, (a1)
391391
; CHECK-NEXT: vsext.vf2 v10, v8
392392
; CHECK-NEXT: vsext.vf2 v11, v9
393-
; CHECK-NEXT: vwsub.vv v8, v11, v10
393+
; CHECK-NEXT: vwsub.vv v8, v10, v11
394394
; CHECK-NEXT: ret
395395
%a = load <2 x i8>, ptr %x
396396
%b = load <2 x i8>, ptr %y

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsubu.ll

+12-12
Original file line numberDiff line numberDiff line change
@@ -386,11 +386,11 @@ define <2 x i32> @vwsubu_v2i32_v2i8(ptr %x, ptr %y) {
386386
; CHECK-LABEL: vwsubu_v2i32_v2i8:
387387
; CHECK: # %bb.0:
388388
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
389-
; CHECK-NEXT: vle8.v v8, (a1)
390-
; CHECK-NEXT: vle8.v v9, (a0)
389+
; CHECK-NEXT: vle8.v v8, (a0)
390+
; CHECK-NEXT: vle8.v v9, (a1)
391391
; CHECK-NEXT: vzext.vf2 v10, v8
392392
; CHECK-NEXT: vzext.vf2 v11, v9
393-
; CHECK-NEXT: vwsubu.vv v8, v11, v10
393+
; CHECK-NEXT: vwsubu.vv v8, v10, v11
394394
; CHECK-NEXT: ret
395395
%a = load <2 x i8>, ptr %x
396396
%b = load <2 x i8>, ptr %y
@@ -900,11 +900,11 @@ define <2 x i32> @vwsubu_v2i32_of_v2i8(ptr %x, ptr %y) {
900900
; CHECK-LABEL: vwsubu_v2i32_of_v2i8:
901901
; CHECK: # %bb.0:
902902
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
903-
; CHECK-NEXT: vle8.v v8, (a1)
904-
; CHECK-NEXT: vle8.v v9, (a0)
903+
; CHECK-NEXT: vle8.v v8, (a0)
904+
; CHECK-NEXT: vle8.v v9, (a1)
905905
; CHECK-NEXT: vzext.vf2 v10, v8
906906
; CHECK-NEXT: vzext.vf2 v11, v9
907-
; CHECK-NEXT: vwsubu.vv v8, v11, v10
907+
; CHECK-NEXT: vwsubu.vv v8, v10, v11
908908
; CHECK-NEXT: ret
909909
%a = load <2 x i8>, ptr %x
910910
%b = load <2 x i8>, ptr %y
@@ -918,11 +918,11 @@ define <2 x i64> @vwsubu_v2i64_of_v2i8(ptr %x, ptr %y) {
918918
; CHECK-LABEL: vwsubu_v2i64_of_v2i8:
919919
; CHECK: # %bb.0:
920920
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
921-
; CHECK-NEXT: vle8.v v8, (a1)
922-
; CHECK-NEXT: vle8.v v9, (a0)
921+
; CHECK-NEXT: vle8.v v8, (a0)
922+
; CHECK-NEXT: vle8.v v9, (a1)
923923
; CHECK-NEXT: vzext.vf4 v10, v8
924924
; CHECK-NEXT: vzext.vf4 v11, v9
925-
; CHECK-NEXT: vwsubu.vv v8, v11, v10
925+
; CHECK-NEXT: vwsubu.vv v8, v10, v11
926926
; CHECK-NEXT: ret
927927
%a = load <2 x i8>, ptr %x
928928
%b = load <2 x i8>, ptr %y
@@ -936,11 +936,11 @@ define <2 x i64> @vwsubu_v2i64_of_v2i16(ptr %x, ptr %y) {
936936
; CHECK-LABEL: vwsubu_v2i64_of_v2i16:
937937
; CHECK: # %bb.0:
938938
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
939-
; CHECK-NEXT: vle16.v v8, (a1)
940-
; CHECK-NEXT: vle16.v v9, (a0)
939+
; CHECK-NEXT: vle16.v v8, (a0)
940+
; CHECK-NEXT: vle16.v v9, (a1)
941941
; CHECK-NEXT: vzext.vf2 v10, v8
942942
; CHECK-NEXT: vzext.vf2 v11, v9
943-
; CHECK-NEXT: vwsubu.vv v8, v11, v10
943+
; CHECK-NEXT: vwsubu.vv v8, v10, v11
944944
; CHECK-NEXT: ret
945945
%a = load <2 x i16>, ptr %x
946946
%b = load <2 x i16>, ptr %y

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