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DAG: Simplify demanded bits for truncating atomic_store (#90113)
It's really unfortunate that STORE and ATOMIC_STORE are separate opcodes. This duplicates a basic simplify demanded for the truncating case. This avoids some AMDGPU lit regressions in a future patch. I'm not sure how to craft a test that exposes this without first introducing the regressions by promoting half to i16.
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llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

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@@ -530,6 +530,7 @@ namespace {
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bool refineExtractVectorEltIntoMultipleNarrowExtractVectorElts(SDNode *N);
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SDValue visitSTORE(SDNode *N);
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SDValue visitATOMIC_STORE(SDNode *N);
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SDValue visitLIFETIME_END(SDNode *N);
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SDValue visitINSERT_VECTOR_ELT(SDNode *N);
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SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
@@ -1909,6 +1910,7 @@ SDValue DAGCombiner::visit(SDNode *N) {
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case ISD::BR_CC: return visitBR_CC(N);
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case ISD::LOAD: return visitLOAD(N);
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case ISD::STORE: return visitSTORE(N);
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case ISD::ATOMIC_STORE: return visitATOMIC_STORE(N);
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case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
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case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
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case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
@@ -21137,6 +21139,24 @@ SDValue DAGCombiner::replaceStoreOfInsertLoad(StoreSDNode *ST) {
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ST->getMemOperand()->getFlags());
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}
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SDValue DAGCombiner::visitATOMIC_STORE(SDNode *N) {
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AtomicSDNode *ST = cast<AtomicSDNode>(N);
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SDValue Val = ST->getVal();
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EVT VT = Val.getValueType();
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EVT MemVT = ST->getMemoryVT();
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if (MemVT.bitsLT(VT)) { // Is truncating store
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APInt TruncDemandedBits = APInt::getLowBitsSet(VT.getScalarSizeInBits(),
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MemVT.getScalarSizeInBits());
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// See if we can simplify the operation with SimplifyDemandedBits, which
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// only works if the value has a single use.
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if (SimplifyDemandedBits(Val, TruncDemandedBits))
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return SDValue(N, 0);
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}
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return SDValue();
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}
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SDValue DAGCombiner::visitSTORE(SDNode *N) {
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StoreSDNode *ST = cast<StoreSDNode>(N);
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SDValue Chain = ST->getChain();

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