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[RISCV] Check for COPY_TO_REGCLASS in usesAllOnesMask (#67037)
Sometimes with mask vectors that have been widened, there is a CopyToRegClass node in between the VMSET and the CopyToReg. This is a resurrection of https://reviews.llvm.org/D148524, and is needed to remove the mask operand when it's extracted from a subvector as planned in #66267 (comment)
1 parent 6e3827a commit 3510552

16 files changed

+139
-171
lines changed

‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3188,6 +3188,12 @@ static bool usesAllOnesMask(SDValue MaskOp, SDValue GlueOp) {
31883188
// Check the instruction defining V0; it needs to be a VMSET pseudo.
31893189
SDValue MaskSetter = Glued->getOperand(2);
31903190

3191+
// Sometimes the VMSET is wrapped in a COPY_TO_REGCLASS, e.g. if the mask came
3192+
// from an extract_subvector or insert_subvector.
3193+
if (MaskSetter->isMachineOpcode() &&
3194+
MaskSetter->getMachineOpcode() == RISCV::COPY_TO_REGCLASS)
3195+
MaskSetter = MaskSetter->getOperand(0);
3196+
31913197
const auto IsVMSet = [](unsigned Opc) {
31923198
return Opc == RISCV::PseudoVMSET_M_B1 || Opc == RISCV::PseudoVMSET_M_B16 ||
31933199
Opc == RISCV::PseudoVMSET_M_B2 || Opc == RISCV::PseudoVMSET_M_B32 ||

‎llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll

Lines changed: 13 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -555,7 +555,7 @@ define <vscale x 32 x half> @vp_nearbyint_nxv32f16_unmasked(<vscale x 32 x half>
555555
; ZVFHMIN-NEXT: sub sp, sp, a1
556556
; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
557557
; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma
558-
; ZVFHMIN-NEXT: vmset.m v1
558+
; ZVFHMIN-NEXT: vmset.m v16
559559
; ZVFHMIN-NEXT: csrr a2, vlenb
560560
; ZVFHMIN-NEXT: slli a1, a2, 1
561561
; ZVFHMIN-NEXT: sub a3, a0, a1
@@ -564,21 +564,21 @@ define <vscale x 32 x half> @vp_nearbyint_nxv32f16_unmasked(<vscale x 32 x half>
564564
; ZVFHMIN-NEXT: and a3, a4, a3
565565
; ZVFHMIN-NEXT: srli a2, a2, 2
566566
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
567-
; ZVFHMIN-NEXT: vslidedown.vx v17, v1, a2
567+
; ZVFHMIN-NEXT: vslidedown.vx v16, v16, a2
568568
; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma
569569
; ZVFHMIN-NEXT: addi a2, sp, 16
570570
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
571571
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12
572572
; ZVFHMIN-NEXT: vsetvli zero, a3, e32, m8, ta, ma
573-
; ZVFHMIN-NEXT: vmv1r.v v0, v17
573+
; ZVFHMIN-NEXT: vmv1r.v v0, v16
574574
; ZVFHMIN-NEXT: vfabs.v v8, v24, v0.t
575575
; ZVFHMIN-NEXT: lui a2, 307200
576576
; ZVFHMIN-NEXT: fmv.w.x fa5, a2
577577
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
578-
; ZVFHMIN-NEXT: vmflt.vf v17, v8, fa5, v0.t
578+
; ZVFHMIN-NEXT: vmflt.vf v16, v8, fa5, v0.t
579579
; ZVFHMIN-NEXT: frflags a2
580580
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
581-
; ZVFHMIN-NEXT: vmv1r.v v0, v17
581+
; ZVFHMIN-NEXT: vmv1r.v v0, v16
582582
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v24, v0.t
583583
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
584584
; ZVFHMIN-NEXT: fsflags a2
@@ -591,23 +591,19 @@ define <vscale x 32 x half> @vp_nearbyint_nxv32f16_unmasked(<vscale x 32 x half>
591591
; ZVFHMIN-NEXT: mv a0, a1
592592
; ZVFHMIN-NEXT: .LBB11_2:
593593
; ZVFHMIN-NEXT: addi a1, sp, 16
594-
; ZVFHMIN-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
595-
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v16
594+
; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
595+
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
596596
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
597-
; ZVFHMIN-NEXT: vmv1r.v v0, v1
598-
; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t
599-
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
600-
; ZVFHMIN-NEXT: vmflt.vf v1, v16, fa5, v0.t
597+
; ZVFHMIN-NEXT: vfabs.v v24, v16
598+
; ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
601599
; ZVFHMIN-NEXT: frflags a0
602-
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
603-
; ZVFHMIN-NEXT: vmv1r.v v0, v1
604-
; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v24, v0.t
605-
; ZVFHMIN-NEXT: vfcvt.f.x.v v16, v16, v0.t
600+
; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
601+
; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
606602
; ZVFHMIN-NEXT: fsflags a0
607603
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
608-
; ZVFHMIN-NEXT: vfsgnj.vv v24, v16, v24, v0.t
604+
; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
609605
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
610-
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v24
606+
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
611607
; ZVFHMIN-NEXT: csrr a0, vlenb
612608
; ZVFHMIN-NEXT: slli a0, a0, 3
613609
; ZVFHMIN-NEXT: add sp, sp, a0

‎llvm/test/CodeGen/RISCV/rvv/rint-vp.ll

Lines changed: 13 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -517,47 +517,42 @@ define <vscale x 32 x half> @vp_rint_nxv32f16_unmasked(<vscale x 32 x half> %va,
517517
; ZVFHMIN-NEXT: and a3, a4, a3
518518
; ZVFHMIN-NEXT: srli a2, a2, 2
519519
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
520-
; ZVFHMIN-NEXT: vslidedown.vx v17, v16, a2
520+
; ZVFHMIN-NEXT: vslidedown.vx v16, v16, a2
521521
; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma
522522
; ZVFHMIN-NEXT: addi a2, sp, 16
523523
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
524524
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12
525525
; ZVFHMIN-NEXT: vsetvli zero, a3, e32, m8, ta, ma
526-
; ZVFHMIN-NEXT: vmv1r.v v0, v17
526+
; ZVFHMIN-NEXT: vmv1r.v v0, v16
527527
; ZVFHMIN-NEXT: vfabs.v v8, v24, v0.t
528528
; ZVFHMIN-NEXT: lui a2, 307200
529529
; ZVFHMIN-NEXT: fmv.w.x fa5, a2
530530
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
531-
; ZVFHMIN-NEXT: vmflt.vf v17, v8, fa5, v0.t
531+
; ZVFHMIN-NEXT: vmflt.vf v16, v8, fa5, v0.t
532532
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
533-
; ZVFHMIN-NEXT: vmv1r.v v0, v17
533+
; ZVFHMIN-NEXT: vmv1r.v v0, v16
534534
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v24, v0.t
535535
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
536536
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
537537
; ZVFHMIN-NEXT: vfsgnj.vv v24, v8, v24, v0.t
538538
; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma
539-
; ZVFHMIN-NEXT: vfncvt.f.f.w v20, v24
539+
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24
540540
; ZVFHMIN-NEXT: bltu a0, a1, .LBB11_2
541541
; ZVFHMIN-NEXT: # %bb.1:
542542
; ZVFHMIN-NEXT: mv a0, a1
543543
; ZVFHMIN-NEXT: .LBB11_2:
544544
; ZVFHMIN-NEXT: addi a1, sp, 16
545-
; ZVFHMIN-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
546-
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
545+
; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
546+
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
547547
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
548-
; ZVFHMIN-NEXT: vmv1r.v v0, v16
549-
; ZVFHMIN-NEXT: vfabs.v v8, v24, v0.t
550-
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
551-
; ZVFHMIN-NEXT: vmflt.vf v16, v8, fa5, v0.t
552-
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
553-
; ZVFHMIN-NEXT: vmv1r.v v0, v16
554-
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v24, v0.t
555-
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
548+
; ZVFHMIN-NEXT: vfabs.v v24, v16
549+
; ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
550+
; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
551+
; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
556552
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
557-
; ZVFHMIN-NEXT: vfsgnj.vv v24, v8, v24, v0.t
553+
; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
558554
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
559-
; ZVFHMIN-NEXT: vfncvt.f.f.w v16, v24
560-
; ZVFHMIN-NEXT: vmv8r.v v8, v16
555+
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
561556
; ZVFHMIN-NEXT: csrr a0, vlenb
562557
; ZVFHMIN-NEXT: slli a0, a0, 3
563558
; ZVFHMIN-NEXT: add sp, sp, a0

‎llvm/test/CodeGen/RISCV/rvv/round-vp.ll

Lines changed: 13 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -565,51 +565,46 @@ define <vscale x 32 x half> @vp_round_nxv32f16_unmasked(<vscale x 32 x half> %va
565565
; ZVFHMIN-NEXT: and a3, a4, a3
566566
; ZVFHMIN-NEXT: srli a2, a2, 2
567567
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
568-
; ZVFHMIN-NEXT: vslidedown.vx v17, v16, a2
568+
; ZVFHMIN-NEXT: vslidedown.vx v16, v16, a2
569569
; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma
570570
; ZVFHMIN-NEXT: addi a2, sp, 16
571571
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
572572
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12
573573
; ZVFHMIN-NEXT: vsetvli zero, a3, e32, m8, ta, ma
574-
; ZVFHMIN-NEXT: vmv1r.v v0, v17
574+
; ZVFHMIN-NEXT: vmv1r.v v0, v16
575575
; ZVFHMIN-NEXT: vfabs.v v8, v24, v0.t
576576
; ZVFHMIN-NEXT: lui a2, 307200
577577
; ZVFHMIN-NEXT: fmv.w.x fa5, a2
578578
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
579-
; ZVFHMIN-NEXT: vmflt.vf v17, v8, fa5, v0.t
579+
; ZVFHMIN-NEXT: vmflt.vf v16, v8, fa5, v0.t
580580
; ZVFHMIN-NEXT: fsrmi a2, 4
581581
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
582-
; ZVFHMIN-NEXT: vmv1r.v v0, v17
582+
; ZVFHMIN-NEXT: vmv1r.v v0, v16
583583
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v24, v0.t
584584
; ZVFHMIN-NEXT: fsrm a2
585585
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
586586
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
587587
; ZVFHMIN-NEXT: vfsgnj.vv v24, v8, v24, v0.t
588588
; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma
589-
; ZVFHMIN-NEXT: vfncvt.f.f.w v20, v24
589+
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24
590590
; ZVFHMIN-NEXT: bltu a0, a1, .LBB11_2
591591
; ZVFHMIN-NEXT: # %bb.1:
592592
; ZVFHMIN-NEXT: mv a0, a1
593593
; ZVFHMIN-NEXT: .LBB11_2:
594594
; ZVFHMIN-NEXT: addi a1, sp, 16
595-
; ZVFHMIN-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
596-
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
595+
; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
596+
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
597597
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
598-
; ZVFHMIN-NEXT: vmv1r.v v0, v16
599-
; ZVFHMIN-NEXT: vfabs.v v8, v24, v0.t
600-
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
601-
; ZVFHMIN-NEXT: vmflt.vf v16, v8, fa5, v0.t
598+
; ZVFHMIN-NEXT: vfabs.v v24, v16
599+
; ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
602600
; ZVFHMIN-NEXT: fsrmi a0, 4
603-
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
604-
; ZVFHMIN-NEXT: vmv1r.v v0, v16
605-
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v24, v0.t
601+
; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
606602
; ZVFHMIN-NEXT: fsrm a0
607-
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
603+
; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
608604
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
609-
; ZVFHMIN-NEXT: vfsgnj.vv v24, v8, v24, v0.t
605+
; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
610606
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
611-
; ZVFHMIN-NEXT: vfncvt.f.f.w v16, v24
612-
; ZVFHMIN-NEXT: vmv8r.v v8, v16
607+
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
613608
; ZVFHMIN-NEXT: csrr a0, vlenb
614609
; ZVFHMIN-NEXT: slli a0, a0, 3
615610
; ZVFHMIN-NEXT: add sp, sp, a0

‎llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll

Lines changed: 13 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -565,51 +565,46 @@ define <vscale x 32 x half> @vp_roundeven_nxv32f16_unmasked(<vscale x 32 x half>
565565
; ZVFHMIN-NEXT: and a3, a4, a3
566566
; ZVFHMIN-NEXT: srli a2, a2, 2
567567
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
568-
; ZVFHMIN-NEXT: vslidedown.vx v17, v16, a2
568+
; ZVFHMIN-NEXT: vslidedown.vx v16, v16, a2
569569
; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma
570570
; ZVFHMIN-NEXT: addi a2, sp, 16
571571
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
572572
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12
573573
; ZVFHMIN-NEXT: vsetvli zero, a3, e32, m8, ta, ma
574-
; ZVFHMIN-NEXT: vmv1r.v v0, v17
574+
; ZVFHMIN-NEXT: vmv1r.v v0, v16
575575
; ZVFHMIN-NEXT: vfabs.v v8, v24, v0.t
576576
; ZVFHMIN-NEXT: lui a2, 307200
577577
; ZVFHMIN-NEXT: fmv.w.x fa5, a2
578578
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
579-
; ZVFHMIN-NEXT: vmflt.vf v17, v8, fa5, v0.t
579+
; ZVFHMIN-NEXT: vmflt.vf v16, v8, fa5, v0.t
580580
; ZVFHMIN-NEXT: fsrmi a2, 0
581581
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
582-
; ZVFHMIN-NEXT: vmv1r.v v0, v17
582+
; ZVFHMIN-NEXT: vmv1r.v v0, v16
583583
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v24, v0.t
584584
; ZVFHMIN-NEXT: fsrm a2
585585
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
586586
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
587587
; ZVFHMIN-NEXT: vfsgnj.vv v24, v8, v24, v0.t
588588
; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma
589-
; ZVFHMIN-NEXT: vfncvt.f.f.w v20, v24
589+
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24
590590
; ZVFHMIN-NEXT: bltu a0, a1, .LBB11_2
591591
; ZVFHMIN-NEXT: # %bb.1:
592592
; ZVFHMIN-NEXT: mv a0, a1
593593
; ZVFHMIN-NEXT: .LBB11_2:
594594
; ZVFHMIN-NEXT: addi a1, sp, 16
595-
; ZVFHMIN-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
596-
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
595+
; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
596+
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
597597
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
598-
; ZVFHMIN-NEXT: vmv1r.v v0, v16
599-
; ZVFHMIN-NEXT: vfabs.v v8, v24, v0.t
600-
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
601-
; ZVFHMIN-NEXT: vmflt.vf v16, v8, fa5, v0.t
598+
; ZVFHMIN-NEXT: vfabs.v v24, v16
599+
; ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
602600
; ZVFHMIN-NEXT: fsrmi a0, 0
603-
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
604-
; ZVFHMIN-NEXT: vmv1r.v v0, v16
605-
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v24, v0.t
601+
; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
606602
; ZVFHMIN-NEXT: fsrm a0
607-
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
603+
; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
608604
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
609-
; ZVFHMIN-NEXT: vfsgnj.vv v24, v8, v24, v0.t
605+
; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
610606
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
611-
; ZVFHMIN-NEXT: vfncvt.f.f.w v16, v24
612-
; ZVFHMIN-NEXT: vmv8r.v v8, v16
607+
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
613608
; ZVFHMIN-NEXT: csrr a0, vlenb
614609
; ZVFHMIN-NEXT: slli a0, a0, 3
615610
; ZVFHMIN-NEXT: add sp, sp, a0

‎llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll

Lines changed: 13 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -565,51 +565,46 @@ define <vscale x 32 x half> @vp_roundtozero_nxv32f16_unmasked(<vscale x 32 x hal
565565
; ZVFHMIN-NEXT: and a3, a4, a3
566566
; ZVFHMIN-NEXT: srli a2, a2, 2
567567
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
568-
; ZVFHMIN-NEXT: vslidedown.vx v17, v16, a2
568+
; ZVFHMIN-NEXT: vslidedown.vx v16, v16, a2
569569
; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma
570570
; ZVFHMIN-NEXT: addi a2, sp, 16
571571
; ZVFHMIN-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
572572
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12
573573
; ZVFHMIN-NEXT: vsetvli zero, a3, e32, m8, ta, ma
574-
; ZVFHMIN-NEXT: vmv1r.v v0, v17
574+
; ZVFHMIN-NEXT: vmv1r.v v0, v16
575575
; ZVFHMIN-NEXT: vfabs.v v8, v24, v0.t
576576
; ZVFHMIN-NEXT: lui a2, 307200
577577
; ZVFHMIN-NEXT: fmv.w.x fa5, a2
578578
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
579-
; ZVFHMIN-NEXT: vmflt.vf v17, v8, fa5, v0.t
579+
; ZVFHMIN-NEXT: vmflt.vf v16, v8, fa5, v0.t
580580
; ZVFHMIN-NEXT: fsrmi a2, 1
581581
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
582-
; ZVFHMIN-NEXT: vmv1r.v v0, v17
582+
; ZVFHMIN-NEXT: vmv1r.v v0, v16
583583
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v24, v0.t
584584
; ZVFHMIN-NEXT: fsrm a2
585585
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
586586
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
587587
; ZVFHMIN-NEXT: vfsgnj.vv v24, v8, v24, v0.t
588588
; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma
589-
; ZVFHMIN-NEXT: vfncvt.f.f.w v20, v24
589+
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24
590590
; ZVFHMIN-NEXT: bltu a0, a1, .LBB11_2
591591
; ZVFHMIN-NEXT: # %bb.1:
592592
; ZVFHMIN-NEXT: mv a0, a1
593593
; ZVFHMIN-NEXT: .LBB11_2:
594594
; ZVFHMIN-NEXT: addi a1, sp, 16
595-
; ZVFHMIN-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
596-
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
595+
; ZVFHMIN-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
596+
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
597597
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
598-
; ZVFHMIN-NEXT: vmv1r.v v0, v16
599-
; ZVFHMIN-NEXT: vfabs.v v8, v24, v0.t
600-
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
601-
; ZVFHMIN-NEXT: vmflt.vf v16, v8, fa5, v0.t
598+
; ZVFHMIN-NEXT: vfabs.v v24, v16
599+
; ZVFHMIN-NEXT: vmflt.vf v0, v24, fa5
602600
; ZVFHMIN-NEXT: fsrmi a0, 1
603-
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma
604-
; ZVFHMIN-NEXT: vmv1r.v v0, v16
605-
; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v24, v0.t
601+
; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t
606602
; ZVFHMIN-NEXT: fsrm a0
607-
; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t
603+
; ZVFHMIN-NEXT: vfcvt.f.x.v v24, v24, v0.t
608604
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu
609-
; ZVFHMIN-NEXT: vfsgnj.vv v24, v8, v24, v0.t
605+
; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
610606
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
611-
; ZVFHMIN-NEXT: vfncvt.f.f.w v16, v24
612-
; ZVFHMIN-NEXT: vmv8r.v v8, v16
607+
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
613608
; ZVFHMIN-NEXT: csrr a0, vlenb
614609
; ZVFHMIN-NEXT: slli a0, a0, 3
615610
; ZVFHMIN-NEXT: add sp, sp, a0

‎llvm/test/CodeGen/RISCV/rvv/vcopysign-vp.ll

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -312,7 +312,7 @@ define <vscale x 32 x half> @vfsgnj_vv_nxv32f16_unmasked(<vscale x 32 x half> %v
312312
; ZVFHMIN-NEXT: sub sp, sp, a1
313313
; ZVFHMIN-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
314314
; ZVFHMIN-NEXT: vsetvli a1, zero, e8, m4, ta, ma
315-
; ZVFHMIN-NEXT: vmset.m v1
315+
; ZVFHMIN-NEXT: vmset.m v24
316316
; ZVFHMIN-NEXT: csrr a2, vlenb
317317
; ZVFHMIN-NEXT: slli a1, a2, 1
318318
; ZVFHMIN-NEXT: sub a3, a0, a1
@@ -321,7 +321,7 @@ define <vscale x 32 x half> @vfsgnj_vv_nxv32f16_unmasked(<vscale x 32 x half> %v
321321
; ZVFHMIN-NEXT: and a3, a4, a3
322322
; ZVFHMIN-NEXT: srli a2, a2, 2
323323
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
324-
; ZVFHMIN-NEXT: vslidedown.vx v0, v1, a2
324+
; ZVFHMIN-NEXT: vslidedown.vx v0, v24, a2
325325
; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma
326326
; ZVFHMIN-NEXT: addi a2, sp, 16
327327
; ZVFHMIN-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
@@ -340,8 +340,7 @@ define <vscale x 32 x half> @vfsgnj_vv_nxv32f16_unmasked(<vscale x 32 x half> %v
340340
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v24
341341
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
342342
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
343-
; ZVFHMIN-NEXT: vmv1r.v v0, v1
344-
; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16, v0.t
343+
; ZVFHMIN-NEXT: vfsgnj.vv v16, v24, v16
345344
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
346345
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
347346
; ZVFHMIN-NEXT: csrr a0, vlenb

‎llvm/test/CodeGen/RISCV/rvv/vfabs-vp.ll

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -291,19 +291,18 @@ define <vscale x 32 x half> @vfabs_vv_nxv32f16_unmasked(<vscale x 32 x half> %va
291291
; ZVFHMIN-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
292292
; ZVFHMIN-NEXT: vslidedown.vx v0, v16, a2
293293
; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma
294-
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v12
294+
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v12
295295
; ZVFHMIN-NEXT: vsetvli zero, a3, e32, m8, ta, ma
296-
; ZVFHMIN-NEXT: vfabs.v v24, v24, v0.t
296+
; ZVFHMIN-NEXT: vfabs.v v16, v16, v0.t
297297
; ZVFHMIN-NEXT: vsetvli a2, zero, e16, m4, ta, ma
298-
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v24
298+
; ZVFHMIN-NEXT: vfncvt.f.f.w v12, v16
299299
; ZVFHMIN-NEXT: bltu a0, a1, .LBB11_2
300300
; ZVFHMIN-NEXT: # %bb.1:
301301
; ZVFHMIN-NEXT: mv a0, a1
302302
; ZVFHMIN-NEXT: .LBB11_2:
303-
; ZVFHMIN-NEXT: vfwcvt.f.f.v v24, v8
303+
; ZVFHMIN-NEXT: vfwcvt.f.f.v v16, v8
304304
; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m8, ta, ma
305-
; ZVFHMIN-NEXT: vmv1r.v v0, v16
306-
; ZVFHMIN-NEXT: vfabs.v v16, v24, v0.t
305+
; ZVFHMIN-NEXT: vfabs.v v16, v16
307306
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
308307
; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v16
309308
; ZVFHMIN-NEXT: ret

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