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| 1 | +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 |
| 2 | +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le -mcpu=pwr9 < %s | FileCheck %s |
| 3 | + |
| 4 | +define <12 x i8> @zext_abdu(<12 x i8> %a, <12 x i8> %b) { |
| 5 | +; CHECK-LABEL: zext_abdu: |
| 6 | +; CHECK: # %bb.0: # %entry |
| 7 | +; CHECK-NEXT: addis 3, 2, .LCPI0_0@toc@ha |
| 8 | +; CHECK-NEXT: xxlxor 36, 36, 36 |
| 9 | +; CHECK-NEXT: addi 3, 3, .LCPI0_0@toc@l |
| 10 | +; CHECK-NEXT: lxv 37, 0(3) |
| 11 | +; CHECK-NEXT: addis 3, 2, .LCPI0_1@toc@ha |
| 12 | +; CHECK-NEXT: addi 3, 3, .LCPI0_1@toc@l |
| 13 | +; CHECK-NEXT: lxv 33, 0(3) |
| 14 | +; CHECK-NEXT: addis 3, 2, .LCPI0_2@toc@ha |
| 15 | +; CHECK-NEXT: vperm 0, 4, 2, 5 |
| 16 | +; CHECK-NEXT: vperm 5, 4, 3, 5 |
| 17 | +; CHECK-NEXT: addi 3, 3, .LCPI0_2@toc@l |
| 18 | +; CHECK-NEXT: lxv 39, 0(3) |
| 19 | +; CHECK-NEXT: vperm 6, 4, 2, 1 |
| 20 | +; CHECK-NEXT: vperm 1, 4, 3, 1 |
| 21 | +; CHECK-NEXT: vperm 2, 4, 2, 7 |
| 22 | +; CHECK-NEXT: vperm 3, 4, 3, 7 |
| 23 | +; CHECK-NEXT: xvnegsp 36, 38 |
| 24 | +; CHECK-NEXT: xvnegsp 35, 35 |
| 25 | +; CHECK-NEXT: xvnegsp 34, 34 |
| 26 | +; CHECK-NEXT: vabsduw 2, 2, 3 |
| 27 | +; CHECK-NEXT: xvnegsp 35, 33 |
| 28 | +; CHECK-NEXT: vabsduw 3, 4, 3 |
| 29 | +; CHECK-NEXT: xvnegsp 36, 37 |
| 30 | +; CHECK-NEXT: xvnegsp 37, 32 |
| 31 | +; CHECK-NEXT: vpkuwum 2, 2, 2 |
| 32 | +; CHECK-NEXT: vabsduw 4, 5, 4 |
| 33 | +; CHECK-NEXT: vpkuwum 3, 4, 3 |
| 34 | +; CHECK-NEXT: vpkuhum 2, 2, 3 |
| 35 | +; CHECK-NEXT: blr |
| 36 | +entry: |
| 37 | + %aa = zext <12 x i8> %a to <12 x i32> |
| 38 | + %bb = zext <12 x i8> %b to <12 x i32> |
| 39 | + %s = sub nsw <12 x i32> %aa, %bb |
| 40 | + %c = icmp slt <12 x i32> %s, zeroinitializer |
| 41 | + %ss = sub nsw <12 x i32> zeroinitializer, %s |
| 42 | + %sel = select <12 x i1> %c, <12 x i32> %ss, <12 x i32> %s |
| 43 | + %ret = trunc <12 x i32> %sel to <12 x i8> |
| 44 | + ret <12 x i8> %ret |
| 45 | +} |
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