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AMDGPU/GlobalISel: Use getSubRegFromChannel (#100732)
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-23
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1 file changed

+3
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llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

Lines changed: 3 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -2169,27 +2169,6 @@ bool AMDGPUInstructionSelector::selectG_SELECT(MachineInstr &I) const {
21692169
return Ret;
21702170
}
21712171

2172-
static int sizeToSubRegIndex(unsigned Size) {
2173-
switch (Size) {
2174-
case 32:
2175-
return AMDGPU::sub0;
2176-
case 64:
2177-
return AMDGPU::sub0_sub1;
2178-
case 96:
2179-
return AMDGPU::sub0_sub1_sub2;
2180-
case 128:
2181-
return AMDGPU::sub0_sub1_sub2_sub3;
2182-
case 256:
2183-
return AMDGPU::sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7;
2184-
default:
2185-
if (Size < 32)
2186-
return AMDGPU::sub0;
2187-
if (Size > 256)
2188-
return -1;
2189-
return sizeToSubRegIndex(llvm::bit_ceil(Size));
2190-
}
2191-
}
2192-
21932172
bool AMDGPUInstructionSelector::selectG_TRUNC(MachineInstr &I) const {
21942173
Register DstReg = I.getOperand(0).getReg();
21952174
Register SrcReg = I.getOperand(1).getReg();
@@ -2293,8 +2272,9 @@ bool AMDGPUInstructionSelector::selectG_TRUNC(MachineInstr &I) const {
22932272
return false;
22942273

22952274
if (SrcSize > 32) {
2296-
int SubRegIdx = sizeToSubRegIndex(DstSize);
2297-
if (SubRegIdx == -1)
2275+
unsigned SubRegIdx =
2276+
DstSize < 32 ? AMDGPU::sub0 : TRI.getSubRegFromChannel(0, DstSize / 32);
2277+
if (SubRegIdx == AMDGPU::NoSubRegister)
22982278
return false;
22992279

23002280
// Deal with weird cases where the class only partially supports the subreg

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