[DAG] Add test coverage for Issue #66603

Author: RKSimon

llvm/test/CodeGen/AArch64/pr66603.ll

@@ -0,0 +1,13 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc < %s -mtriple=aarch64-- -verify-machineinstrs | FileCheck %s
+
+define i32 @PR66603(double %x) nounwind {
+; CHECK-LABEL: PR66603:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fcvtzs w0, d0
+; CHECK-NEXT:    ret
+  %as_i8 = fptosi double %x to i8
+  %frozen_i8 = freeze i8 %as_i8
+  %ext = sext i8 %frozen_i8 to i32
+  ret i32 %ext
+}

llvm/test/CodeGen/RISCV/pr66603.ll

@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc < %s -mtriple=riscv32-- -mattr=+d -verify-machineinstrs | FileCheck %s -check-prefix=RV32
+; RUN: llc < %s -mtriple=riscv64-- -mattr=+d -verify-machineinstrs | FileCheck %s -check-prefix=RV64
+
+define i32 @PR66603(double %x) nounwind {
+; RV32-LABEL: PR66603:
+; RV32:       # %bb.0:
+; RV32-NEXT:    fcvt.w.d a0, fa0, rtz
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: PR66603:
+; RV64:       # %bb.0:
+; RV64-NEXT:    fcvt.l.d a0, fa0, rtz
+; RV64-NEXT:    ret
+  %as_i8 = fptosi double %x to i8
+  %frozen_i8 = freeze i8 %as_i8
+  %ext = sext i8 %frozen_i8 to i32
+  ret i32 %ext
+}