@@ -29,13 +29,13 @@ define i16 @test(ptr %arg, i64 %N) {
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; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 2
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; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_MEMCHECK:%.*]]
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; CHECK: vector.memcheck:
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- ; CHECK-NEXT: [[UGLYGEP :%.*]] = getelementptr i8, ptr [[L_2_LCSSA]], i64 2
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- ; CHECK-NEXT: [[UGLYGEP5 :%.*]] = getelementptr i8, ptr [[L_1_LCSSA]], i64 2
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+ ; CHECK-NEXT: [[SCEVGEP :%.*]] = getelementptr i8, ptr [[L_2_LCSSA]], i64 2
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+ ; CHECK-NEXT: [[SCEVGEP5 :%.*]] = getelementptr i8, ptr [[L_1_LCSSA]], i64 2
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; CHECK-NEXT: [[TMP1:%.*]] = shl i64 [[N]], 1
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; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 4
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- ; CHECK-NEXT: [[UGLYGEP6 :%.*]] = getelementptr i8, ptr [[L_1_LCSSA]], i64 [[TMP2]]
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- ; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[L_2_LCSSA]], [[UGLYGEP6 ]]
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- ; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[UGLYGEP5 ]], [[UGLYGEP ]]
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+ ; CHECK-NEXT: [[SCEVGEP6 :%.*]] = getelementptr i8, ptr [[L_1_LCSSA]], i64 [[TMP2]]
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+ ; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[L_2_LCSSA]], [[SCEVGEP6 ]]
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+ ; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[SCEVGEP5 ]], [[SCEVGEP ]]
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; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]
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; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
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; CHECK: vector.ph:
@@ -48,10 +48,10 @@ define i16 @test(ptr %arg, i64 %N) {
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; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw i64 [[TMP3]], 1
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; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i16, ptr [[L_1]], i64 [[TMP4]]
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; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i16, ptr [[TMP5]], i32 0
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- ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i16>, ptr [[TMP6]], align 2, !alias.scope !0
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+ ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i16>, ptr [[TMP6]], align 2, !alias.scope [[META0:![0-9]+]]
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; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i16, ptr [[L_2]], i64 0
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; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i16> [[WIDE_LOAD]], i32 1
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- ; CHECK-NEXT: store i16 [[TMP8]], ptr [[TMP7]], align 2, !alias.scope !3 , !noalias !0
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+ ; CHECK-NEXT: store i16 [[TMP8]], ptr [[TMP7]], align 2, !alias.scope [[META3:![0-9]+]] , !noalias [[META0]]
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
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; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[TMP9]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
@@ -74,7 +74,7 @@ define i16 @test(ptr %arg, i64 %N) {
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; CHECK-NEXT: [[LOOP_L_1:%.*]] = load i16, ptr [[GEP_1]], align 2
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; CHECK-NEXT: [[GEP_2:%.*]] = getelementptr inbounds i16, ptr [[L_2_LCSSA]], i64 0
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; CHECK-NEXT: store i16 [[LOOP_L_1]], ptr [[GEP_2]], align 2
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- ; CHECK-NEXT: br i1 [[C_5]], label [[LOOP_3]], label [[EXIT_LOOPEXIT]], !llvm.loop [[LOOP7 :![0-9]+]]
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+ ; CHECK-NEXT: br i1 [[C_5]], label [[LOOP_3]], label [[EXIT_LOOPEXIT]], !llvm.loop [[LOOP8 :![0-9]+]]
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; CHECK: exit.loopexit:
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; CHECK-NEXT: br label [[EXIT:%.*]]
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; CHECK: exit.loopexit1:
@@ -138,31 +138,17 @@ define void @test2(ptr %dst) {
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; CHECK-NEXT: [[INDVAR_NEXT]] = add i32 [[INDVAR]], 1
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; CHECK-NEXT: br i1 [[C_1]], label [[LOOP_2]], label [[LOOP_3_PH:%.*]]
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; CHECK: loop.3.ph:
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- ; CHECK-NEXT: [[INDVAR_LCSSA1:%.*]] = phi i32 [ [[INDVAR]], [[LOOP_2]] ]
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; CHECK-NEXT: [[INDVAR_LCSSA:%.*]] = phi i32 [ [[INDVAR]], [[LOOP_2]] ]
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; CHECK-NEXT: [[IV_1_LCSSA:%.*]] = phi i64 [ [[IV_1]], [[LOOP_2]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = and i64 [[IV_1_LCSSA]], 4294967295
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- ; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[INDVAR_LCSSA1 ]], -1
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+ ; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[INDVAR_LCSSA ]], -1
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; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 1000
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- ; CHECK-NEXT: [[SMIN2 :%.*]] = call i32 @llvm.smin.i32(i32 [[TMP2]], i32 1)
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- ; CHECK-NEXT: [[TMP3:%.*]] = sub i32 [[TMP2]], [[SMIN2 ]]
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+ ; CHECK-NEXT: [[SMIN :%.*]] = call i32 @llvm.smin.i32(i32 [[TMP2]], i32 1)
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+ ; CHECK-NEXT: [[TMP3:%.*]] = sub i32 [[TMP2]], [[SMIN ]]
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; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
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; CHECK-NEXT: [[TMP5:%.*]] = add nuw nsw i64 [[TMP4]], 1
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; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP5]], 2
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- ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]]
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- ; CHECK: vector.scevcheck:
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- ; CHECK-NEXT: [[TMP6:%.*]] = mul i32 [[INDVAR_LCSSA]], -1
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- ; CHECK-NEXT: [[TMP7:%.*]] = add i32 [[TMP6]], 1000
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- ; CHECK-NEXT: [[SMIN:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP7]], i32 1)
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- ; CHECK-NEXT: [[TMP8:%.*]] = sub i32 [[TMP7]], [[SMIN]]
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- ; CHECK-NEXT: [[TMP9:%.*]] = add i32 [[TMP6]], 999
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- ; CHECK-NEXT: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 1, i32 [[TMP8]])
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- ; CHECK-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL]], 0
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- ; CHECK-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL]], 1
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- ; CHECK-NEXT: [[TMP10:%.*]] = sub i32 [[TMP9]], [[MUL_RESULT]]
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- ; CHECK-NEXT: [[TMP11:%.*]] = icmp ugt i32 [[TMP10]], [[TMP9]]
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- ; CHECK-NEXT: [[TMP12:%.*]] = or i1 [[TMP11]], [[MUL_OVERFLOW]]
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- ; CHECK-NEXT: br i1 [[TMP12]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
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+ ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
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; CHECK: vector.ph:
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; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP5]], 2
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; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP5]], [[N_MOD_VF]]
@@ -171,21 +157,21 @@ define void @test2(ptr %dst) {
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[OFFSET_IDX:%.*]] = sub i64 [[TMP0]], [[INDEX]]
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- ; CHECK-NEXT: [[TMP13 :%.*]] = add i64 [[OFFSET_IDX]], 0
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- ; CHECK-NEXT: [[TMP14 :%.*]] = add nsw i64 [[TMP13 ]], -1
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- ; CHECK-NEXT: [[TMP15 :%.*]] = and i64 [[TMP14 ]], 4294967295
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- ; CHECK-NEXT: [[TMP16 :%.*]] = getelementptr inbounds i32, ptr [[DST:%.*]], i64 [[TMP15 ]]
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- ; CHECK-NEXT: [[TMP17 :%.*]] = getelementptr inbounds i32, ptr [[TMP16 ]], i32 0
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- ; CHECK-NEXT: [[TMP18 :%.*]] = getelementptr inbounds i32, ptr [[TMP17 ]], i32 -1
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- ; CHECK-NEXT: store <2 x i32> zeroinitializer, ptr [[TMP18 ]], align 4
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+ ; CHECK-NEXT: [[TMP6 :%.*]] = add i64 [[OFFSET_IDX]], 0
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+ ; CHECK-NEXT: [[TMP7 :%.*]] = add nsw i64 [[TMP6 ]], -1
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+ ; CHECK-NEXT: [[TMP8 :%.*]] = and i64 [[TMP7 ]], 4294967295
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+ ; CHECK-NEXT: [[TMP9 :%.*]] = getelementptr inbounds i32, ptr [[DST:%.*]], i64 [[TMP8 ]]
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+ ; CHECK-NEXT: [[TMP10 :%.*]] = getelementptr inbounds i32, ptr [[TMP9 ]], i32 0
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+ ; CHECK-NEXT: [[TMP11 :%.*]] = getelementptr inbounds i32, ptr [[TMP10 ]], i32 -1
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+ ; CHECK-NEXT: store <2 x i32> zeroinitializer, ptr [[TMP11 ]], align 4
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
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- ; CHECK-NEXT: [[TMP19 :%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
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- ; CHECK-NEXT: br i1 [[TMP19 ]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8 :![0-9]+]]
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+ ; CHECK-NEXT: [[TMP12 :%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
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+ ; CHECK-NEXT: br i1 [[TMP12 ]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP9 :![0-9]+]]
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; CHECK: middle.block:
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; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP5]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[CMP_N]], label [[LOOP_1_LATCH:%.*]], label [[SCALAR_PH]]
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; CHECK: scalar.ph:
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- ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[TMP0]], [[LOOP_3_PH]] ], [ [[TMP0]], [[VECTOR_SCEVCHECK]] ]
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+ ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[TMP0]], [[LOOP_3_PH]] ]
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; CHECK-NEXT: br label [[LOOP_3:%.*]]
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; CHECK: loop.3:
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; CHECK-NEXT: [[IV_2:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_2_NEXT:%.*]], [[LOOP_3]] ]
@@ -195,7 +181,7 @@ define void @test2(ptr %dst) {
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; CHECK-NEXT: store i32 0, ptr [[GEP_DST]], align 4
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; CHECK-NEXT: [[IV_2_TRUNC:%.*]] = trunc i64 [[IV_2]] to i32
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; CHECK-NEXT: [[EC:%.*]] = icmp sgt i32 [[IV_2_TRUNC]], 1
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- ; CHECK-NEXT: br i1 [[EC]], label [[LOOP_3]], label [[LOOP_1_LATCH]], !llvm.loop [[LOOP9 :![0-9]+]]
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+ ; CHECK-NEXT: br i1 [[EC]], label [[LOOP_3]], label [[LOOP_1_LATCH]], !llvm.loop [[LOOP10 :![0-9]+]]
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; CHECK: loop.1.latch:
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; CHECK-NEXT: [[C_2:%.*]] = call i1 @cond()
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; CHECK-NEXT: br i1 [[C_2]], label [[EXIT:%.*]], label [[LOOP_1_HEADER]]
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