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[LV] Don't vectorize first-order recurrence with VF <vscale x 1 x ..>
The assertion added as part of #93395 surfaced cases where first-order recurrences are vectorized with <vscale x 1 x ..>. If vscale is 1, then we are unable to extract the penultimate value (second to last lane). Previously this case got mis-compiled, trying to extract from an invalid lane (-1) https://llvm.godbolt.org/z/3adzYYcf9. Fixes #97452.
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‎llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

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@@ -6813,6 +6813,11 @@ LoopVectorizationCostModel::getInstructionCost(Instruction *I, ElementCount VF,
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// First-order recurrences are replaced by vector shuffles inside the loop.
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if (VF.isVector() && Legal->isFixedOrderRecurrence(Phi)) {
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// For <vscale x 1 x i64>, if vscale = 1 we are unable to extract the
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// penultimate value of the recurrence.
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// TODO: Consider vscale_range info.
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if (VF.isScalable() && VF.getKnownMinValue() == 1)
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return InstructionCost::getInvalid();
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SmallVector<int> Mask(VF.getKnownMinValue());
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std::iota(Mask.begin(), Mask.end(), VF.getKnownMinValue() - 1);
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return TTI.getShuffleCost(TargetTransformInfo::SK_Splice,

‎llvm/test/Transforms/LoopVectorize/RISCV/first-order-recurrence-scalable-vf1.ll

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -p loop-vectorize -S %s | FileCheck %s
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target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
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target triple = "riscv64-unknown-linux-gnu"
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; Make sure we do not pick <vscale x 1 x i64> as VF for a loop with a
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; first-order recurrence.
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define i64 @pr97452_scalable_vf1_for(ptr %src) #0 {
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; CHECK-LABEL: define i64 @pr97452_scalable_vf1_for(
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; CHECK-SAME: ptr [[SRC:%.*]]) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[VECTOR_RECUR:%.*]] = phi <4 x i64> [ <i64 poison, i64 poison, i64 poison, i64 0>, %[[VECTOR_PH]] ], [ [[WIDE_LOAD1:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0
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; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 4
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; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 [[TMP0]]
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; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 [[TMP1]]
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; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP2]], i32 0
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; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP2]], i32 4
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; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP4]], align 8
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; CHECK-NEXT: [[WIDE_LOAD1]] = load <4 x i64>, ptr [[TMP5]], align 8
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
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; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 16
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; CHECK-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT_FOR_PHI:%.*]] = extractelement <4 x i64> [[WIDE_LOAD1]], i32 2
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; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <4 x i64> [[WIDE_LOAD1]], i32 3
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; CHECK-NEXT: br i1 false, label %[[EXIT:.*]], label %[[SCALAR_PH]]
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; CHECK: [[SCALAR_PH]]:
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; CHECK-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[VECTOR_RECUR_EXTRACT]], %[[MIDDLE_BLOCK]] ]
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 16, %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[SCALAR_RECUR:%.*]] = phi i64 [ [[SCALAR_RECUR_INIT]], %[[SCALAR_PH]] ], [ [[L:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
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; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 [[IV]]
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; CHECK-NEXT: [[L]] = load i64, ptr [[GEP]], align 8
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; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 22
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; CHECK-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: [[RES:%.*]] = phi i64 [ [[SCALAR_RECUR]], %[[LOOP]] ], [ [[VECTOR_RECUR_EXTRACT_FOR_PHI]], %[[MIDDLE_BLOCK]] ]
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; CHECK-NEXT: ret i64 [[RES]]
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;
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entry:
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br label %loop
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loop:
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%for = phi i64 [ 0, %entry ], [ %l, %loop ]
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%iv.next = add i64 %iv, 1
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%gep = getelementptr inbounds i64, ptr %src, i64 %iv
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%l = load i64, ptr %gep, align 8
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%ec = icmp eq i64 %iv, 22
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br i1 %ec, label %exit, label %loop
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exit:
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%res = phi i64 [ %for, %loop ]
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ret i64 %res
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}
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attributes #0 = { "target-features"="+64bit,+v,+zvl128b,+zvl256b" }
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;.
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; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
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; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
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; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
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; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
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;.

‎llvm/test/Transforms/LoopVectorize/first-order-recurrence-scalable-vf1.ll

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -p loop-vectorize -scalable-vectorization=on -force-vector-width=1 -force-target-supports-scalable-vectors=true -S %s | FileCheck %s
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target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
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define i64 @pr97452_scalable_vf1_for_live_out(ptr %src) {
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; CHECK-LABEL: define i64 @pr97452_scalable_vf1_for_live_out(
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; CHECK-SAME: ptr [[SRC:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[FOR:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[L:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
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; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 [[IV]]
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; CHECK-NEXT: [[L]] = load i64, ptr [[GEP]], align 8
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; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 22
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; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: [[RES:%.*]] = phi i64 [ [[FOR]], %[[LOOP]] ]
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; CHECK-NEXT: ret i64 [[RES]]
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;
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entry:
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br label %loop
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loop:
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%for = phi i64 [ 0, %entry ], [ %l, %loop ]
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%iv.next = add i64 %iv, 1
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%gep = getelementptr inbounds i64, ptr %src, i64 %iv
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%l = load i64, ptr %gep, align 8
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%ec = icmp eq i64 %iv, 22
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br i1 %ec, label %exit, label %loop
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exit:
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%res = phi i64 [ %for, %loop ]
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ret i64 %res
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}
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define void @pr97452_scalable_vf1_for_no_live_out(ptr %src, ptr noalias %dst) {
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; CHECK-LABEL: define void @pr97452_scalable_vf1_for_no_live_out(
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; CHECK-SAME: ptr [[SRC:%.*]], ptr noalias [[DST:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[FOR:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[L:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
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; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i64, ptr [[SRC]], i64 [[IV]]
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; CHECK-NEXT: [[L]] = load i64, ptr [[GEP]], align 8
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; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds i64, ptr [[DST]], i64 [[IV]]
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; CHECK-NEXT: store i64 [[L]], ptr [[GEP_DST]], align 8
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; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 22
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; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%for = phi i64 [ 0, %entry ], [ %l, %loop ]
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%iv.next = add i64 %iv, 1
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%gep = getelementptr inbounds i64, ptr %src, i64 %iv
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%l = load i64, ptr %gep, align 8
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%gep.dst = getelementptr inbounds i64, ptr %dst, i64 %iv
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store i64 %l, ptr %gep.dst
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%ec = icmp eq i64 %iv, 22
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br i1 %ec, label %exit, label %loop
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exit:
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ret void
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}

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