Skip to content

Commit 26ae98c

Browse files
arsenmarsenm
authored
AMDGPU: Replace undef global initializers in tests with poison (#131051)
1 parent 21cef8a commit 26ae98c

File tree

82 files changed

+180
-180
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

82 files changed

+180
-180
lines changed

‎llvm/test/CodeGen/AMDGPU/32-bit-local-address-space.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -80,7 +80,7 @@ define amdgpu_kernel void @mul_32bit_ptr(ptr addrspace(1) %out, ptr addrspace(3)
8080
ret void
8181
}
8282

83-
@g_lds = addrspace(3) global float undef, align 4
83+
@g_lds = addrspace(3) global float poison, align 4
8484

8585
; FUNC-LABEL: {{^}}infer_ptr_alignment_global_offset:
8686
; SI: v_mov_b32_e32 [[PTR:v[0-9]+]], 0{{$}}
@@ -93,7 +93,7 @@ define amdgpu_kernel void @infer_ptr_alignment_global_offset(ptr addrspace(1) %o
9393

9494

9595
@ptr = addrspace(3) global ptr addrspace(3) poison
96-
@dst = addrspace(3) global [16383 x i32] undef
96+
@dst = addrspace(3) global [16383 x i32] poison
9797

9898
; FUNC-LABEL: {{^}}global_ptr:
9999
; SI: ds_write_b32

‎llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -8,8 +8,8 @@
88
; FIXME: Merge with other test. DS offset folding doesn't work due to
99
; register bank copies, and no return optimization is missing.
1010

11-
@lds0 = internal addrspace(3) global [512 x i32] undef
12-
@lds1 = internal addrspace(3) global [512 x i64] undef, align 8
11+
@lds0 = internal addrspace(3) global [512 x i32] poison
12+
@lds1 = internal addrspace(3) global [512 x i64] poison, align 8
1313

1414
declare i32 @llvm.amdgcn.workitem.id.x() #0
1515

‎llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9,8 +9,8 @@
99
; FIXME: Merge with other test. DS offset folding doesn't work due to
1010
; register bank copies, and no return optimization is missing.
1111

12-
@lds0 = internal addrspace(3) global [512 x i32] undef, align 4
13-
@lds1 = internal addrspace(3) global [512 x i64] undef, align 8
12+
@lds0 = internal addrspace(3) global [512 x i32] poison, align 4
13+
@lds1 = internal addrspace(3) global [512 x i64] poison, align 8
1414

1515
declare i32 @llvm.amdgcn.workitem.id.x() #0
1616

‎llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.illegal.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
; ERR: LLVM ERROR: unable to legalize instruction: %{{[0-9]+}}:_(p5) = G_GLOBAL_VALUE @external_private (in function: fn_external_private)
55

66
@external_private = external addrspace(5) global i32, align 4
7-
@internal_private = internal addrspace(5) global i32 undef, align 4
7+
@internal_private = internal addrspace(5) global i32 poison, align 4
88

99
define ptr addrspace(5) @fn_external_private() {
1010
ret ptr addrspace(5) @external_private

‎llvm/test/CodeGen/AMDGPU/GlobalISel/hip.extern.shared.array.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=gfx900 -verify-machineinstrs -o - %s | FileCheck %s
22

3-
@lds0 = addrspace(3) global [512 x float] undef
4-
@lds1 = addrspace(3) global [256 x float] undef
5-
@lds2 = addrspace(3) global [4096 x float] undef
6-
@lds3 = addrspace(3) global [67 x i8] undef
3+
@lds0 = addrspace(3) global [512 x float] poison
4+
@lds1 = addrspace(3) global [256 x float] poison
5+
@lds2 = addrspace(3) global [4096 x float] poison
6+
@lds3 = addrspace(3) global [67 x i8] poison
77

88
@dynamic_shared0 = external addrspace(3) global [0 x float]
99
@dynamic_shared1 = external addrspace(3) global [0 x double]

‎llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constantexpr.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -stop-after=irtranslator -o - %s | FileCheck %s
33

4-
@var = global i32 undef
4+
@var = global i32 poison
55

66
define i32 @test() {
77
; CHECK-LABEL: name: test

‎llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,8 @@
22
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=bonaire -verify-machineinstrs < %s | FileCheck %s
33
; TODO: Replace with existing DAG tests
44

5-
@lds_512_4 = internal unnamed_addr addrspace(3) global [128 x i32] undef, align 4
6-
@lds_4_8 = addrspace(3) global i32 undef, align 8
5+
@lds_512_4 = internal unnamed_addr addrspace(3) global [128 x i32] poison, align 4
6+
@lds_4_8 = addrspace(3) global i32 poison, align 8
77

88
define amdgpu_kernel void @use_lds_globals(ptr addrspace(1) %out, ptr addrspace(3) %in) #0 {
99
; CHECK-LABEL: use_lds_globals:

‎llvm/test/CodeGen/AMDGPU/GlobalISel/lds-relocs.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
; FIXME: Merge with DAG test
33

44
@lds.external = external unnamed_addr addrspace(3) global [0 x i32]
5-
@lds.defined = unnamed_addr addrspace(3) global [8 x i32] undef, align 8
5+
@lds.defined = unnamed_addr addrspace(3) global [8 x i32] poison, align 8
66

77
; GCN-LABEL: {{^}}test_basic:
88
; GCN: s_add_u32 s0, lds.defined@abs32@lo, s0 ; encoding: [0xff,0x00,0x00,0x80,A,A,A,A]

‎llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -87,10 +87,10 @@ bb2:
8787

8888
; FIXME: These aren't localized because thesee were legalized before
8989
; the localizer, and are no longer G_GLOBAL_VALUE.
90-
@gv0 = addrspace(1) global i32 undef, align 4
91-
@gv1 = addrspace(1) global i32 undef, align 4
92-
@gv2 = addrspace(1) global i32 undef, align 4
93-
@gv3 = addrspace(1) global i32 undef, align 4
90+
@gv0 = addrspace(1) global i32 poison, align 4
91+
@gv1 = addrspace(1) global i32 poison, align 4
92+
@gv2 = addrspace(1) global i32 poison, align 4
93+
@gv3 = addrspace(1) global i32 poison, align 4
9494

9595
define amdgpu_kernel void @localize_globals(i1 %cond) {
9696
; GFX9-LABEL: localize_globals:
@@ -159,10 +159,10 @@ bb2:
159159
ret void
160160
}
161161

162-
@static.gv0 = internal addrspace(1) global i32 undef, align 4
163-
@static.gv1 = internal addrspace(1) global i32 undef, align 4
164-
@static.gv2 = internal addrspace(1) global i32 undef, align 4
165-
@static.gv3 = internal addrspace(1) global i32 undef, align 4
162+
@static.gv0 = internal addrspace(1) global i32 poison, align 4
163+
@static.gv1 = internal addrspace(1) global i32 poison, align 4
164+
@static.gv2 = internal addrspace(1) global i32 poison, align 4
165+
@static.gv3 = internal addrspace(1) global i32 poison, align 4
166166

167167
define void @localize_internal_globals(i1 %cond) {
168168
; GFX9-LABEL: localize_internal_globals:

‎llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -4,17 +4,17 @@
44

55
declare void @llvm.memcpy.p1.p4.i32(ptr addrspace(1) nocapture, ptr addrspace(4) nocapture, i32, i1) #0
66

7-
@lds.i32 = unnamed_addr addrspace(3) global i32 undef, align 4
8-
@lds.arr = unnamed_addr addrspace(3) global [256 x i32] undef, align 4
7+
@lds.i32 = unnamed_addr addrspace(3) global i32 poison, align 4
8+
@lds.arr = unnamed_addr addrspace(3) global [256 x i32] poison, align 4
99

10-
@global.i32 = unnamed_addr addrspace(1) global i32 undef, align 4
11-
@global.arr = unnamed_addr addrspace(1) global [256 x i32] undef, align 4
10+
@global.i32 = unnamed_addr addrspace(1) global i32 poison, align 4
11+
@global.arr = unnamed_addr addrspace(1) global [256 x i32] poison, align 4
1212

1313
;.
14-
; HSA: @lds.i32 = unnamed_addr addrspace(3) global i32 undef, align 4
15-
; HSA: @lds.arr = unnamed_addr addrspace(3) global [256 x i32] undef, align 4
16-
; HSA: @global.i32 = unnamed_addr addrspace(1) global i32 undef, align 4
17-
; HSA: @global.arr = unnamed_addr addrspace(1) global [256 x i32] undef, align 4
14+
; HSA: @lds.i32 = unnamed_addr addrspace(3) global i32 poison, align 4
15+
; HSA: @lds.arr = unnamed_addr addrspace(3) global [256 x i32] poison, align 4
16+
; HSA: @global.i32 = unnamed_addr addrspace(1) global i32 poison, align 4
17+
; HSA: @global.arr = unnamed_addr addrspace(1) global [256 x i32] poison, align 4
1818
;.
1919
define amdgpu_kernel void @store_cast_0_flat_to_group_addrspacecast() #1 {
2020
; HSA-LABEL: define {{[^@]+}}@store_cast_0_flat_to_group_addrspacecast

‎llvm/test/CodeGen/AMDGPU/addrspacecast-initializer-unsupported.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,6 @@
22

33
; ERROR: LLVM ERROR: Unsupported expression in static initializer: addrspacecast (ptr addrspace(3) @lds.arr to ptr addrspace(4))
44

5-
@lds.arr = unnamed_addr addrspace(3) global [256 x i32] undef, align 4
5+
@lds.arr = unnamed_addr addrspace(3) global [256 x i32] poison, align 4
66

77
@gv_flatptr_from_lds = unnamed_addr addrspace(2) global ptr addrspace(4) getelementptr ([256 x i32], ptr addrspace(4) addrspacecast (ptr addrspace(3) @lds.arr to ptr addrspace(4)), i64 0, i64 8), align 4

‎llvm/test/CodeGen/AMDGPU/addrspacecast-initializer.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@
1616
; CHECK: .quad constant.arr+32
1717
; CHECK: .size gv_flatptr_from_constant, 8
1818

19-
@global.arr = unnamed_addr addrspace(1) global [256 x i32] undef, align 4
19+
@global.arr = unnamed_addr addrspace(1) global [256 x i32] poison, align 4
2020
@constant.arr = external unnamed_addr addrspace(4) global [256 x i32], align 4
2121

2222
@gv_flatptr_from_global = unnamed_addr addrspace(4) global ptr addrspace(0) getelementptr ([256 x i32], ptr addrspace(0) addrspacecast (ptr addrspace(1) @global.arr to ptr addrspace(0)), i64 0, i64 8), align 4

‎llvm/test/CodeGen/AMDGPU/addrspacecast-known-non-null.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ define void @cast_alloca() {
2121
ret void
2222
}
2323

24-
@lds = internal unnamed_addr addrspace(3) global i8 undef, align 4
24+
@lds = internal unnamed_addr addrspace(3) global i8 poison, align 4
2525

2626
; CHECK-LABEL: {{^}}cast_lds_gv:
2727
; CHECK: s_mov_b64 s[{{[0-9]+}}:[[HIREG:[0-9]+]]], src_shared_base

‎llvm/test/CodeGen/AMDGPU/amdgpu-alias-analysis.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -220,7 +220,7 @@ define void @test_8_3(ptr %p) {
220220
ret void
221221
}
222222

223-
@shm = internal addrspace(3) global [2 x i8] undef, align 4
223+
@shm = internal addrspace(3) global [2 x i8] poison, align 4
224224

225225
; CHECK-LABEL: Function: test_8_4
226226
; CHECK: NoAlias: i8* %p, i8 addrspace(3)* %p1

‎llvm/test/CodeGen/AMDGPU/amdgpu-late-codegenprepare.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,7 @@ define amdgpu_kernel void @constant_from_offset_cast_global_null() {
4141
ret void
4242
}
4343

44-
@gv = unnamed_addr addrspace(1) global [64 x i8] undef, align 4
44+
@gv = unnamed_addr addrspace(1) global [64 x i8] poison, align 4
4545

4646
define amdgpu_kernel void @constant_from_offset_cast_global_gv() {
4747
; GFX9-LABEL: @constant_from_offset_cast_global_gv(

‎llvm/test/CodeGen/AMDGPU/amdpal-callable.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -125,7 +125,7 @@ define amdgpu_gfx float @simple_stack_recurse(float %arg0) #0 {
125125
ret float %add
126126
}
127127

128-
@lds = internal addrspace(3) global [64 x float] undef
128+
@lds = internal addrspace(3) global [64 x float] poison
129129

130130
define amdgpu_gfx float @simple_lds(float %arg0) #0 {
131131
%val = load float, ptr addrspace(3) @lds

‎llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -16,8 +16,8 @@
1616

1717
declare i32 @llvm.amdgcn.workitem.id.x()
1818

19-
@local_var32 = addrspace(3) global i32 undef, align 4
20-
@local_var64 = addrspace(3) global i64 undef, align 8
19+
@local_var32 = addrspace(3) global i32 poison, align 4
20+
@local_var64 = addrspace(3) global i64 poison, align 8
2121

2222
; Show what the atomic optimization pass will do for local pointers.
2323

‎llvm/test/CodeGen/AMDGPU/divergence-at-use.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 - < %s | FileCheck %s
22

3-
@local = addrspace(3) global i32 undef
3+
@local = addrspace(3) global i32 poison
44

55
define amdgpu_kernel void @reducible() {
66
; CHECK-LABEL: reducible:

‎llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@
66

77
declare i32 @llvm.amdgcn.workitem.id.x() #0
88

9-
@lds.obj = addrspace(3) global [256 x i32] undef, align 4
9+
@lds.obj = addrspace(3) global [256 x i32] poison, align 4
1010

1111
define amdgpu_kernel void @write_ds_sub0_offset0_global() #0 {
1212
; CI-LABEL: write_ds_sub0_offset0_global:

‎llvm/test/CodeGen/AMDGPU/ds_read2.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -6,8 +6,8 @@
66
; FIXME: We don't get cases where the address was an SGPR because we
77
; get a copy to the address register for each one.
88

9-
@lds = addrspace(3) global [512 x float] undef, align 4
10-
@lds.f64 = addrspace(3) global [512 x double] undef, align 8
9+
@lds = addrspace(3) global [512 x float] poison, align 4
10+
@lds.f64 = addrspace(3) global [512 x double] poison, align 8
1111

1212
define amdgpu_kernel void @simple_read2_f32(ptr addrspace(1) %out) #0 {
1313
; CI-LABEL: simple_read2_f32:
@@ -921,7 +921,7 @@ define amdgpu_kernel void @misaligned_read2_f64(ptr addrspace(1) %out, ptr addrs
921921
ret void
922922
}
923923

924-
@foo = addrspace(3) global [4 x i32] undef, align 4
924+
@foo = addrspace(3) global [4 x i32] poison, align 4
925925

926926
define amdgpu_kernel void @load_constant_adjacent_offsets(ptr addrspace(1) %out) {
927927
; CI-LABEL: load_constant_adjacent_offsets:
@@ -983,7 +983,7 @@ define amdgpu_kernel void @load_constant_disjoint_offsets(ptr addrspace(1) %out)
983983
ret void
984984
}
985985

986-
@bar = addrspace(3) global [4 x i64] undef, align 4
986+
@bar = addrspace(3) global [4 x i64] poison, align 4
987987

988988
define amdgpu_kernel void @load_misaligned64_constant_offsets(ptr addrspace(1) %out) {
989989
; CI-LABEL: load_misaligned64_constant_offsets:
@@ -1017,7 +1017,7 @@ define amdgpu_kernel void @load_misaligned64_constant_offsets(ptr addrspace(1) %
10171017
ret void
10181018
}
10191019

1020-
@bar.large = addrspace(3) global [4096 x i64] undef, align 4
1020+
@bar.large = addrspace(3) global [4096 x i64] poison, align 4
10211021

10221022
define amdgpu_kernel void @load_misaligned64_constant_large_offsets(ptr addrspace(1) %out) {
10231023
; CI-LABEL: load_misaligned64_constant_large_offsets:
@@ -1053,8 +1053,8 @@ define amdgpu_kernel void @load_misaligned64_constant_large_offsets(ptr addrspac
10531053
ret void
10541054
}
10551055

1056-
@sgemm.lA = internal unnamed_addr addrspace(3) global [264 x float] undef, align 4
1057-
@sgemm.lB = internal unnamed_addr addrspace(3) global [776 x float] undef, align 4
1056+
@sgemm.lA = internal unnamed_addr addrspace(3) global [264 x float] poison, align 4
1057+
@sgemm.lB = internal unnamed_addr addrspace(3) global [776 x float] poison, align 4
10581058

10591059
define amdgpu_kernel void @sgemm_inner_loop_read2_sequence(ptr addrspace(1) %C, i32 %lda, i32 %ldb) #0 {
10601060
; CI-LABEL: sgemm_inner_loop_read2_sequence:
@@ -1440,7 +1440,7 @@ define amdgpu_ps <2 x float> @ds_read_interp_read(i32 inreg %prims, ptr addrspac
14401440
ret <2 x float> %r1
14411441
}
14421442

1443-
@v2i32_align1 = internal addrspace(3) global [100 x <2 x i32>] undef, align 1
1443+
@v2i32_align1 = internal addrspace(3) global [100 x <2 x i32>] poison, align 1
14441444

14451445
define amdgpu_kernel void @read2_v2i32_align1_odd_offset(ptr addrspace(1) %out) {
14461446
; CI-LABEL: read2_v2i32_align1_odd_offset:

‎llvm/test/CodeGen/AMDGPU/ds_read2_offset_order.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; RUN: llc -mtriple=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI %s
22
; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI %s
33

4-
@lds = addrspace(3) global [512 x float] undef, align 4
4+
@lds = addrspace(3) global [512 x float] poison, align 4
55

66
; offset0 is larger than offset1
77

‎llvm/test/CodeGen/AMDGPU/ds_read2_superreg.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,11 @@
11
; RUN: llc -mtriple=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt,-enable-ds128 < %s | FileCheck --check-prefix=CI %s
22

3-
@lds = addrspace(3) global [512 x float] undef, align 4
4-
@lds.v2 = addrspace(3) global [512 x <2 x float>] undef, align 4
5-
@lds.v3 = addrspace(3) global [512 x <3 x float>] undef, align 4
6-
@lds.v4 = addrspace(3) global [512 x <4 x float>] undef, align 4
7-
@lds.v8 = addrspace(3) global [512 x <8 x float>] undef, align 4
8-
@lds.v16 = addrspace(3) global [512 x <16 x float>] undef, align 4
3+
@lds = addrspace(3) global [512 x float] poison, align 4
4+
@lds.v2 = addrspace(3) global [512 x <2 x float>] poison, align 4
5+
@lds.v3 = addrspace(3) global [512 x <3 x float>] poison, align 4
6+
@lds.v4 = addrspace(3) global [512 x <4 x float>] poison, align 4
7+
@lds.v8 = addrspace(3) global [512 x <8 x float>] poison, align 4
8+
@lds.v16 = addrspace(3) global [512 x <16 x float>] poison, align 4
99

1010
; CI-LABEL: {{^}}simple_read2_v2f32_superreg_align4:
1111
; CI: ds_read2_b32 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset1:1{{$}}

‎llvm/test/CodeGen/AMDGPU/ds_read2st64.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
; RUN: llc -mtriple=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s
22
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
33

4-
@lds = addrspace(3) global [512 x float] undef, align 4
5-
@lds.f64 = addrspace(3) global [512 x double] undef, align 8
4+
@lds = addrspace(3) global [512 x float] poison, align 4
5+
@lds.f64 = addrspace(3) global [512 x double] poison, align 8
66

77

88
; GCN-LABEL: @simple_read2st64_f32_0_1

‎llvm/test/CodeGen/AMDGPU/ds_write2.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -3,8 +3,8 @@
33
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs -mattr=+load-store-opt,-unaligned-access-mode < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-ALIGNED %s
44
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs -mattr=+load-store-opt,+unaligned-access-mode < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-UNALIGNED %s
55

6-
@lds = addrspace(3) global [512 x float] undef, align 4
7-
@lds.f64 = addrspace(3) global [512 x double] undef, align 8
6+
@lds = addrspace(3) global [512 x float] poison, align 4
7+
@lds.f64 = addrspace(3) global [512 x double] poison, align 8
88

99
define amdgpu_kernel void @simple_write2_one_val_f32(ptr addrspace(1) %C, ptr addrspace(1) %in) #0 {
1010
; CI-LABEL: simple_write2_one_val_f32:
@@ -764,7 +764,7 @@ define amdgpu_kernel void @simple_write2_two_val_f64(ptr addrspace(1) %C, ptr ad
764764
ret void
765765
}
766766

767-
@foo = addrspace(3) global [4 x i32] undef, align 4
767+
@foo = addrspace(3) global [4 x i32] poison, align 4
768768

769769
define amdgpu_kernel void @store_constant_adjacent_offsets() {
770770
; CI-LABEL: store_constant_adjacent_offsets:
@@ -808,7 +808,7 @@ define amdgpu_kernel void @store_constant_disjoint_offsets() {
808808
ret void
809809
}
810810

811-
@bar = addrspace(3) global [4 x i64] undef, align 4
811+
@bar = addrspace(3) global [4 x i64] poison, align 4
812812

813813
define amdgpu_kernel void @store_misaligned64_constant_offsets() {
814814
; CI-LABEL: store_misaligned64_constant_offsets:
@@ -834,7 +834,7 @@ define amdgpu_kernel void @store_misaligned64_constant_offsets() {
834834
ret void
835835
}
836836

837-
@bar.large = addrspace(3) global [4096 x i64] undef, align 4
837+
@bar.large = addrspace(3) global [4096 x i64] poison, align 4
838838

839839
define amdgpu_kernel void @store_misaligned64_constant_large_offsets() {
840840
; CI-LABEL: store_misaligned64_constant_large_offsets:
@@ -862,8 +862,8 @@ define amdgpu_kernel void @store_misaligned64_constant_large_offsets() {
862862
ret void
863863
}
864864

865-
@sgemm.lA = internal unnamed_addr addrspace(3) global [264 x float] undef, align 4
866-
@sgemm.lB = internal unnamed_addr addrspace(3) global [776 x float] undef, align 4
865+
@sgemm.lA = internal unnamed_addr addrspace(3) global [264 x float] poison, align 4
866+
@sgemm.lB = internal unnamed_addr addrspace(3) global [776 x float] poison, align 4
867867

868868
define amdgpu_kernel void @write2_sgemm_sequence(ptr addrspace(1) %C, i32 %lda, i32 %ldb, ptr addrspace(1) %in) #0 {
869869
; CI-LABEL: write2_sgemm_sequence:
@@ -1000,7 +1000,7 @@ define amdgpu_kernel void @simple_write2_v4f32_superreg_align4(ptr addrspace(3)
10001000
ret void
10011001
}
10021002

1003-
@v2i32_align1 = internal addrspace(3) global [100 x <2 x i32>] undef, align 1
1003+
@v2i32_align1 = internal addrspace(3) global [100 x <2 x i32>] poison, align 1
10041004

10051005
define amdgpu_kernel void @write2_v2i32_align1_odd_offset() {
10061006
; CI-LABEL: write2_v2i32_align1_odd_offset:

‎llvm/test/CodeGen/AMDGPU/ds_write2st64.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; RUN: llc -mtriple=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s
22
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
33

4-
@lds = addrspace(3) global [512 x float] undef, align 4
4+
@lds = addrspace(3) global [512 x float] poison, align 4
55

66
; GCN-LABEL: @simple_write2st64_one_val_f32_0_1
77
; CI-DAG: s_mov_b32 m0

0 commit comments

Comments
 (0)