Move isIGLPMutationOnly to SIInstrInfo

Change-Id: If3650ce24a1a047557b3e40363b72aefd909e873

Author: jrbyrnes

llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp

@@ -2698,13 +2698,6 @@ bool IGroupLPDAGMutation::initIGLPOpt(SUnit &SU) {
 
 namespace llvm {
 
-namespace AMDGPU {
-bool isIGLPMutationOnly(unsigned Opcode) {
-  return Opcode == AMDGPU::SCHED_GROUP_BARRIER || Opcode == AMDGPU::IGLP_OPT;
-}
-
-} // end namespace AMDGPU
-
 /// \p Phase specifes whether or not this is a reentry into the
 /// IGroupLPDAGMutation. Since there may be multiple scheduling passes on the
 /// same scheduling region (e.g. pre and post-RA scheduling / multiple

llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.h

@@ -19,10 +19,6 @@ namespace AMDGPU {
 // The current phase of instruction scheduling
 enum class SchedulingPhase { Initial, PreRAReentry, PostRA };
 
-// Return true if the instruction is mutually exclusive with all non-IGLP DAG
-// mutations, requiring all other mutations to be disabled.
-bool isIGLPMutationOnly(unsigned Opcode);
-
 } // namespace AMDGPU
 
 std::unique_ptr<ScheduleDAGMutation>

llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp

@@ -121,9 +121,9 @@ void GCNIterativeScheduler::printSchedRP(raw_ostream &OS,
 
 void GCNIterativeScheduler::swapIGLPMutations(const Region &R, bool IsReentry) {
   bool HasIGLPInstrs = false;
-
+  const SIInstrInfo *SII = static_cast<const SIInstrInfo *>(TII);
   for (MachineBasicBlock::iterator I = R.Begin; I != R.End; I++) {
-    if (AMDGPU::isIGLPMutationOnly(I->getOpcode())) {
+    if (SII->isIGLPMutationOnly(I->getOpcode())) {
       HasIGLPInstrs = true;
       break;
     }
@@ -134,6 +134,7 @@ void GCNIterativeScheduler::swapIGLPMutations(const Region &R, bool IsReentry) {
     SavedMutations.swap(Mutations);
     auto SchedPhase = IsReentry ? AMDGPU::SchedulingPhase::PreRAReentry
                                 : AMDGPU::SchedulingPhase::Initial;
+
     addMutation(createIGroupLPDAGMutation(SchedPhase));
   }
 }

llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp

@@ -1155,9 +1155,10 @@ bool GCNSchedStage::initGCNRegion() {
   Unsched.reserve(DAG.NumRegionInstrs);
   if (StageID == GCNSchedStageID::OccInitialSchedule ||
       StageID == GCNSchedStageID::ILPInitialSchedule) {
+    const SIInstrInfo *SII = static_cast<const SIInstrInfo *>(DAG.TII);
     for (auto &I : DAG) {
       Unsched.push_back(&I);
-      if (AMDGPU::isIGLPMutationOnly(I.getOpcode()))
+      if (SII->isIGLPMutationOnly(I.getOpcode()))
         DAG.RegionsWithIGLPInstrs[RegionIdx] = true;
     }
   } else {
@@ -2041,8 +2042,9 @@ void GCNScheduleDAGMILive::updateRegionBoundaries(
 }
 
 static bool hasIGLPInstrs(ScheduleDAGInstrs *DAG) {
-  return any_of(*DAG, [](MachineBasicBlock::iterator MI) {
-    return AMDGPU::isIGLPMutationOnly(MI->getOpcode());
+  const SIInstrInfo *SII = static_cast<const SIInstrInfo *>(DAG->TII);
+  return any_of(*DAG, [SII](MachineBasicBlock::iterator MI) {
+    return SII->isIGLPMutationOnly(MI->getOpcode());
   });
 }
 

llvm/lib/Target/AMDGPU/SIInstrInfo.h

@@ -985,6 +985,12 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
 
   bool isIGLP(const MachineInstr &MI) const { return isIGLP(MI.getOpcode()); }
 
+  // Return true if the instruction is mutually exclusive with all non-IGLP DAG
+  // mutations, requiring all other mutations to be disabled.
+  bool isIGLPMutationOnly(unsigned Opcode) const {
+    return Opcode == AMDGPU::SCHED_GROUP_BARRIER || Opcode == AMDGPU::IGLP_OPT;
+  }
+
   static unsigned getNonSoftWaitcntOpcode(unsigned Opcode) {
     switch (Opcode) {
     case AMDGPU::S_WAITCNT_soft: