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[AMDGPU] Remove amdgpu-no-heap-ptr and amdgpu-no-lds-kernel-id attributes from lowered kernels in amdgpu-sw-lower-lds pass (#120887)
'amdgpu-sw-lower-lds' pass internally calls '__asan_malloc_impl' for heap memory allocation. Pass also uses 'amdgcn_lds_kernel_id' for non-kernel lds accesses lowering. This patch removes 'amdgpu-no-heap-ptr' and 'amdgpu-no-lds-kernel-id' from all kernels lowered by the pass.
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3 files changed

+297
-4
lines changed

3 files changed

+297
-4
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUSwLowerLDS.cpp

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1176,10 +1176,13 @@ bool AMDGPUSwLowerLDS::run() {
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LDSParams.IndirectAccess.DynamicLDSGlobals.empty()) {
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Changed = false;
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} else {
1179-
removeFnAttrFromReachable(CG, Func,
1180-
{"amdgpu-no-workitem-id-x",
1181-
"amdgpu-no-workitem-id-y",
1182-
"amdgpu-no-workitem-id-z"});
1179+
removeFnAttrFromReachable(
1180+
CG, Func,
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{"amdgpu-no-workitem-id-x", "amdgpu-no-workitem-id-y",
1182+
"amdgpu-no-workitem-id-z", "amdgpu-no-heap-ptr"});
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if (!LDSParams.IndirectAccess.StaticLDSGlobals.empty() ||
1184+
!LDSParams.IndirectAccess.DynamicLDSGlobals.empty())
1185+
removeFnAttrFromReachable(CG, Func, {"amdgpu-no-lds-kernel-id"});
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reorderStaticDynamicIndirectLDSSet(LDSParams);
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buildSwLDSGlobal(Func);
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buildSwDynLDSGlobal(Func);

‎llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-no-kernel-lds-id.ll

Lines changed: 130 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,130 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals all --version 5
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; RUN: opt < %s -passes=amdgpu-sw-lower-lds -amdgpu-asan-instrument-lds=false -S -mtriple=amdgcn-amd-amdhsa | FileCheck %s
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; Test to check if static LDS is lowered correctly when a non-kernel with LDS accesses is called from kernel.
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; Also checks if amdgpu-no-lds-kernel-id attribute is removed from the list of attributes
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@lds_1 = internal addrspace(3) global [1 x i8] poison, align 1
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@lds_2 = internal addrspace(3) global [1 x i32] poison, align 2
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@lds_3 = external addrspace(3) global [3 x i8], align 4
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@lds_4 = external addrspace(3) global [4 x i8], align 8
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;.
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; CHECK: @llvm.amdgcn.sw.lds.k0 = internal addrspace(3) global ptr poison, no_sanitize_address, align 8, !absolute_symbol [[META0:![0-9]+]]
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; CHECK: @llvm.amdgcn.sw.lds.k0.md = internal addrspace(1) global %llvm.amdgcn.sw.lds.k0.md.type { %llvm.amdgcn.sw.lds.k0.md.item { i32 0, i32 8, i32 32 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 32, i32 1, i32 32 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 64, i32 4, i32 32 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 96, i32 3, i32 32 }, %llvm.amdgcn.sw.lds.k0.md.item { i32 128, i32 4, i32 32 } }, no_sanitize_address
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; @llvm.amdgcn.sw.lds.base.table = internal addrspace(1) constant [1 x ptr addrspace(3)] [ptr addrspace(3) @llvm.amdgcn.sw.lds.k0], no_sanitize_address
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; @llvm.amdgcn.sw.lds.offset.table = internal addrspace(1) constant [1 x [2 x ptr addrspace(1)]] [[2 x ptr addrspace(1)] [ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 0), ptr addrspace(1) getelementptr inbounds (%llvm.amdgcn.sw.lds.k0.md.type, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 4, i32 0)]], no_sanitize_address
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;.
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define void @use_variables() sanitize_address {
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; CHECK-LABEL: define void @use_variables(
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; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.lds.kernel.id()
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; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x ptr addrspace(3)], ptr addrspace(1) @llvm.amdgcn.sw.lds.base.table, i32 0, i32 [[TMP1]]
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; CHECK-NEXT: [[TMP3:%.*]] = load ptr addrspace(3), ptr addrspace(1) [[TMP2]], align 4
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; CHECK-NEXT: [[TMP4:%.*]] = load ptr addrspace(1), ptr addrspace(3) [[TMP3]], align 8
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; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x [2 x ptr addrspace(1)]], ptr addrspace(1) @llvm.amdgcn.sw.lds.offset.table, i32 0, i32 [[TMP1]], i32 0
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; CHECK-NEXT: [[TMP6:%.*]] = load ptr addrspace(1), ptr addrspace(1) [[TMP5]], align 8
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; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) [[TMP6]], align 4
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; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[TMP3]], i32 [[TMP7]]
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; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x [2 x ptr addrspace(1)]], ptr addrspace(1) @llvm.amdgcn.sw.lds.offset.table, i32 0, i32 [[TMP1]], i32 1
29+
; CHECK-NEXT: [[TMP10:%.*]] = load ptr addrspace(1), ptr addrspace(1) [[TMP9]], align 8
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; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(1) [[TMP10]], align 4
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; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i8, ptr addrspace(3) [[TMP3]], i32 [[TMP11]]
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; CHECK-NEXT: [[X:%.*]] = addrspacecast ptr addrspace(3) [[TMP8]] to ptr
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; CHECK-NEXT: [[TMP13:%.*]] = addrspacecast ptr addrspace(3) [[TMP8]] to ptr
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; CHECK-NEXT: store i8 3, ptr [[TMP13]], align 4
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; CHECK-NEXT: [[TMP14:%.*]] = ptrtoint ptr addrspace(3) [[TMP12]] to i32
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; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP4]], i32 [[TMP14]]
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; CHECK-NEXT: store i8 3, ptr addrspace(1) [[TMP15]], align 8
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; CHECK-NEXT: ret void
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;
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%X = addrspacecast ptr addrspace(3) @lds_3 to ptr
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store i8 3, ptr addrspacecast( ptr addrspace(3) @lds_3 to ptr), align 4
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store i8 3, ptr addrspace(3) @lds_4, align 8
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ret void
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}
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define amdgpu_kernel void @k0() sanitize_address #1 {
47+
; CHECK-LABEL: define amdgpu_kernel void @k0(
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; CHECK-SAME: ) #[[ATTR1:[0-9]+]] !llvm.amdgcn.lds.kernel.id [[META2:![0-9]+]] {
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; CHECK-NEXT: [[WID:.*]]:
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; CHECK-NEXT: [[TMP0:%.*]] = call i32 @llvm.amdgcn.workitem.id.x()
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; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.amdgcn.workitem.id.y()
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; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.amdgcn.workitem.id.z()
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; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP0]], [[TMP1]]
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; CHECK-NEXT: [[TMP4:%.*]] = or i32 [[TMP3]], [[TMP2]]
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; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
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; CHECK-NEXT: br i1 [[TMP5]], label %[[MALLOC:.*]], label %[[BB24:.*]]
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; CHECK: [[MALLOC]]:
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; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 4, i32 0), align 4
59+
; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 4, i32 2), align 4
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; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP6]], [[TMP7]]
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; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
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; CHECK-NEXT: [[TMP10:%.*]] = call ptr @llvm.returnaddress(i32 0)
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; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[TMP10]] to i64
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; CHECK-NEXT: [[TMP12:%.*]] = call i64 @__asan_malloc_impl(i64 [[TMP9]], i64 [[TMP11]])
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; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr addrspace(1)
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; CHECK-NEXT: store ptr addrspace(1) [[TMP13]], ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
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; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP13]], i64 8
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; CHECK-NEXT: [[TMP15:%.*]] = ptrtoint ptr addrspace(1) [[TMP14]] to i64
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; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP15]], i64 24)
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; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP13]], i64 33
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; CHECK-NEXT: [[TMP17:%.*]] = ptrtoint ptr addrspace(1) [[TMP16]] to i64
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; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP17]], i64 31)
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; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP13]], i64 68
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; CHECK-NEXT: [[TMP19:%.*]] = ptrtoint ptr addrspace(1) [[TMP18]] to i64
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; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP19]], i64 28)
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; CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP13]], i64 99
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; CHECK-NEXT: [[TMP21:%.*]] = ptrtoint ptr addrspace(1) [[TMP20]] to i64
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; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP21]], i64 29)
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; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP13]], i64 132
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; CHECK-NEXT: [[TMP23:%.*]] = ptrtoint ptr addrspace(1) [[TMP22]] to i64
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; CHECK-NEXT: call void @__asan_poison_region(i64 [[TMP23]], i64 28)
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; CHECK-NEXT: br label %[[BB24]]
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; CHECK: [[BB24]]:
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; CHECK-NEXT: [[XYZCOND:%.*]] = phi i1 [ false, %[[WID]] ], [ true, %[[MALLOC]] ]
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; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()
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; CHECK-NEXT: [[TMP25:%.*]] = load ptr addrspace(1), ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, align 8
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; CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 4
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; CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds i8, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 [[TMP26]]
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; CHECK-NEXT: [[TMP28:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 0), align 4
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; CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds i8, ptr addrspace(3) @llvm.amdgcn.sw.lds.k0, i32 [[TMP28]]
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; CHECK-NEXT: call void @use_variables()
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; CHECK-NEXT: [[TMP30:%.*]] = ptrtoint ptr addrspace(3) [[TMP27]] to i32
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; CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP25]], i32 [[TMP30]]
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; CHECK-NEXT: store i8 7, ptr addrspace(1) [[TMP31]], align 1
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; CHECK-NEXT: [[TMP32:%.*]] = ptrtoint ptr addrspace(3) [[TMP29]] to i32
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; CHECK-NEXT: [[TMP33:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[TMP25]], i32 [[TMP32]]
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; CHECK-NEXT: store i32 8, ptr addrspace(1) [[TMP33]], align 2
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; CHECK-NEXT: br label %[[CONDFREE:.*]]
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; CHECK: [[CONDFREE]]:
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; CHECK-NEXT: call void @llvm.amdgcn.s.barrier()
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; CHECK-NEXT: br i1 [[XYZCOND]], label %[[FREE:.*]], label %[[END:.*]]
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; CHECK: [[FREE]]:
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; CHECK-NEXT: [[TMP34:%.*]] = call ptr @llvm.returnaddress(i32 0)
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; CHECK-NEXT: [[TMP35:%.*]] = ptrtoint ptr [[TMP34]] to i64
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; CHECK-NEXT: [[TMP36:%.*]] = ptrtoint ptr addrspace(1) [[TMP25]] to i64
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; CHECK-NEXT: call void @__asan_free_impl(i64 [[TMP36]], i64 [[TMP35]])
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; CHECK-NEXT: br label %[[END]]
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; CHECK: [[END]]:
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; CHECK-NEXT: ret void
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;
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call void @use_variables()
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store i8 7, ptr addrspace(3) @lds_1, align 1
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store i32 8, ptr addrspace(3) @lds_2, align 2
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ret void
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}
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!llvm.module.flags = !{!0}
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!0 = !{i32 4, !"nosanitize_address", i32 1}
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attributes #1 = { "amdgpu-no-lds-kernel-id" }
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;.
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; CHECK: attributes #[[ATTR0]] = { sanitize_address }
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; CHECK: attributes #[[ATTR1]] = { sanitize_address "amdgpu-lds-size"="8" }
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; CHECK: attributes #[[ATTR2:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
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; CHECK: attributes #[[ATTR3:[0-9]+]] = { nocallback nofree nosync nounwind willreturn memory(none) }
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; CHECK: attributes #[[ATTR4:[0-9]+]] = { convergent nocallback nofree nounwind willreturn }
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;.
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; CHECK: [[META0]] = !{i32 0, i32 1}
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; CHECK: [[META1:![0-9]+]] = !{i32 4, !"nosanitize_address", i32 1}
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; CHECK: [[META2]] = !{i32 0}
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;.

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