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AMDGPU: Replace ptr addrspace(8) undef uses with poison
1 parent aeb2f61 commit 1fe990c

16 files changed

+83
-83
lines changed

‎llvm/test/CodeGen/AMDGPU/amdpal.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -72,7 +72,7 @@ entry:
7272
%e = getelementptr [2 x i32], ptr addrspace(5) %v1, i32 0, i32 %idx
7373
%x = load i32, ptr addrspace(5) %e
7474
%xf = bitcast i32 %x to float
75-
call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float %xf, ptr addrspace(8) undef, i32 0, i32 0, i32 0)
75+
call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float %xf, ptr addrspace(8) poison, i32 0, i32 0, i32 0)
7676
ret void
7777
}
7878

‎llvm/test/CodeGen/AMDGPU/combine-add-zext-xor.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -66,7 +66,7 @@ define i32 @combine_add_zext_xor() {
6666
br i1 undef, label %bb9, label %bb
6767

6868
bb: ; preds = %.a
69-
%.i3 = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) undef, i32 %.2, i32 64, i32 1)
69+
%.i3 = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) poison, i32 %.2, i32 64, i32 1)
7070
%i5 = icmp eq i32 %.i3, 0
7171
br label %bb9
7272

@@ -146,7 +146,7 @@ define i32 @combine_sub_zext_xor() {
146146
br i1 undef, label %bb9, label %bb
147147

148148
bb: ; preds = %.a
149-
%.i3 = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) undef, i32 %.2, i32 64, i32 1)
149+
%.i3 = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) poison, i32 %.2, i32 64, i32 1)
150150
%i5 = icmp eq i32 %.i3, 0
151151
br label %bb9
152152

@@ -229,7 +229,7 @@ define i32 @combine_add_zext_or() {
229229
br i1 undef, label %bb9, label %bb
230230

231231
bb: ; preds = %.a
232-
%.i3 = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) undef, i32 %.2, i32 64, i32 1)
232+
%.i3 = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) poison, i32 %.2, i32 64, i32 1)
233233
%i5 = icmp eq i32 %.i3, 0
234234
br label %bb9
235235

@@ -313,7 +313,7 @@ define i32 @combine_sub_zext_or() {
313313
br i1 undef, label %bb9, label %bb
314314

315315
bb: ; preds = %.a
316-
%.i3 = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) undef, i32 %.2, i32 64, i32 1)
316+
%.i3 = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) poison, i32 %.2, i32 64, i32 1)
317317
%i5 = icmp eq i32 %.i3, 0
318318
br label %bb9
319319

@@ -392,7 +392,7 @@ define i32 @combine_add_zext_and() {
392392
br i1 undef, label %bb9, label %bb
393393

394394
bb: ; preds = %.a
395-
%.i3 = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) undef, i32 %.2, i32 64, i32 1)
395+
%.i3 = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) poison, i32 %.2, i32 64, i32 1)
396396
%i5 = icmp eq i32 %.i3, 0
397397
br label %bb9
398398

@@ -471,7 +471,7 @@ define i32 @combine_sub_zext_and() {
471471
br i1 undef, label %bb9, label %bb
472472

473473
bb: ; preds = %.a
474-
%.i3 = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) undef, i32 %.2, i32 64, i32 1)
474+
%.i3 = call i32 @llvm.amdgcn.raw.ptr.buffer.load.i32(ptr addrspace(8) poison, i32 %.2, i32 64, i32 1)
475475
%i5 = icmp eq i32 %.i3, 0
476476
br label %bb9
477477

‎llvm/test/CodeGen/AMDGPU/else.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -47,7 +47,7 @@ else:
4747

4848
end:
4949
%r = phi float [ %v.if, %if ], [ %v.else, %else ]
50-
call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float %r, ptr addrspace(8) undef, i32 0, i32 0, i32 0)
50+
call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float %r, ptr addrspace(8) poison, i32 0, i32 0, i32 0)
5151
ret void
5252
}
5353

‎llvm/test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ define amdgpu_hs void @main(ptr addrspace(6) inreg %arg) {
1313
; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
1414
; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
1515
; GCN-NEXT: [[DEF1:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
16-
; GCN-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY]], [[DEF1]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable load (s128) from `ptr addrspace(8) undef`, align 1, addrspace 8)
16+
; GCN-NEXT: [[BUFFER_LOAD_DWORDX4_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_OFFEN [[COPY]], [[DEF1]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable load (s128) from `ptr addrspace(8) poison`, align 1, addrspace 8)
1717
; GCN-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub2
1818
; GCN-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub1
1919
; GCN-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_OFFEN]].sub0
@@ -22,14 +22,14 @@ define amdgpu_hs void @main(ptr addrspace(6) inreg %arg) {
2222
; GCN-NEXT: [[DEF2:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
2323
; GCN-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[DEF2]]
2424
; GCN-NEXT: [[DEF3:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
25-
; GCN-NEXT: BUFFER_STORE_DWORDX3_OFFEN_exact killed [[COPY4]], [[COPY5]], [[DEF3]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable store (s96) into `ptr addrspace(8) undef`, align 1, addrspace 8)
25+
; GCN-NEXT: BUFFER_STORE_DWORDX3_OFFEN_exact killed [[COPY4]], [[COPY5]], [[DEF3]], [[S_MOV_B32_]], 0, 0, 0, implicit $exec :: (dereferenceable store (s96) into `ptr addrspace(8) poison`, align 1, addrspace 8)
2626
; GCN-NEXT: S_ENDPGM 0
2727
main_body:
28-
%tmp25 = call <4 x float> @llvm.amdgcn.raw.ptr.buffer.load.v4f32(ptr addrspace(8) undef, i32 undef, i32 0, i32 0)
28+
%tmp25 = call <4 x float> @llvm.amdgcn.raw.ptr.buffer.load.v4f32(ptr addrspace(8) poison, i32 undef, i32 0, i32 0)
2929
%tmp27 = bitcast <4 x float> %tmp25 to <16 x i8>
3030
%tmp28 = shufflevector <16 x i8> %tmp27, <16 x i8> poison, <12 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>
3131
%tmp29 = bitcast <12 x i8> %tmp28 to <3 x i32>
32-
call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> %tmp29, ptr addrspace(8) undef, i32 undef, i32 0, i32 0) #3
32+
call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> %tmp29, ptr addrspace(8) poison, i32 undef, i32 0, i32 0) #3
3333
ret void
3434
}
3535

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -623,7 +623,7 @@ define amdgpu_kernel void @test_export_pos_before_param_ordered(float %x, float
623623
define amdgpu_kernel void @test_export_pos_before_param_across_load(i32 %idx) #0 {
624624
call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float 1.0, float 1.0, float 1.0, float 1.0, i1 false, i1 false)
625625
call void @llvm.amdgcn.exp.f32(i32 33, i32 15, float 1.0, float 1.0, float 1.0, float 0.5, i1 false, i1 false)
626-
%load = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) undef, i32 %idx, i32 0, i32 0)
626+
%load = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) poison, i32 %idx, i32 0, i32 0)
627627
call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float 0.0, float 0.0, float 0.0, float %load, i1 true, i1 false)
628628
ret void
629629
}

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.atomic.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -103,7 +103,7 @@ main_body:
103103
;CHECK: buffer_atomic_add v0,
104104
define amdgpu_ps float @test4() {
105105
main_body:
106-
%v = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.add.i32(i32 1, ptr addrspace(8) undef, i32 4, i32 0, i32 0)
106+
%v = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.add.i32(i32 1, ptr addrspace(8) poison, i32 4, i32 0, i32 0)
107107
%v.float = bitcast i32 %v to float
108108
ret float %v.float
109109
}

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.atomic.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -115,7 +115,7 @@ main_body:
115115
;CHECK: buffer_atomic_add v0,
116116
define amdgpu_ps float @test4() {
117117
main_body:
118-
%v = call i32 @llvm.amdgcn.struct.ptr.buffer.atomic.add.i32(i32 1, ptr addrspace(8) undef, i32 0, i32 4, i32 0, i32 0)
118+
%v = call i32 @llvm.amdgcn.struct.ptr.buffer.atomic.add.i32(i32 1, ptr addrspace(8) poison, i32 0, i32 4, i32 0, i32 0)
119119
%v.float = bitcast i32 %v to float
120120
ret float %v.float
121121
}

‎llvm/test/CodeGen/AMDGPU/loop_exit_with_xor.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -46,7 +46,7 @@ loop:
4646
br i1 %tmp27, label %then, label %endif
4747

4848
then: ; preds = %bb
49-
call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float undef, ptr addrspace(8) undef, i32 0, i32 undef, i32 0)
49+
call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float undef, ptr addrspace(8) poison, i32 0, i32 undef, i32 0)
5050
br label %endif
5151

5252
endif: ; preds = %bb28, %bb
@@ -85,7 +85,7 @@ loop:
8585
%tmp23phi = phi i32 [ %tmp23, %loop ], [ 0, %entry ]
8686
%tmp23 = add nuw i32 %tmp23phi, 1
8787
%tmp27 = icmp ult i32 %arg, %tmp23
88-
call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float undef, ptr addrspace(8) undef, i32 0, i32 undef, i32 0)
88+
call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float undef, ptr addrspace(8) poison, i32 0, i32 undef, i32 0)
8989
br i1 %tmp27, label %loop, label %loopexit
9090

9191
loopexit:
@@ -136,7 +136,7 @@ loop:
136136
br i1 %tmp27, label %then, label %endif
137137

138138
then: ; preds = %bb
139-
call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float undef, ptr addrspace(8) undef, i32 0, i32 undef, i32 0)
139+
call void @llvm.amdgcn.raw.ptr.buffer.store.f32(float undef, ptr addrspace(8) poison, i32 0, i32 undef, i32 0)
140140
br label %endif
141141

142142
endif: ; preds = %bb28, %bb

‎llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@ define amdgpu_kernel void @workgroup_ids_kernel() {
6161
%ielemx = insertelement <3 x i32> poison, i32 %idx, i64 0
6262
%ielemy = insertelement <3 x i32> %ielemx, i32 %idy, i64 1
6363
%ielemz = insertelement <3 x i32> %ielemy, i32 %idz, i64 2
64-
call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> %ielemz, ptr addrspace(8) undef, i32 0, i32 0, i32 0)
64+
call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> %ielemz, ptr addrspace(8) poison, i32 0, i32 0, i32 0)
6565
ret void
6666
}
6767

‎llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -68,7 +68,7 @@ define amdgpu_cs void @_amdgpu_cs_main() {
6868
%ielemx = insertelement <3 x i32> poison, i32 %idx, i64 0
6969
%ielemy = insertelement <3 x i32> %ielemx, i32 %idy, i64 1
7070
%ielemz = insertelement <3 x i32> %ielemy, i32 %idz, i64 2
71-
call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> %ielemz, ptr addrspace(8) undef, i32 0, i32 0, i32 0)
71+
call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> %ielemz, ptr addrspace(8) poison, i32 0, i32 0, i32 0)
7272
ret void
7373
}
7474

‎llvm/test/CodeGen/AMDGPU/merge-store-crash.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@ main_body:
2626
%tmp9 = insertelement <4 x i32> %tmp8, i32 %tmp7, i32 1
2727
%tmp10 = insertelement <4 x i32> %tmp9, i32 poison, i32 2
2828
%tmp11 = insertelement <4 x i32> %tmp10, i32 poison, i32 3
29-
call void @llvm.amdgcn.struct.ptr.tbuffer.store.v4i32(<4 x i32> %tmp11, ptr addrspace(8) undef, i32 0, i32 0, i32 %arg, i32 78, i32 3) #2
29+
call void @llvm.amdgcn.struct.ptr.tbuffer.store.v4i32(<4 x i32> %tmp11, ptr addrspace(8) poison, i32 0, i32 0, i32 %arg, i32 78, i32 3) #2
3030
ret void
3131
}
3232

‎llvm/test/CodeGen/AMDGPU/merge-store-usedef.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ define amdgpu_vs void @test1(i32 %v) #0 {
1010

1111
store i32 %v, ptr addrspace(3) null
1212

13-
call void @llvm.amdgcn.raw.ptr.tbuffer.store.i32(i32 %v, ptr addrspace(8) undef, i32 0, i32 0, i32 68, i32 1)
13+
call void @llvm.amdgcn.raw.ptr.tbuffer.store.i32(i32 %v, ptr addrspace(8) poison, i32 0, i32 0, i32 68, i32 1)
1414

1515
%w = load i32, ptr addrspace(3) null
1616
store i32 %w, ptr addrspace(3) %p1

‎llvm/test/CodeGen/AMDGPU/required-export-priority.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -254,7 +254,7 @@ define amdgpu_ps void @test_export_pos_before_param_across_load(i32 %idx) #0 {
254254
; GCN-NEXT: s_endpgm
255255
call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float 1.0, float 1.0, float 1.0, float 1.0, i1 false, i1 false)
256256
call void @llvm.amdgcn.exp.f32(i32 33, i32 15, float 1.0, float 1.0, float 1.0, float 0.5, i1 false, i1 false)
257-
%load = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) undef, i32 %idx, i32 0, i32 0)
257+
%load = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) poison, i32 %idx, i32 0, i32 0)
258258
call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float 0.0, float 0.0, float 0.0, float %load, i1 true, i1 false)
259259
ret void
260260
}

‎llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -318,7 +318,7 @@ define amdgpu_vs void @reorder_local_load_tbuffer_store_local_load(ptr addrspace
318318

319319
%vdata = insertelement <4 x i32> poison, i32 %a1, i32 0
320320
%vaddr.add = add i32 %vaddr, 32
321-
call void @llvm.amdgcn.struct.ptr.tbuffer.store.v4i32(<4 x i32> %vdata, ptr addrspace(8) undef, i32 %vaddr.add, i32 0, i32 0, i32 228, i32 3)
321+
call void @llvm.amdgcn.struct.ptr.tbuffer.store.v4i32(<4 x i32> %vdata, ptr addrspace(8) poison, i32 %vaddr.add, i32 0, i32 0, i32 228, i32 3)
322322

323323
%tmp2 = load i32, ptr addrspace(3) %ptr2, align 4
324324

‎llvm/test/CodeGen/AMDGPU/wave32.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1959,7 +1959,7 @@ main_body:
19591959
br i1 %cc, label %endif, label %if
19601960

19611961
if:
1962-
%src = call float @llvm.amdgcn.struct.ptr.buffer.load.f32(ptr addrspace(8) undef, i32 %idx, i32 0, i32 0, i32 0)
1962+
%src = call float @llvm.amdgcn.struct.ptr.buffer.load.f32(ptr addrspace(8) poison, i32 %idx, i32 0, i32 0, i32 0)
19631963
%out = fadd float %src, %src
19641964
%out.0 = call float @llvm.amdgcn.wwm.f32(float %out)
19651965
%out.1 = fadd float %src, %out.0
@@ -2046,7 +2046,7 @@ main_body:
20462046
br i1 %cc, label %endif, label %if
20472047

20482048
if:
2049-
%src = call float @llvm.amdgcn.struct.ptr.buffer.load.f32(ptr addrspace(8) undef, i32 %idx, i32 0, i32 0, i32 0)
2049+
%src = call float @llvm.amdgcn.struct.ptr.buffer.load.f32(ptr addrspace(8) poison, i32 %idx, i32 0, i32 0, i32 0)
20502050
%out = fadd float %src, %src
20512051
%out.0 = call float @llvm.amdgcn.strict.wwm.f32(float %out)
20522052
%out.1 = fadd float %src, %out.0
@@ -2128,8 +2128,8 @@ define amdgpu_ps float @test_wqm2(i32 inreg %idx0, i32 inreg %idx1) #0 {
21282128
; GFX1064-NEXT: s_and_b64 exec, exec, s[2:3]
21292129
; GFX1064-NEXT: ; return to shader part epilog
21302130
main_body:
2131-
%src0 = call float @llvm.amdgcn.struct.ptr.buffer.load.f32(ptr addrspace(8) undef, i32 %idx0, i32 0, i32 0, i32 0)
2132-
%src1 = call float @llvm.amdgcn.struct.ptr.buffer.load.f32(ptr addrspace(8) undef, i32 %idx1, i32 0, i32 0, i32 0)
2131+
%src0 = call float @llvm.amdgcn.struct.ptr.buffer.load.f32(ptr addrspace(8) poison, i32 %idx0, i32 0, i32 0, i32 0)
2132+
%src1 = call float @llvm.amdgcn.struct.ptr.buffer.load.f32(ptr addrspace(8) poison, i32 %idx1, i32 0, i32 0, i32 0)
21332133
%out = fadd float %src0, %src1
21342134
%out.0 = bitcast float %out to i32
21352135
%out.1 = call i32 @llvm.amdgcn.wqm.i32(i32 %out.0)

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