[PowerPC] add a peephole to remove redundant swap instructions after vector splats on P8

Vector store on P8 little endian will have swap instruction added before
the store in PPCISelLowring. If the vector is generated by splat, the
swap instruction can be eliminated.

Reviewed By: shchenz

Differential Revision: https://reviews.llvm.org/D139691

Author: Ting Wang

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

@@ -641,6 +641,18 @@ bool PPCMIPeephole::simplifyCode() {
           DefMI->getOperand(0).setReg(MI.getOperand(0).getReg());
           LLVM_DEBUG(dbgs() << "Removing redundant splat: ");
           LLVM_DEBUG(MI.dump());
+        } else if (Immed == 2 &&
+                   (DefOpc == PPC::VSPLTB || DefOpc == PPC::VSPLTH ||
+                    DefOpc == PPC::VSPLTW || DefOpc == PPC::XXSPLTW)) {
+          // Swap of various vector splats, convert to copy.
+          ToErase = &MI;
+          Simplified = true;
+          LLVM_DEBUG(dbgs() << "Optimizing swap(vsplt[b|h|w]|xxspltw) => "
+                               "copy(vsplt[b|h|w]|xxspltw): ");
+          LLVM_DEBUG(MI.dump());
+          BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(PPC::COPY),
+                  MI.getOperand(0).getReg())
+              .add(MI.getOperand(1));
         }
         break;
       }

llvm/test/CodeGen/PowerPC/VSX-XForm-Scalars.ll

@@ -14,7 +14,6 @@ define void @testExpandPostRAPseudo(ptr nocapture readonly %ptr) {
 ; CHECK-P8:    lfiwzx f0, 0, r3
 ; CHECK-P8:    ld r4, .LC0@toc@l(r4)
 ; CHECK-P8:    xxspltw vs0, vs0, 1
-; CHECK-P8:    xxswapd vs0, vs0
 ; CHECK-P8;    stxvd2x vs0, 0, r4
 ; CHECK-P8:    lis r4, 1024
 ; CHECK-P8:    lfiwax f0, 0, r3

llvm/test/CodeGen/PowerPC/aix-vsx-splatimm.ll

@@ -47,13 +47,11 @@ define void @test_aix_splatimm(i32 %arg, i32 %arg1, i32 %arg2) {
 ; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    mullw 4, 4, 5
 ; CHECK-NEXT:    vsplth 2, 2, 3
-; CHECK-NEXT:    xxswapd 0, 34
+; CHECK-NEXT:    stxvd2x 34, 0, 3
 ; CHECK-NEXT:    neg 4, 4
 ; CHECK-NEXT:    mtvsrd 35, 4
-; CHECK-NEXT:    stxvd2x 0, 0, 3
 ; CHECK-NEXT:    vsplth 3, 3, 3
-; CHECK-NEXT:    xxswapd 1, 35
-; CHECK-NEXT:    stxvd2x 1, 0, 3
+; CHECK-NEXT:    stxvd2x 35, 0, 3
 bb:
   br i1 undef, label %bb22, label %bb3
 

llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll

@@ -1196,8 +1196,7 @@ define dso_local void @testByteSplat() #0 {
 ; CHECK-P7-NEXT:    lvx v3, 0, r3
 ; CHECK-P7-NEXT:    vperm v2, v3, v3, v2
 ; CHECK-P7-NEXT:    vspltb v2, v2, 15
-; CHECK-P7-NEXT:    xxswapd vs0, v2
-; CHECK-P7-NEXT:    stxvd2x vs0, 0, r3
+; CHECK-P7-NEXT:    stxvd2x v2, 0, r3
 ; CHECK-P7-NEXT:    blr
 ;
 ; P8-AIX-LABEL: testByteSplat:

llvm/test/CodeGen/PowerPC/load-and-splat.ll

@@ -84,7 +84,6 @@ define dso_local void @test2(ptr nocapture %c, ptr nocapture readonly %a) local_
 ; P8-NEXT:    addi r4, r4, 12
 ; P8-NEXT:    lfiwzx f0, 0, r4
 ; P8-NEXT:    xxspltw vs0, vs0, 1
-; P8-NEXT:    xxswapd vs0, vs0
 ; P8-NEXT:    stxvd2x vs0, 0, r3
 ; P8-NEXT:    blr
 ;
@@ -141,7 +140,6 @@ define dso_local void @test3(ptr nocapture %c, ptr nocapture readonly %a) local_
 ; P8-NEXT:    addi r4, r4, 12
 ; P8-NEXT:    lfiwzx f0, 0, r4
 ; P8-NEXT:    xxspltw vs0, vs0, 1
-; P8-NEXT:    xxswapd vs0, vs0
 ; P8-NEXT:    stxvd2x vs0, 0, r3
 ; P8-NEXT:    blr
 ;