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arsenmarsenm
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AMDGPU: Don't bitcast float typed atomic store in IR
Implement the promotion in the DAG.
1 parent cc73448 commit 1b66317

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6 files changed

+91
-41
lines changed

6 files changed

+91
-41
lines changed

‎llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Lines changed: 20 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -4946,7 +4946,8 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
49464946
Node->getOpcode() == ISD::INSERT_VECTOR_ELT) {
49474947
OVT = Node->getOperand(0).getSimpleValueType();
49484948
}
4949-
if (Node->getOpcode() == ISD::STRICT_UINT_TO_FP ||
4949+
if (Node->getOpcode() == ISD::ATOMIC_STORE ||
4950+
Node->getOpcode() == ISD::STRICT_UINT_TO_FP ||
49504951
Node->getOpcode() == ISD::STRICT_SINT_TO_FP ||
49514952
Node->getOpcode() == ISD::STRICT_FSETCC ||
49524953
Node->getOpcode() == ISD::STRICT_FSETCCS)
@@ -5557,7 +5558,8 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
55575558
Results.push_back(CvtVec);
55585559
break;
55595560
}
5560-
case ISD::ATOMIC_SWAP: {
5561+
case ISD::ATOMIC_SWAP:
5562+
case ISD::ATOMIC_STORE: {
55615563
AtomicSDNode *AM = cast<AtomicSDNode>(Node);
55625564
SDLoc SL(Node);
55635565
SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, NVT, AM->getVal());
@@ -5566,13 +5568,22 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
55665568
assert(AM->getMemoryVT().getSizeInBits() == NVT.getSizeInBits() &&
55675569
"unexpected atomic_swap with illegal type");
55685570

5569-
SDValue NewAtomic
5570-
= DAG.getAtomic(ISD::ATOMIC_SWAP, SL, NVT,
5571-
DAG.getVTList(NVT, MVT::Other),
5572-
{ AM->getChain(), AM->getBasePtr(), CastVal },
5573-
AM->getMemOperand());
5574-
Results.push_back(DAG.getNode(ISD::BITCAST, SL, OVT, NewAtomic));
5575-
Results.push_back(NewAtomic.getValue(1));
5571+
SDValue Op0 = AM->getBasePtr();
5572+
SDValue Op1 = CastVal;
5573+
5574+
// ATOMIC_STORE uses a swapped operand order from every other AtomicSDNode,
5575+
// but really it should merge with ISD::STORE.
5576+
if (AM->getOpcode() == ISD::ATOMIC_STORE)
5577+
std::swap(Op0, Op1);
5578+
5579+
SDValue NewAtomic = DAG.getAtomic(AM->getOpcode(), SL, NVT, AM->getChain(),
5580+
Op0, Op1, AM->getMemOperand());
5581+
5582+
if (AM->getOpcode() != ISD::ATOMIC_STORE) {
5583+
Results.push_back(DAG.getNode(ISD::BITCAST, SL, OVT, NewAtomic));
5584+
Results.push_back(NewAtomic.getValue(1));
5585+
} else
5586+
Results.push_back(NewAtomic);
55765587
break;
55775588
}
55785589
case ISD::ATOMIC_LOAD: {

‎llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2249,6 +2249,7 @@ bool DAGTypeLegalizer::PromoteFloatOperand(SDNode *N, unsigned OpNo) {
22492249
case ISD::SELECT_CC: R = PromoteFloatOp_SELECT_CC(N, OpNo); break;
22502250
case ISD::SETCC: R = PromoteFloatOp_SETCC(N, OpNo); break;
22512251
case ISD::STORE: R = PromoteFloatOp_STORE(N, OpNo); break;
2252+
case ISD::ATOMIC_STORE: R = PromoteFloatOp_ATOMIC_STORE(N, OpNo); break;
22522253
}
22532254
// clang-format on
22542255

@@ -2371,6 +2372,23 @@ SDValue DAGTypeLegalizer::PromoteFloatOp_STORE(SDNode *N, unsigned OpNo) {
23712372
ST->getMemOperand());
23722373
}
23732374

2375+
SDValue DAGTypeLegalizer::PromoteFloatOp_ATOMIC_STORE(SDNode *N,
2376+
unsigned OpNo) {
2377+
AtomicSDNode *ST = cast<AtomicSDNode>(N);
2378+
SDValue Val = ST->getVal();
2379+
SDLoc DL(N);
2380+
2381+
SDValue Promoted = GetPromotedFloat(Val);
2382+
EVT VT = ST->getOperand(1).getValueType();
2383+
EVT IVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
2384+
2385+
SDValue NewVal = DAG.getNode(GetPromotionOpcode(Promoted.getValueType(), VT),
2386+
DL, IVT, Promoted);
2387+
2388+
return DAG.getAtomic(ISD::ATOMIC_STORE, DL, IVT, ST->getChain(), NewVal,
2389+
ST->getBasePtr(), ST->getMemOperand());
2390+
}
2391+
23742392
//===----------------------------------------------------------------------===//
23752393
// Float Result Promotion
23762394
//===----------------------------------------------------------------------===//
@@ -3193,6 +3211,9 @@ bool DAGTypeLegalizer::SoftPromoteHalfOperand(SDNode *N, unsigned OpNo) {
31933211
case ISD::SELECT_CC: Res = SoftPromoteHalfOp_SELECT_CC(N, OpNo); break;
31943212
case ISD::SETCC: Res = SoftPromoteHalfOp_SETCC(N); break;
31953213
case ISD::STORE: Res = SoftPromoteHalfOp_STORE(N, OpNo); break;
3214+
case ISD::ATOMIC_STORE:
3215+
Res = SoftPromoteHalfOp_ATOMIC_STORE(N, OpNo);
3216+
break;
31963217
case ISD::STACKMAP:
31973218
Res = SoftPromoteHalfOp_STACKMAP(N, OpNo);
31983219
break;
@@ -3346,6 +3367,19 @@ SDValue DAGTypeLegalizer::SoftPromoteHalfOp_STORE(SDNode *N, unsigned OpNo) {
33463367
ST->getMemOperand());
33473368
}
33483369

3370+
SDValue DAGTypeLegalizer::SoftPromoteHalfOp_ATOMIC_STORE(SDNode *N,
3371+
unsigned OpNo) {
3372+
assert(OpNo == 1 && "Can only soften the stored value!");
3373+
AtomicSDNode *ST = cast<AtomicSDNode>(N);
3374+
SDValue Val = ST->getVal();
3375+
SDLoc dl(N);
3376+
3377+
SDValue Promoted = GetSoftPromotedHalf(Val);
3378+
return DAG.getAtomic(ISD::ATOMIC_STORE, dl, Promoted.getValueType(),
3379+
ST->getChain(), Promoted, ST->getBasePtr(),
3380+
ST->getMemOperand());
3381+
}
3382+
33493383
SDValue DAGTypeLegalizer::SoftPromoteHalfOp_STACKMAP(SDNode *N, unsigned OpNo) {
33503384
assert(OpNo > 1); // Because the first two arguments are guaranteed legal.
33513385
SmallVector<SDValue> NewOps(N->ops().begin(), N->ops().end());

‎llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -709,6 +709,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
709709
SDValue PromoteFloatOp_UnaryOp(SDNode *N, unsigned OpNo);
710710
SDValue PromoteFloatOp_FP_TO_XINT_SAT(SDNode *N, unsigned OpNo);
711711
SDValue PromoteFloatOp_STORE(SDNode *N, unsigned OpNo);
712+
SDValue PromoteFloatOp_ATOMIC_STORE(SDNode *N, unsigned OpNo);
712713
SDValue PromoteFloatOp_SELECT_CC(SDNode *N, unsigned OpNo);
713714
SDValue PromoteFloatOp_SETCC(SDNode *N, unsigned OpNo);
714715

@@ -753,6 +754,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
753754
SDValue SoftPromoteHalfOp_SETCC(SDNode *N);
754755
SDValue SoftPromoteHalfOp_SELECT_CC(SDNode *N, unsigned OpNo);
755756
SDValue SoftPromoteHalfOp_STORE(SDNode *N, unsigned OpNo);
757+
SDValue SoftPromoteHalfOp_ATOMIC_STORE(SDNode *N, unsigned OpNo);
756758
SDValue SoftPromoteHalfOp_STACKMAP(SDNode *N, unsigned OpNo);
757759
SDValue SoftPromoteHalfOp_PATCHPOINT(SDNode *N, unsigned OpNo);
758760

‎llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -161,6 +161,18 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
161161
setOperationAction(ISD::ATOMIC_LOAD, MVT::bf16, Promote);
162162
AddPromotedToType(ISD::ATOMIC_LOAD, MVT::bf16, MVT::i16);
163163

164+
setOperationAction(ISD::ATOMIC_STORE, MVT::f32, Promote);
165+
AddPromotedToType(ISD::ATOMIC_STORE, MVT::f32, MVT::i32);
166+
167+
setOperationAction(ISD::ATOMIC_STORE, MVT::f64, Promote);
168+
AddPromotedToType(ISD::ATOMIC_STORE, MVT::f64, MVT::i64);
169+
170+
setOperationAction(ISD::ATOMIC_STORE, MVT::f16, Promote);
171+
AddPromotedToType(ISD::ATOMIC_STORE, MVT::f16, MVT::i16);
172+
173+
setOperationAction(ISD::ATOMIC_STORE, MVT::bf16, Promote);
174+
AddPromotedToType(ISD::ATOMIC_STORE, MVT::bf16, MVT::i16);
175+
164176
// There are no 64-bit extloads. These should be done as a 32-bit extload and
165177
// an extension to 64-bit.
166178
for (MVT VT : MVT::integer_valuetypes())

‎llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -236,6 +236,10 @@ class AMDGPUTargetLowering : public TargetLowering {
236236
return AtomicExpansionKind::None;
237237
}
238238

239+
AtomicExpansionKind shouldCastAtomicStoreInIR(StoreInst *SI) const override {
240+
return AtomicExpansionKind::None;
241+
}
242+
239243
static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg);
240244
static CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg);
241245

‎llvm/test/Transforms/AtomicExpand/AMDGPU/no-expand-atomic-store.ll

Lines changed: 19 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -4,8 +4,7 @@
44
define void @store_atomic_f32_global_system(float %val, ptr addrspace(1) %ptr) {
55
; CHECK-LABEL: define void @store_atomic_f32_global_system(
66
; CHECK-SAME: float [[VAL:%.*]], ptr addrspace(1) [[PTR:%.*]]) {
7-
; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[VAL]] to i32
8-
; CHECK-NEXT: store atomic i32 [[TMP1]], ptr addrspace(1) [[PTR]] seq_cst, align 4
7+
; CHECK-NEXT: store atomic float [[VAL]], ptr addrspace(1) [[PTR]] seq_cst, align 4, !some.unknown.md [[META0:![0-9]+]]
98
; CHECK-NEXT: ret void
109
;
1110
store atomic float %val, ptr addrspace(1) %ptr seq_cst, align 4, !some.unknown.md !0
@@ -15,8 +14,7 @@ define void @store_atomic_f32_global_system(float %val, ptr addrspace(1) %ptr) {
1514
define void @store_atomic_f32_global_agent(float %val, ptr addrspace(1) %ptr) {
1615
; CHECK-LABEL: define void @store_atomic_f32_global_agent(
1716
; CHECK-SAME: float [[VAL:%.*]], ptr addrspace(1) [[PTR:%.*]]) {
18-
; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[VAL]] to i32
19-
; CHECK-NEXT: store atomic i32 [[TMP1]], ptr addrspace(1) [[PTR]] syncscope("agent") seq_cst, align 4
17+
; CHECK-NEXT: store atomic float [[VAL]], ptr addrspace(1) [[PTR]] syncscope("agent") seq_cst, align 4, !some.unknown.md [[META0]]
2018
; CHECK-NEXT: ret void
2119
;
2220
store atomic float %val, ptr addrspace(1) %ptr syncscope("agent") seq_cst, align 4, !some.unknown.md !0
@@ -26,8 +24,7 @@ define void @store_atomic_f32_global_agent(float %val, ptr addrspace(1) %ptr) {
2624
define void @store_atomic_f32_local(float %val, ptr addrspace(3) %ptr) {
2725
; CHECK-LABEL: define void @store_atomic_f32_local(
2826
; CHECK-SAME: float [[VAL:%.*]], ptr addrspace(3) [[PTR:%.*]]) {
29-
; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[VAL]] to i32
30-
; CHECK-NEXT: store atomic i32 [[TMP1]], ptr addrspace(3) [[PTR]] seq_cst, align 4
27+
; CHECK-NEXT: store atomic float [[VAL]], ptr addrspace(3) [[PTR]] seq_cst, align 4, !some.unknown.md [[META0]]
3128
; CHECK-NEXT: ret void
3229
;
3330
store atomic float %val, ptr addrspace(3) %ptr seq_cst, align 4, !some.unknown.md !0
@@ -37,8 +34,7 @@ define void @store_atomic_f32_local(float %val, ptr addrspace(3) %ptr) {
3734
define void @store_atomic_f32_flat(float %val, ptr %ptr) {
3835
; CHECK-LABEL: define void @store_atomic_f32_flat(
3936
; CHECK-SAME: float [[VAL:%.*]], ptr [[PTR:%.*]]) {
40-
; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[VAL]] to i32
41-
; CHECK-NEXT: store atomic i32 [[TMP1]], ptr [[PTR]] seq_cst, align 4
37+
; CHECK-NEXT: store atomic float [[VAL]], ptr [[PTR]] seq_cst, align 4, !some.unknown.md [[META0]]
4238
; CHECK-NEXT: ret void
4339
;
4440
store atomic float %val, ptr %ptr seq_cst, align 4, !some.unknown.md !0
@@ -48,8 +44,7 @@ define void @store_atomic_f32_flat(float %val, ptr %ptr) {
4844
define void @store_atomic_f16_global_system(half %val, ptr addrspace(1) %ptr) {
4945
; CHECK-LABEL: define void @store_atomic_f16_global_system(
5046
; CHECK-SAME: half [[VAL:%.*]], ptr addrspace(1) [[PTR:%.*]]) {
51-
; CHECK-NEXT: [[TMP1:%.*]] = bitcast half [[VAL]] to i16
52-
; CHECK-NEXT: store atomic i16 [[TMP1]], ptr addrspace(1) [[PTR]] seq_cst, align 4
47+
; CHECK-NEXT: store atomic half [[VAL]], ptr addrspace(1) [[PTR]] seq_cst, align 4, !some.unknown.md [[META0]]
5348
; CHECK-NEXT: ret void
5449
;
5550
store atomic half %val, ptr addrspace(1) %ptr seq_cst, align 4, !some.unknown.md !0
@@ -59,8 +54,7 @@ define void @store_atomic_f16_global_system(half %val, ptr addrspace(1) %ptr) {
5954
define void @store_atomic_f16_global_agent(half %val, ptr addrspace(1) %ptr) {
6055
; CHECK-LABEL: define void @store_atomic_f16_global_agent(
6156
; CHECK-SAME: half [[VAL:%.*]], ptr addrspace(1) [[PTR:%.*]]) {
62-
; CHECK-NEXT: [[TMP1:%.*]] = bitcast half [[VAL]] to i16
63-
; CHECK-NEXT: store atomic i16 [[TMP1]], ptr addrspace(1) [[PTR]] syncscope("agent") seq_cst, align 4
57+
; CHECK-NEXT: store atomic half [[VAL]], ptr addrspace(1) [[PTR]] syncscope("agent") seq_cst, align 4, !some.unknown.md [[META0]]
6458
; CHECK-NEXT: ret void
6559
;
6660
store atomic half %val, ptr addrspace(1) %ptr syncscope("agent") seq_cst, align 4, !some.unknown.md !0
@@ -70,8 +64,7 @@ define void @store_atomic_f16_global_agent(half %val, ptr addrspace(1) %ptr) {
7064
define void @store_atomic_f16_local(half %val, ptr addrspace(3) %ptr) {
7165
; CHECK-LABEL: define void @store_atomic_f16_local(
7266
; CHECK-SAME: half [[VAL:%.*]], ptr addrspace(3) [[PTR:%.*]]) {
73-
; CHECK-NEXT: [[TMP1:%.*]] = bitcast half [[VAL]] to i16
74-
; CHECK-NEXT: store atomic i16 [[TMP1]], ptr addrspace(3) [[PTR]] seq_cst, align 4
67+
; CHECK-NEXT: store atomic half [[VAL]], ptr addrspace(3) [[PTR]] seq_cst, align 4, !some.unknown.md [[META0]]
7568
; CHECK-NEXT: ret void
7669
;
7770
store atomic half %val, ptr addrspace(3) %ptr seq_cst, align 4, !some.unknown.md !0
@@ -81,8 +74,7 @@ define void @store_atomic_f16_local(half %val, ptr addrspace(3) %ptr) {
8174
define void @store_atomic_f16_flat(half %val, ptr %ptr) {
8275
; CHECK-LABEL: define void @store_atomic_f16_flat(
8376
; CHECK-SAME: half [[VAL:%.*]], ptr [[PTR:%.*]]) {
84-
; CHECK-NEXT: [[TMP1:%.*]] = bitcast half [[VAL]] to i16
85-
; CHECK-NEXT: store atomic i16 [[TMP1]], ptr [[PTR]] seq_cst, align 4
77+
; CHECK-NEXT: store atomic half [[VAL]], ptr [[PTR]] seq_cst, align 4, !some.unknown.md [[META0]]
8678
; CHECK-NEXT: ret void
8779
;
8880
store atomic half %val, ptr %ptr seq_cst, align 4, !some.unknown.md !0
@@ -92,8 +84,7 @@ define void @store_atomic_f16_flat(half %val, ptr %ptr) {
9284
define void @store_atomic_bf16_global_system(bfloat %val, ptr addrspace(1) %ptr) {
9385
; CHECK-LABEL: define void @store_atomic_bf16_global_system(
9486
; CHECK-SAME: bfloat [[VAL:%.*]], ptr addrspace(1) [[PTR:%.*]]) {
95-
; CHECK-NEXT: [[TMP1:%.*]] = bitcast bfloat [[VAL]] to i16
96-
; CHECK-NEXT: store atomic i16 [[TMP1]], ptr addrspace(1) [[PTR]] seq_cst, align 4
87+
; CHECK-NEXT: store atomic bfloat [[VAL]], ptr addrspace(1) [[PTR]] seq_cst, align 4, !some.unknown.md [[META0]]
9788
; CHECK-NEXT: ret void
9889
;
9990
store atomic bfloat %val, ptr addrspace(1) %ptr seq_cst, align 4, !some.unknown.md !0
@@ -103,8 +94,7 @@ define void @store_atomic_bf16_global_system(bfloat %val, ptr addrspace(1) %ptr)
10394
define void @store_atomic_bf16_global_agent(bfloat %val, ptr addrspace(1) %ptr) {
10495
; CHECK-LABEL: define void @store_atomic_bf16_global_agent(
10596
; CHECK-SAME: bfloat [[VAL:%.*]], ptr addrspace(1) [[PTR:%.*]]) {
106-
; CHECK-NEXT: [[TMP1:%.*]] = bitcast bfloat [[VAL]] to i16
107-
; CHECK-NEXT: store atomic i16 [[TMP1]], ptr addrspace(1) [[PTR]] syncscope("agent") seq_cst, align 4
97+
; CHECK-NEXT: store atomic bfloat [[VAL]], ptr addrspace(1) [[PTR]] syncscope("agent") seq_cst, align 4, !some.unknown.md [[META0]]
10898
; CHECK-NEXT: ret void
10999
;
110100
store atomic bfloat %val, ptr addrspace(1) %ptr syncscope("agent") seq_cst, align 4, !some.unknown.md !0
@@ -114,8 +104,7 @@ define void @store_atomic_bf16_global_agent(bfloat %val, ptr addrspace(1) %ptr)
114104
define void @store_atomic_bf16_local(bfloat %val, ptr addrspace(3) %ptr) {
115105
; CHECK-LABEL: define void @store_atomic_bf16_local(
116106
; CHECK-SAME: bfloat [[VAL:%.*]], ptr addrspace(3) [[PTR:%.*]]) {
117-
; CHECK-NEXT: [[TMP1:%.*]] = bitcast bfloat [[VAL]] to i16
118-
; CHECK-NEXT: store atomic i16 [[TMP1]], ptr addrspace(3) [[PTR]] seq_cst, align 4
107+
; CHECK-NEXT: store atomic bfloat [[VAL]], ptr addrspace(3) [[PTR]] seq_cst, align 4, !some.unknown.md [[META0]]
119108
; CHECK-NEXT: ret void
120109
;
121110
store atomic bfloat %val, ptr addrspace(3) %ptr seq_cst, align 4, !some.unknown.md !0
@@ -125,8 +114,7 @@ define void @store_atomic_bf16_local(bfloat %val, ptr addrspace(3) %ptr) {
125114
define void @store_atomic_bf16_flat(bfloat %val, ptr %ptr) {
126115
; CHECK-LABEL: define void @store_atomic_bf16_flat(
127116
; CHECK-SAME: bfloat [[VAL:%.*]], ptr [[PTR:%.*]]) {
128-
; CHECK-NEXT: [[TMP1:%.*]] = bitcast bfloat [[VAL]] to i16
129-
; CHECK-NEXT: store atomic i16 [[TMP1]], ptr [[PTR]] seq_cst, align 4
117+
; CHECK-NEXT: store atomic bfloat [[VAL]], ptr [[PTR]] seq_cst, align 4, !some.unknown.md [[META0]]
130118
; CHECK-NEXT: ret void
131119
;
132120
store atomic bfloat %val, ptr %ptr seq_cst, align 4, !some.unknown.md !0
@@ -135,8 +123,7 @@ define void @store_atomic_bf16_flat(bfloat %val, ptr %ptr) {
135123
define void @store_atomic_f64_global_system(double %val, ptr addrspace(1) %ptr) {
136124
; CHECK-LABEL: define void @store_atomic_f64_global_system(
137125
; CHECK-SAME: double [[VAL:%.*]], ptr addrspace(1) [[PTR:%.*]]) {
138-
; CHECK-NEXT: [[TMP1:%.*]] = bitcast double [[VAL]] to i64
139-
; CHECK-NEXT: store atomic i64 [[TMP1]], ptr addrspace(1) [[PTR]] seq_cst, align 8
126+
; CHECK-NEXT: store atomic double [[VAL]], ptr addrspace(1) [[PTR]] seq_cst, align 8, !some.unknown.md [[META0]]
140127
; CHECK-NEXT: ret void
141128
;
142129
store atomic double %val, ptr addrspace(1) %ptr seq_cst, align 8, !some.unknown.md !0
@@ -146,8 +133,7 @@ define void @store_atomic_f64_global_system(double %val, ptr addrspace(1) %ptr)
146133
define void @store_atomic_f64_global_agent(double %val, ptr addrspace(1) %ptr) {
147134
; CHECK-LABEL: define void @store_atomic_f64_global_agent(
148135
; CHECK-SAME: double [[VAL:%.*]], ptr addrspace(1) [[PTR:%.*]]) {
149-
; CHECK-NEXT: [[TMP1:%.*]] = bitcast double [[VAL]] to i64
150-
; CHECK-NEXT: store atomic i64 [[TMP1]], ptr addrspace(1) [[PTR]] syncscope("agent") seq_cst, align 8
136+
; CHECK-NEXT: store atomic double [[VAL]], ptr addrspace(1) [[PTR]] syncscope("agent") seq_cst, align 8, !some.unknown.md [[META0]]
151137
; CHECK-NEXT: ret void
152138
;
153139
store atomic double %val, ptr addrspace(1) %ptr syncscope("agent") seq_cst, align 8, !some.unknown.md !0
@@ -157,8 +143,7 @@ define void @store_atomic_f64_global_agent(double %val, ptr addrspace(1) %ptr) {
157143
define void @store_atomic_f64_local(double %val, ptr addrspace(3) %ptr) {
158144
; CHECK-LABEL: define void @store_atomic_f64_local(
159145
; CHECK-SAME: double [[VAL:%.*]], ptr addrspace(3) [[PTR:%.*]]) {
160-
; CHECK-NEXT: [[TMP1:%.*]] = bitcast double [[VAL]] to i64
161-
; CHECK-NEXT: store atomic i64 [[TMP1]], ptr addrspace(3) [[PTR]] seq_cst, align 8
146+
; CHECK-NEXT: store atomic double [[VAL]], ptr addrspace(3) [[PTR]] seq_cst, align 8, !some.unknown.md [[META0]]
162147
; CHECK-NEXT: ret void
163148
;
164149
store atomic double %val, ptr addrspace(3) %ptr seq_cst, align 8, !some.unknown.md !0
@@ -168,12 +153,14 @@ define void @store_atomic_f64_local(double %val, ptr addrspace(3) %ptr) {
168153
define void @store_atomic_f64_flat(double %val, ptr %ptr) {
169154
; CHECK-LABEL: define void @store_atomic_f64_flat(
170155
; CHECK-SAME: double [[VAL:%.*]], ptr [[PTR:%.*]]) {
171-
; CHECK-NEXT: [[TMP1:%.*]] = bitcast double [[VAL]] to i64
172-
; CHECK-NEXT: store atomic i64 [[TMP1]], ptr [[PTR]] seq_cst, align 8
156+
; CHECK-NEXT: store atomic double [[VAL]], ptr [[PTR]] seq_cst, align 8, !some.unknown.md [[META0]]
173157
; CHECK-NEXT: ret void
174158
;
175159
store atomic double %val, ptr %ptr seq_cst, align 8, !some.unknown.md !0
176160
ret void
177161
}
178162

179163
!0 = !{}
164+
;.
165+
; CHECK: [[META0]] = !{}
166+
;.

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