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fabianmcgfabianmcg
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Reland [mlir][test][gpu] Migrate CUDA tests to the TargetAttr compilation workflow (#65768)
The revert happened due to a build bot failure that threw 'CUDA_ERROR_UNSUPPORTED_PTX_VERSION'. The failure's root cause was a pass using "+ptx76" for compilation and an old CUDA driver on the bot. This commit relands the patch with "+ptx60". Original Gh PR: #65768 Original commit message: Migrate tests referencing `gpu-to-cubin` to the new compilation workflow using `TargetAttrs`. The `test-lower-to-nvvm` pass pipeline was modified to use the new compilation workflow to simplify the introduction of future tests. The `createLowerGpuOpsToNVVMOpsPass` function was removed, as it didn't allow for passing all options available in the `ConvertGpuOpsToNVVMOp` pass.
1 parent 2374ae4 commit 119c489

25 files changed

+63
-133
lines changed

‎mlir/include/mlir/Conversion/GPUToNVVM/GPUToNVVMPass.h

Lines changed: 1 addition & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -16,9 +16,7 @@ namespace mlir {
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class LLVMTypeConverter;
1717
class ConversionTarget;
1818
class RewritePatternSet;
19-
20-
template <typename OpT>
21-
class OperationPass;
19+
class Pass;
2220

2321
namespace gpu {
2422
class GPUModuleOp;
@@ -45,14 +43,6 @@ void populateGpuSubgroupReduceOpLoweringPattern(LLVMTypeConverter &converter,
4543
/// Collect a set of patterns to convert WMMA ops from GPU dialect to NVVM.
4644
void populateGpuWMMAToNVVMConversionPatterns(LLVMTypeConverter &converter,
4745
RewritePatternSet &patterns);
48-
49-
/// Creates a pass that lowers GPU dialect operations to NVVM counterparts. The
50-
/// index bitwidth used for the lowering of the device side index computations
51-
/// is configurable.
52-
std::unique_ptr<OperationPass<gpu::GPUModuleOp>> createLowerGpuOpsToNVVMOpsPass(
53-
unsigned indexBitwidth = kDeriveIndexBitwidthFromDataLayout,
54-
bool hasRedux = false);
55-
5646
} // namespace mlir
5747

5848
#endif // MLIR_CONVERSION_GPUTONVVM_GPUTONVVMPASS_H_

‎mlir/include/mlir/Conversion/Passes.td

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -486,7 +486,6 @@ def LowerHostCodeToLLVMPass : Pass<"lower-host-to-llvm", "ModuleOp"> {
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487487
def ConvertGpuOpsToNVVMOps : Pass<"convert-gpu-to-nvvm", "gpu::GPUModuleOp"> {
488488
let summary = "Generate NVVM operations for gpu operations";
489-
let constructor = "mlir::createLowerGpuOpsToNVVMOpsPass()";
490489
let dependentDialects = [
491490
"cf::ControlFlowDialect",
492491
"memref::MemRefDialect",

‎mlir/lib/Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp

Lines changed: 1 addition & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -210,11 +210,7 @@ struct GPULaneIdOpToNVVM : ConvertOpToLLVMPattern<gpu::LaneIdOp> {
210210
/// code.
211211
struct LowerGpuOpsToNVVMOpsPass
212212
: public impl::ConvertGpuOpsToNVVMOpsBase<LowerGpuOpsToNVVMOpsPass> {
213-
LowerGpuOpsToNVVMOpsPass() = default;
214-
LowerGpuOpsToNVVMOpsPass(unsigned indexBitwidth, bool hasRedux = false) {
215-
this->indexBitwidth = indexBitwidth;
216-
this->hasRedux = hasRedux;
217-
}
213+
using Base::Base;
218214

219215
void runOnOperation() override {
220216
gpu::GPUModuleOp m = getOperation();
@@ -378,8 +374,3 @@ void mlir::populateGpuToNVVMConversionPatterns(LLVMTypeConverter &converter,
378374
"__nv_tanh");
379375
populateOpPatterns<math::TanOp>(converter, patterns, "__nv_tanf", "__nv_tan");
380376
}
381-
382-
std::unique_ptr<OperationPass<gpu::GPUModuleOp>>
383-
mlir::createLowerGpuOpsToNVVMOpsPass(unsigned indexBitwidth, bool hasRedux) {
384-
return std::make_unique<LowerGpuOpsToNVVMOpsPass>(indexBitwidth, hasRedux);
385-
}

‎mlir/lib/Dialect/SparseTensor/Pipelines/SparseTensorPipelines.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -52,7 +52,7 @@ void mlir::sparse_tensor::buildSparseCompiler(
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pm.addPass(createSparseGPUCodegenPass());
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pm.addNestedPass<gpu::GPUModuleOp>(createStripDebugInfoPass());
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pm.addNestedPass<gpu::GPUModuleOp>(createConvertSCFToCFPass());
55-
pm.addNestedPass<gpu::GPUModuleOp>(createLowerGpuOpsToNVVMOpsPass());
55+
pm.addNestedPass<gpu::GPUModuleOp>(createConvertGpuOpsToNVVMOps());
5656
}
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5858
// TODO(springerm): Add sparse support to the BufferDeallocation pass and add

‎mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/dump-ptx.mlir

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@@ -1,6 +1,5 @@
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// RUN: mlir-opt %s \
2-
// RUN: | mlir-opt -gpu-kernel-outlining \
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// RUN: | mlir-opt -pass-pipeline='builtin.module(gpu.module(strip-debuginfo,convert-gpu-to-nvvm,gpu-to-cubin{dump-ptx}))' \
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// RUN: | mlir-opt -test-lower-to-nvvm -debug-only=serialize-to-isa \
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// RUN: 2>&1 | FileCheck %s
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// CHECK: Generated by LLVM NVPTX Back-End

‎mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/sparse-mma-2-4-f16.mlir

Lines changed: 2 additions & 3 deletions
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@@ -2,10 +2,9 @@
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// NOTE: this test requires gpu-sm80
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//
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// RUN: mlir-opt \
5-
// RUN: --pass-pipeline="builtin.module(gpu.module(strip-debuginfo,convert-gpu-to-nvvm,convert-nvgpu-to-nvvm,affine-expand-index-ops,lower-affine,convert-arith-to-llvm),convert-vector-to-llvm,canonicalize,cse,gpu.module(gpu-to-cubin{chip=sm_80 features=+ptx71}))" \
5+
// RUN: --pass-pipeline="builtin.module(gpu.module(strip-debuginfo,convert-gpu-to-nvvm,convert-nvgpu-to-nvvm,affine-expand-index-ops,lower-affine,convert-arith-to-llvm),convert-vector-to-llvm,canonicalize,cse)" \
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// RUN: %s \
7-
// RUN: | mlir-opt --convert-vector-to-scf --convert-scf-to-cf -convert-cf-to-llvm --convert-vector-to-llvm \
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// RUN: --convert-arith-to-llvm --gpu-to-llvm --reconcile-unrealized-casts \
7+
// RUN: | mlir-opt --test-lower-to-nvvm="cubin-chip=sm_80 cubin-features=+ptx71" \
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// RUN: | mlir-cpu-runner \
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// RUN: --shared-libs=%mlir_cuda_runtime \
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// RUN: --shared-libs=%mlir_c_runner_utils \

‎mlir/test/Integration/Dialect/Vector/GPU/CUDA/test-reduction-distribute.mlir

Lines changed: 1 addition & 3 deletions
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@@ -1,9 +1,7 @@
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// RUN: mlir-opt %s -test-vector-warp-distribute="hoist-uniform distribute-transfer-write propagate-distribution" -canonicalize |\
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// RUN: mlir-opt -test-vector-warp-distribute=rewrite-warp-ops-to-scf-if |\
33
// RUN: mlir-opt -lower-affine -convert-vector-to-scf -convert-scf-to-cf -convert-vector-to-llvm \
4-
// RUN: -convert-arith-to-llvm -gpu-kernel-outlining |\
5-
// RUN: mlir-opt -pass-pipeline='builtin.module(gpu.module(strip-debuginfo,convert-gpu-to-nvvm,reconcile-unrealized-casts,gpu-to-cubin))' |\
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// RUN: mlir-opt -gpu-to-llvm -reconcile-unrealized-casts |\
4+
// RUN: -convert-arith-to-llvm -test-lower-to-nvvm | \
75
// RUN: mlir-cpu-runner -e main -entry-point-result=void \
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// RUN: -shared-libs=%mlir_cuda_runtime \
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// RUN: -shared-libs=%mlir_c_runner_utils \

‎mlir/test/Integration/Dialect/Vector/GPU/CUDA/test-warp-distribute.mlir

Lines changed: 3 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -2,9 +2,7 @@
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// everything on the same thread.
33
// RUN: mlir-opt %s -test-vector-warp-distribute=rewrite-warp-ops-to-scf-if -canonicalize | \
44
// RUN: mlir-opt -convert-vector-to-scf -convert-scf-to-cf -convert-cf-to-llvm -convert-vector-to-llvm -convert-arith-to-llvm \
5-
// RUN: -gpu-kernel-outlining |\
6-
// RUN: mlir-opt -pass-pipeline='builtin.module(gpu.module(strip-debuginfo,convert-gpu-to-nvvm,reconcile-unrealized-casts,gpu-to-cubin))' |\
7-
// RUN: mlir-opt -gpu-to-llvm -reconcile-unrealized-casts |\
5+
// RUN: -test-lower-to-nvvm | \
86
// RUN: mlir-cpu-runner -e main -entry-point-result=void \
97
// RUN: -shared-libs=%mlir_cuda_runtime \
108
// RUN: -shared-libs=%mlir_c_runner_utils \
@@ -15,9 +13,7 @@
1513
// RUN: mlir-opt %s -test-vector-warp-distribute="hoist-uniform distribute-transfer-write" \
1614
// RUN: -test-vector-warp-distribute=rewrite-warp-ops-to-scf-if -canonicalize | \
1715
// RUN: mlir-opt -convert-vector-to-scf -convert-scf-to-cf -convert-cf-to-llvm -convert-vector-to-llvm -convert-arith-to-llvm \
18-
// RUN: -gpu-kernel-outlining |\
19-
// RUN: mlir-opt -pass-pipeline='builtin.module(gpu.module(strip-debuginfo,convert-gpu-to-nvvm,reconcile-unrealized-casts,gpu-to-cubin))' |\
20-
// RUN: mlir-opt -gpu-to-llvm -reconcile-unrealized-casts |\
16+
// RUN: -test-lower-to-nvvm | \
2117
// RUN: mlir-cpu-runner -e main -entry-point-result=void \
2218
// RUN: -shared-libs=%mlir_cuda_runtime \
2319
// RUN: -shared-libs=%mlir_c_runner_utils \
@@ -27,9 +23,7 @@
2723
// RUN: mlir-opt %s -test-vector-warp-distribute="hoist-uniform distribute-transfer-write propagate-distribution" \
2824
// RUN: -test-vector-warp-distribute=rewrite-warp-ops-to-scf-if -canonicalize | \
2925
// RUN: mlir-opt -convert-vector-to-scf -convert-scf-to-cf -convert-cf-to-llvm -convert-vector-to-llvm -convert-arith-to-llvm \
30-
// RUN: -gpu-kernel-outlining |\
31-
// RUN: mlir-opt -pass-pipeline='builtin.module(gpu.module(strip-debuginfo,convert-gpu-to-nvvm,reconcile-unrealized-casts,gpu-to-cubin))' |\
32-
// RUN: mlir-opt -gpu-to-llvm -reconcile-unrealized-casts |\
26+
// RUN: -test-lower-to-nvvm | \
3327
// RUN: mlir-cpu-runner -e main -entry-point-result=void \
3428
// RUN: -shared-libs=%mlir_cuda_runtime \
3529
// RUN: -shared-libs=%mlir_c_runner_utils \

‎mlir/test/Integration/GPU/CUDA/TensorCore/wmma-matmul-f16.mlir

Lines changed: 1 addition & 3 deletions
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@@ -1,7 +1,5 @@
11
// RUN: mlir-opt %s \
2-
// RUN: | mlir-opt -gpu-kernel-outlining \
3-
// RUN: | mlir-opt -pass-pipeline='builtin.module(gpu.module(strip-debuginfo,convert-gpu-to-nvvm,gpu-to-cubin{chip=sm_70}))' \
4-
// RUN: | mlir-opt --convert-scf-to-cf -gpu-to-llvm \
2+
// RUN: | mlir-opt -test-lower-to-nvvm="cubin-chip=sm_70" \
53
// RUN: | mlir-cpu-runner \
64
// RUN: --shared-libs=%mlir_cuda_runtime \
75
// RUN: --shared-libs=%mlir_runner_utils \

‎mlir/test/Integration/GPU/CUDA/TensorCore/wmma-matmul-f32-bare-ptr.mlir

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@@ -3,9 +3,7 @@
33
// Similar to the wmma-matmul-f32 but but with the memref bare pointer lowering convention.
44
// This test also uses gpu.memcpy operations (instead of gpu.host_register).
55
// RUN: mlir-opt %s \
6-
// RUN: | mlir-opt -gpu-kernel-outlining \
7-
// RUN: | mlir-opt -pass-pipeline='builtin.module(gpu.module(strip-debuginfo,convert-gpu-to-nvvm{use-bare-ptr-memref-call-conv=1},gpu-to-cubin{chip=sm_70}))' \
8-
// RUN: | mlir-opt --convert-scf-to-cf -gpu-to-llvm="use-bare-pointers-for-host=1 use-bare-pointers-for-kernels=1" \
6+
// RUN: | mlir-opt -test-lower-to-nvvm="host-bare-ptr-calling-convention=1 kernel-bare-ptr-calling-convention=1 cubin-chip=sm_70" \
97
// RUN: | mlir-cpu-runner \
108
// RUN: --shared-libs=%mlir_cuda_runtime \
119
// RUN: --entry-point-result=void \

‎mlir/test/Integration/GPU/CUDA/TensorCore/wmma-matmul-f32.mlir

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Original file line numberDiff line numberDiff line change
@@ -1,7 +1,5 @@
11
// RUN: mlir-opt %s \
2-
// RUN: | mlir-opt -gpu-kernel-outlining \
3-
// RUN: | mlir-opt -pass-pipeline='builtin.module(gpu.module(strip-debuginfo,convert-gpu-to-nvvm,gpu-to-cubin{chip=sm_70}))' \
4-
// RUN: | mlir-opt --convert-scf-to-cf -gpu-to-llvm \
2+
// RUN: | mlir-opt -test-lower-to-nvvm="cubin-chip=sm_70" \
53
// RUN: | mlir-cpu-runner \
64
// RUN: --shared-libs=%mlir_cuda_runtime \
75
// RUN: --shared-libs=%mlir_runner_utils \

‎mlir/test/Integration/GPU/CUDA/all-reduce-and.mlir

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@@ -1,7 +1,5 @@
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// RUN: mlir-opt %s \
2-
// RUN: | mlir-opt -gpu-kernel-outlining \
3-
// RUN: | mlir-opt -pass-pipeline='builtin.module(gpu.module(strip-debuginfo,convert-gpu-to-nvvm,gpu-to-cubin))' \
4-
// RUN: | mlir-opt -gpu-to-llvm \
2+
// RUN: | mlir-opt -test-lower-to-nvvm \
53
// RUN: | mlir-cpu-runner \
64
// RUN: --shared-libs=%mlir_cuda_runtime \
75
// RUN: --shared-libs=%mlir_runner_utils \
@@ -10,9 +8,7 @@
108

119
// Same as above but with the memref bare pointer lowering convention.
1210
// RUN: mlir-opt %s \
13-
// RUN: | mlir-opt -gpu-kernel-outlining \
14-
// RUN: | mlir-opt -pass-pipeline='builtin.module(gpu.module(strip-debuginfo,convert-gpu-to-nvvm{use-bare-ptr-memref-call-conv=1},gpu-to-cubin))' \
15-
// RUN: | mlir-opt -gpu-to-llvm="use-bare-pointers-for-kernels=1" \
11+
// RUN: | mlir-opt -test-lower-to-nvvm="kernel-bare-ptr-calling-convention=1" \
1612
// RUN: | mlir-cpu-runner \
1713
// RUN: --shared-libs=%mlir_cuda_runtime \
1814
// RUN: --shared-libs=%mlir_runner_utils \

‎mlir/test/Integration/GPU/CUDA/all-reduce-max.mlir

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@@ -1,7 +1,5 @@
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// RUN: mlir-opt %s \
2-
// RUN: | mlir-opt -gpu-kernel-outlining \
3-
// RUN: | mlir-opt -pass-pipeline='builtin.module(gpu.module(strip-debuginfo,convert-gpu-to-nvvm,gpu-to-cubin))' \
4-
// RUN: | mlir-opt -gpu-to-llvm \
2+
// RUN: | mlir-opt -test-lower-to-nvvm \
53
// RUN: | mlir-cpu-runner \
64
// RUN: --shared-libs=%mlir_cuda_runtime \
75
// RUN: --shared-libs=%mlir_runner_utils \

‎mlir/test/Integration/GPU/CUDA/all-reduce-min.mlir

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@@ -1,7 +1,5 @@
11
// RUN: mlir-opt %s \
2-
// RUN: | mlir-opt -gpu-kernel-outlining \
3-
// RUN: | mlir-opt -pass-pipeline='builtin.module(gpu.module(strip-debuginfo,convert-gpu-to-nvvm,gpu-to-cubin))' \
4-
// RUN: | mlir-opt -gpu-to-llvm \
2+
// RUN: | mlir-opt -test-lower-to-nvvm \
53
// RUN: | mlir-cpu-runner \
64
// RUN: --shared-libs=%mlir_cuda_runtime \
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// RUN: --shared-libs=%mlir_runner_utils \

‎mlir/test/Integration/GPU/CUDA/all-reduce-op.mlir

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@@ -1,7 +1,5 @@
11
// RUN: mlir-opt %s \
2-
// RUN: | mlir-opt -gpu-kernel-outlining \
3-
// RUN: | mlir-opt -pass-pipeline='builtin.module(gpu.module(strip-debuginfo,convert-gpu-to-nvvm,gpu-to-cubin))' \
4-
// RUN: | mlir-opt -gpu-to-llvm \
2+
// RUN: | mlir-opt -test-lower-to-nvvm \
53
// RUN: | mlir-cpu-runner \
64
// RUN: --shared-libs=%mlir_cuda_runtime \
75
// RUN: --shared-libs=%mlir_runner_utils \

‎mlir/test/Integration/GPU/CUDA/all-reduce-or.mlir

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@@ -1,7 +1,5 @@
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// RUN: mlir-opt %s \
2-
// RUN: | mlir-opt -gpu-kernel-outlining \
3-
// RUN: | mlir-opt -pass-pipeline='builtin.module(gpu.module(strip-debuginfo,convert-gpu-to-nvvm,gpu-to-cubin))' \
4-
// RUN: | mlir-opt -gpu-to-llvm \
2+
// RUN: | mlir-opt -test-lower-to-nvvm \
53
// RUN: | mlir-cpu-runner \
64
// RUN: --shared-libs=%mlir_cuda_runtime \
75
// RUN: --shared-libs=%mlir_runner_utils \

‎mlir/test/Integration/GPU/CUDA/all-reduce-region.mlir

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@@ -1,7 +1,5 @@
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// RUN: mlir-opt %s \
2-
// RUN: | mlir-opt -gpu-kernel-outlining \
3-
// RUN: | mlir-opt -pass-pipeline='builtin.module(gpu.module(strip-debuginfo,convert-gpu-to-nvvm,gpu-to-cubin))' \
4-
// RUN: | mlir-opt -gpu-to-llvm \
2+
// RUN: | mlir-opt -test-lower-to-nvvm \
53
// RUN: | mlir-cpu-runner \
64
// RUN: --shared-libs=%mlir_cuda_runtime \
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// RUN: --shared-libs=%mlir_runner_utils \

‎mlir/test/Integration/GPU/CUDA/all-reduce-xor.mlir

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@@ -1,7 +1,5 @@
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// RUN: mlir-opt %s \
2-
// RUN: | mlir-opt -gpu-kernel-outlining \
3-
// RUN: | mlir-opt -pass-pipeline='builtin.module(gpu.module(strip-debuginfo,convert-gpu-to-nvvm,gpu-to-cubin))' \
4-
// RUN: | mlir-opt -gpu-to-llvm \
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// RUN: | mlir-opt -test-lower-to-nvvm \
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// RUN: | mlir-cpu-runner \
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// RUN: --shared-libs=%mlir_cuda_runtime \
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// RUN: --shared-libs=%mlir_runner_utils \

‎mlir/test/Integration/GPU/CUDA/async.mlir

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// RUN: mlir-opt %s \
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// RUN: | mlir-opt -gpu-kernel-outlining \
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// RUN: | mlir-opt -pass-pipeline='builtin.module(gpu.module(strip-debuginfo,convert-gpu-to-nvvm,gpu-to-cubin))' \
4-
// RUN: | mlir-opt -gpu-async-region -gpu-to-llvm \
3+
// RUN: | mlir-opt -pass-pipeline='builtin.module(gpu.module(strip-debuginfo,convert-gpu-to-nvvm),nvvm-attach-target)' \
4+
// RUN: | mlir-opt -gpu-async-region -gpu-to-llvm -gpu-module-to-binary \
55
// RUN: | mlir-opt -async-to-async-runtime -async-runtime-ref-counting \
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// RUN: | mlir-opt -convert-async-to-llvm -convert-func-to-llvm \
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// RUN: | mlir-cpu-runner \

‎mlir/test/Integration/GPU/CUDA/gpu-to-cubin.mlir

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// RUN: mlir-opt %s \
2-
// RUN: | mlir-opt -gpu-kernel-outlining \
3-
// RUN: | mlir-opt -convert-vector-to-scf -convert-scf-to-cf -convert-cf-to-llvm -convert-vector-to-llvm -convert-arith-to-llvm \
4-
// RUN: | mlir-opt -pass-pipeline='builtin.module(gpu.module(strip-debuginfo,convert-gpu-to-nvvm,gpu-to-cubin))' \
5-
// RUN: | mlir-opt -gpu-to-llvm -reconcile-unrealized-casts \
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// RUN: | mlir-opt -test-lower-to-nvvm \
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// RUN: | mlir-cpu-runner \
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// RUN: --shared-libs=%mlir_cuda_runtime \
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// RUN: --shared-libs=%mlir_runner_utils \

‎mlir/test/Integration/GPU/CUDA/multiple-all-reduce.mlir

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// RUN: mlir-opt %s \
2-
// RUN: | mlir-opt -gpu-kernel-outlining \
3-
// RUN: | mlir-opt -pass-pipeline='builtin.module(gpu.module(strip-debuginfo,convert-gpu-to-nvvm,gpu-to-cubin))' \
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// RUN: | mlir-opt -gpu-to-llvm \
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// RUN: | mlir-opt -test-lower-to-nvvm \
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// RUN: | mlir-cpu-runner \
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// RUN: --shared-libs=%mlir_cuda_runtime \
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// RUN: --shared-libs=%mlir_runner_utils \

‎mlir/test/Integration/GPU/CUDA/printf.mlir

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@@ -1,6 +1,5 @@
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// RUN: mlir-opt %s \
2-
// RUN: | mlir-opt -pass-pipeline='builtin.module(gpu.module(strip-debuginfo,convert-gpu-to-nvvm,gpu-to-cubin))' \
3-
// RUN: | mlir-opt -gpu-to-llvm \
2+
// RUN: | mlir-opt -test-lower-to-nvvm \
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// RUN: | mlir-cpu-runner \
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// RUN: --shared-libs=%mlir_cuda_runtime \
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// RUN: --shared-libs=%mlir_runner_utils \

‎mlir/test/Integration/GPU/CUDA/shuffle.mlir

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// RUN: mlir-opt %s \
2-
// RUN: | mlir-opt -gpu-kernel-outlining \
3-
// RUN: | mlir-opt -pass-pipeline='builtin.module(gpu.module(strip-debuginfo,convert-gpu-to-nvvm,gpu-to-cubin))' \
4-
// RUN: | mlir-opt -gpu-to-llvm \
2+
// RUN: | mlir-opt -test-lower-to-nvvm \
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// RUN: | mlir-cpu-runner \
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// RUN: --shared-libs=%mlir_cuda_runtime \
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// RUN: --shared-libs=%mlir_runner_utils \

‎mlir/test/Integration/GPU/CUDA/two-modules.mlir

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// RUN: mlir-opt %s \
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// RUN: | mlir-opt -gpu-kernel-outlining \
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// RUN: | mlir-opt -pass-pipeline='builtin.module(gpu.module(strip-debuginfo,convert-gpu-to-nvvm,gpu-to-cubin))' \
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// RUN: | mlir-opt -gpu-to-llvm \
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// RUN: | mlir-opt -test-lower-to-nvvm \
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// RUN: | mlir-cpu-runner \
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// RUN: --shared-libs=%mlir_cuda_runtime \
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// RUN: --shared-libs=%mlir_runner_utils \

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