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1 parent 140e80a commit 1061c6dCopy full SHA for 1061c6d
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -21555,10 +21555,10 @@ bool RISCVTargetLowering::splitValueIntoRegisterParts(
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if (ValueVT.isRISCVVectorTuple() && PartVT.isRISCVVectorTuple()) {
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unsigned ValNF = ValueVT.getRISCVVectorTupleNumFields();
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- unsigned ValLMUL =
+ [[maybe_unused]] unsigned ValLMUL =
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divideCeil(ValueVT.getSizeInBits(), ValNF * RISCV::RVVBitsPerBlock);
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unsigned PartNF = PartVT.getRISCVVectorTupleNumFields();
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- unsigned PartLMUL =
+ [[maybe_unused]] unsigned PartLMUL =
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divideCeil(PartVT.getSizeInBits(), PartNF * RISCV::RVVBitsPerBlock);
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assert(ValNF == PartNF && ValLMUL == PartLMUL &&
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"RISC-V vector tuple type only accepts same register class type "
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