Precommit test

Author: jf-botto

llvm/test/CodeGen/AArch64/icmp-ult-eq-fold.ll

@@ -0,0 +1,227 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
+
+
+define i1 @lt8_u8(i8 %0) {
+; CHECK-LABEL: lt8_u8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0xff
+; CHECK-NEXT:    cmp w8, #8
+; CHECK-NEXT:    cset w0, lo
+; CHECK-NEXT:    ret
+  %2 = icmp ult i8 %0, 8
+  ret i1 %2
+}
+
+define i1 @lt32_u8(i8 %0) {
+; CHECK-LABEL: lt32_u8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0xff
+; CHECK-NEXT:    cmp w8, #32
+; CHECK-NEXT:    cset w0, lo
+; CHECK-NEXT:    ret
+  %2 = icmp ult i8 %0, 32
+  ret i1 %2
+}
+
+define i1 @lt64_u8(i8 %0) {
+; CHECK-LABEL: lt64_u8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0xff
+; CHECK-NEXT:    cmp w8, #64
+; CHECK-NEXT:    cset w0, lo
+; CHECK-NEXT:    ret
+  %2 = icmp ult i8 %0, 64
+  ret i1 %2
+}
+
+define i1 @lt8_u32(i32 %0) {
+; CHECK-LABEL: lt8_u32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    cmp w0, #8
+; CHECK-NEXT:    cset w0, lo
+; CHECK-NEXT:    ret
+  %2 = icmp ult i32 %0, 8
+  ret i1 %2
+}
+
+define i1 @lt32_u32(i32 %0) {
+; CHECK-LABEL: lt32_u32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    cmp w0, #32
+; CHECK-NEXT:    cset w0, lo
+; CHECK-NEXT:    ret
+  %2 = icmp ult i32 %0, 32
+  ret i1 %2
+}
+
+define i1 @lt64_u32(i32 %0) {
+; CHECK-LABEL: lt64_u32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    cmp w0, #64
+; CHECK-NEXT:    cset w0, lo
+; CHECK-NEXT:    ret
+  %2 = icmp ult i32 %0, 64
+  ret i1 %2
+}
+
+define i1 @lt8_u64(i64 %0) {
+; CHECK-LABEL: lt8_u64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    cmp x0, #8
+; CHECK-NEXT:    cset w0, lo
+; CHECK-NEXT:    ret
+  %2 = icmp ult i64 %0, 8
+  ret i1 %2
+}
+
+define i1 @lt32_u64(i64 %0) {
+; CHECK-LABEL: lt32_u64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    cmp x0, #32
+; CHECK-NEXT:    cset w0, lo
+; CHECK-NEXT:    ret
+  %2 = icmp ult i64 %0, 32
+  ret i1 %2
+}
+
+define i1 @lt64_u64(i64 %0) {
+; CHECK-LABEL: lt64_u64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    cmp x0, #64
+; CHECK-NEXT:    cset w0, lo
+; CHECK-NEXT:    ret
+  %2 = icmp ult i64 %0, 64
+  ret i1 %2
+}
+
+define i1 @lt8_u16_and_5(i8 %0) {
+; CHECK-LABEL: lt8_u16_and_5:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #5 // =0x5
+; CHECK-NEXT:    and w8, w0, w8
+; CHECK-NEXT:    cmp w8, #16
+; CHECK-NEXT:    cset w0, lo
+; CHECK-NEXT:    ret
+  %2 = and i8 %0, 5
+  %3 = icmp ult i8 %2, 16
+  ret i1 %3
+}
+
+define i1 @lt8_u16_and_19(i8 %0) {
+; CHECK-LABEL: lt8_u16_and_19:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #19 // =0x13
+; CHECK-NEXT:    and w8, w0, w8
+; CHECK-NEXT:    cmp w8, #16
+; CHECK-NEXT:    cset w0, lo
+; CHECK-NEXT:    ret
+  %2 = and i8 %0, 19
+  %3 = icmp ult i8 %2, 16
+  ret i1 %3
+}
+
+define i1 @lt32_u16_and_7(i32 %0) {
+; CHECK-LABEL: lt32_u16_and_7:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0x7
+; CHECK-NEXT:    cmp w8, #16
+; CHECK-NEXT:    cset w0, lo
+; CHECK-NEXT:    ret
+  %2 = and i32 %0, 7
+  %3 = icmp ult i32 %2, 16
+  ret i1 %3
+}
+
+define i1 @lt32_u16_and_21(i32 %0) {
+; CHECK-LABEL: lt32_u16_and_21:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #21 // =0x15
+; CHECK-NEXT:    and w8, w0, w8
+; CHECK-NEXT:    cmp w8, #16
+; CHECK-NEXT:    cset w0, lo
+; CHECK-NEXT:    ret
+  %2 = and i32 %0, 21
+  %3 = icmp ult i32 %2, 16
+  ret i1 %3
+}
+
+define i1 @lt64_u16_and_9(i64 %0) {
+; CHECK-LABEL: lt64_u16_and_9:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #9 // =0x9
+; CHECK-NEXT:    and x8, x0, x8
+; CHECK-NEXT:    cmp x8, #16
+; CHECK-NEXT:    cset w0, lo
+; CHECK-NEXT:    ret
+  %2 = and i64 %0, 9
+  %3 = icmp ult i64 %2, 16
+  ret i1 %3
+}
+
+define i1 @lt64_u16_and_23(i64 %0) {
+; CHECK-LABEL: lt64_u16_and_23:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #23 // =0x17
+; CHECK-NEXT:    and x8, x0, x8
+; CHECK-NEXT:    cmp x8, #16
+; CHECK-NEXT:    cset w0, lo
+; CHECK-NEXT:    ret
+  %2 = and i64 %0, 23
+  %3 = icmp ult i64 %2, 16
+  ret i1 %3
+}
+
+; negative test
+define i1 @lt3_u8(i8 %0) {
+; CHECK-LABEL: lt3_u8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    and w8, w0, #0xff
+; CHECK-NEXT:    cmp w8, #3
+; CHECK-NEXT:    cset w0, lo
+; CHECK-NEXT:    ret
+  %2 = icmp ult i8 %0, 3
+  ret i1 %2
+}
+
+; negative test
+define i1 @lt3_u32(i32 %0) {
+; CHECK-LABEL: lt3_u32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    cmp w0, #3
+; CHECK-NEXT:    cset w0, lo
+; CHECK-NEXT:    ret
+  %2 = icmp ult i32 %0, 3
+  ret i1 %2
+}
+
+; negative test
+define i1 @lt3_u64(i64 %0) {
+; CHECK-LABEL: lt3_u64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    cmp x0, #3
+; CHECK-NEXT:    cset w0, lo
+; CHECK-NEXT:    ret
+  %2 = icmp ult i64 %0, 3
+  ret i1 %2
+}
+
+; negative test
+define i32 @lt32_u16_multiple_use(i32 %0) {
+; CHECK-LABEL: lt32_u16_multiple_use:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #21 // =0x15
+; CHECK-NEXT:    mov w9, #10 // =0xa
+; CHECK-NEXT:    and w8, w0, w8
+; CHECK-NEXT:    cmp w8, #16
+; CHECK-NEXT:    orr w8, w8, w9
+; CHECK-NEXT:    cset w10, lo
+; CHECK-NEXT:    mul w0, w8, w10
+; CHECK-NEXT:    ret
+  %2 = and i32 %0, 21
+  %3 = icmp ult i32 %2, 16
+  %4 = add i32 %2, 10
+  %5 = zext i1 %3 to i32
+  %6 = mul i32 %4, %5
+  ret i32 %6
+}