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[X86] Fold some (truncate (srl (add X, C1), C2)) patterns to (add (truncate (srl X, C2)), C1') (#126448)
Addresses the poor codegen identified in #123239 and a few extra cases. This transformation is correct for `eq` (https://alive2.llvm.org/ce/z/qZhwtT), `ne` (https://alive2.llvm.org/ce/z/6gsmNz), `ult` (https://alive2.llvm.org/ce/z/xip_td) and `ugt` (https://alive2.llvm.org/ce/z/39XQkX). Fixes #123239
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‎llvm/lib/Target/X86/X86ISelLowering.cpp

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@@ -53697,6 +53697,41 @@ static SDValue combineLRINT_LLRINT(SDNode *N, SelectionDAG &DAG,
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DAG.getUNDEF(SrcVT)));
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}
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// Attempt to fold some (truncate (srl (add X, C1), C2)) patterns to
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// (add (truncate (srl X, C2)), C1'). C1' will be smaller than C1 so we are able
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// to avoid generating code with MOVABS and large constants in certain cases.
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static SDValue combinei64TruncSrlAdd(SDValue N, EVT VT, SelectionDAG &DAG,
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const SDLoc &DL) {
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using namespace llvm::SDPatternMatch;
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SDValue AddLhs;
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APInt AddConst, SrlConst;
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if (VT != MVT::i32 ||
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!sd_match(N, m_AllOf(m_SpecificVT(MVT::i64),
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m_Srl(m_OneUse(m_Add(m_Value(AddLhs),
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m_ConstInt(AddConst))),
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m_ConstInt(SrlConst)))))
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return SDValue();
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if (SrlConst.ule(31) || AddConst.lshr(SrlConst).shl(SrlConst) != AddConst)
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return SDValue();
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SDValue AddLHSSrl =
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DAG.getNode(ISD::SRL, DL, MVT::i64, AddLhs, N.getOperand(1));
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SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, VT, AddLHSSrl);
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APInt NewAddConstVal =
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(~((~AddConst).lshr(SrlConst))).trunc(VT.getSizeInBits());
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SDValue NewAddConst = DAG.getConstant(NewAddConstVal, DL, VT);
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SDValue NewAddNode = DAG.getNode(ISD::ADD, DL, VT, Trunc, NewAddConst);
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APInt CleanupSizeConstVal = (SrlConst - 32).zextOrTrunc(VT.getSizeInBits());
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EVT CleanUpVT =
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EVT::getIntegerVT(*DAG.getContext(), CleanupSizeConstVal.getZExtValue());
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SDValue CleanUp = DAG.getAnyExtOrTrunc(NewAddNode, DL, CleanUpVT);
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return DAG.getAnyExtOrTrunc(CleanUp, DL, VT);
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}
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/// Attempt to pre-truncate inputs to arithmetic ops if it will simplify
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/// the codegen.
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/// e.g. TRUNC( BINOP( X, Y ) ) --> BINOP( TRUNC( X ), TRUNC( Y ) )
@@ -53742,6 +53777,9 @@ static SDValue combineTruncatedArithmetic(SDNode *N, SelectionDAG &DAG,
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if (!Src.hasOneUse())
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return SDValue();
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if (SDValue R = combinei64TruncSrlAdd(Src, VT, DAG, DL))
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return R;
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// Only support vector truncation for now.
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// TODO: i64 scalar math would benefit as well.
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if (!VT.isVector())

‎llvm/test/CodeGen/X86/combine-i64-trunc-srl-add.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefixes=X64
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; Test for https://github.com/llvm/llvm-project/issues/123239
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define i1 @test_ult_trunc_add(i64 %x) {
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; X64-LABEL: test_ult_trunc_add:
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; X64: # %bb.0:
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; X64-NEXT: shrq $48, %rdi
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; X64-NEXT: addl $-65522, %edi # imm = 0xFFFF000E
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; X64-NEXT: cmpl $3, %edi
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; X64-NEXT: setb %al
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; X64-NEXT: retq
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%add = add i64 %x, 3940649673949184
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%shr = lshr i64 %add, 48
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%conv = trunc i64 %shr to i32
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%res = icmp ult i32 %conv, 3
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ret i1 %res
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}
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define i1 @test_ult_add(i64 %x) {
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; X64-LABEL: test_ult_add:
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; X64: # %bb.0:
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; X64-NEXT: shrq $48, %rdi
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; X64-NEXT: addl $-65522, %edi # imm = 0xFFFF000E
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; X64-NEXT: cmpl $3, %edi
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; X64-NEXT: setb %al
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; X64-NEXT: retq
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%add = add i64 3940649673949184, %x
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%cmp = icmp ult i64 %add, 844424930131968
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ret i1 %cmp
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}
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define i1 @test_ugt_trunc_add(i64 %x) {
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; X64-LABEL: test_ugt_trunc_add:
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; X64: # %bb.0:
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; X64-NEXT: shrq $48, %rdi
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; X64-NEXT: addl $-65522, %edi # imm = 0xFFFF000E
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; X64-NEXT: cmpl $4, %edi
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; X64-NEXT: setae %al
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; X64-NEXT: retq
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%add = add i64 %x, 3940649673949184
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%shr = lshr i64 %add, 48
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%conv = trunc i64 %shr to i32
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%res = icmp ugt i32 %conv, 3
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ret i1 %res
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}
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define i1 @test_ugt_add(i64 %x) {
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; X64-LABEL: test_ugt_add:
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; X64: # %bb.0:
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; X64-NEXT: movabsq $3940649673949184, %rax # imm = 0xE000000000000
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; X64-NEXT: addq %rdi, %rax
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; X64-NEXT: movabsq $844424930131968, %rcx # imm = 0x3000000000000
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; X64-NEXT: cmpq %rcx, %rax
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; X64-NEXT: seta %al
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; X64-NEXT: retq
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%add = add i64 3940649673949184, %x
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%cmp = icmp ugt i64 %add, 844424930131968
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ret i1 %cmp
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}
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define i1 @test_eq_trunc_add(i64 %x) {
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; X64-LABEL: test_eq_trunc_add:
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; X64: # %bb.0:
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; X64-NEXT: shrq $48, %rdi
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; X64-NEXT: cmpl $65525, %edi # imm = 0xFFF5
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; X64-NEXT: sete %al
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; X64-NEXT: retq
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%add = add i64 %x, 3940649673949184
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%shr = lshr i64 %add, 48
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%conv = trunc i64 %shr to i32
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%res = icmp eq i32 %conv, 3
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ret i1 %res
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}
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define i1 @test_eq_add(i64 %x) {
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; X64-LABEL: test_eq_add:
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; X64: # %bb.0:
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; X64-NEXT: movabsq $-3096224743817216, %rax # imm = 0xFFF5000000000000
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; X64-NEXT: cmpq %rax, %rdi
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; X64-NEXT: sete %al
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; X64-NEXT: retq
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%add = add i64 3940649673949184, %x
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%cmp = icmp eq i64 %add, 844424930131968
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ret i1 %cmp
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}
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define i1 @test_ne_trunc_add(i64 %x) {
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; X64-LABEL: test_ne_trunc_add:
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; X64: # %bb.0:
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; X64-NEXT: shrq $48, %rdi
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; X64-NEXT: cmpl $65525, %edi # imm = 0xFFF5
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; X64-NEXT: setne %al
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; X64-NEXT: retq
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%add = add i64 %x, 3940649673949184
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%shr = lshr i64 %add, 48
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%conv = trunc i64 %shr to i32
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%res = icmp ne i32 %conv, 3
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ret i1 %res
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}
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define i1 @test_ne_add(i64 %x) {
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; X64-LABEL: test_ne_add:
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; X64: # %bb.0:
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; X64-NEXT: movabsq $-3096224743817216, %rax # imm = 0xFFF5000000000000
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; X64-NEXT: cmpq %rax, %rdi
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; X64-NEXT: setne %al
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; X64-NEXT: retq
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%add = add i64 3940649673949184, %x
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%cmp = icmp ne i64 %add, 844424930131968
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ret i1 %cmp
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}
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define i32 @test_trunc_add(i64 %x) {
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; X64-LABEL: test_trunc_add:
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; X64: # %bb.0:
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; X64-NEXT: shrq $48, %rdi
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; X64-NEXT: leal -65522(%rdi), %eax
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; X64-NEXT: retq
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%add = add i64 %x, 3940649673949184
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%shr = lshr i64 %add, 48
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%conv = trunc i64 %shr to i32
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ret i32 %conv
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}

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