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[AArch64] Add support for Neoverse-N3, Neoverse-V3 and Neoverse-V3AE
Neoverse-N3, Neoverse-V3 and Neoverse-V3AE are Armv9.2 AArch64 CPUs. Technical Reference Manual for Neoverse-N3: https://developer.arm.com/documentation/107997/latest/ Technical Reference Manual for Neoverse-V3: https://developer.arm.com/documentation/107734/latest/ Technical Reference Manual for Neoverse-V3AE: https://developer.arm.com/documentation/101595/latest/
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‎clang/docs/ReleaseNotes.rst

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@@ -633,6 +633,9 @@ Arm and AArch64 Support
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* Arm Cortex-A78AE (cortex-a78ae).
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* Arm Cortex-A520AE (cortex-a520ae).
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* Arm Cortex-A720AE (cortex-a720ae).
636+
* Arm Neoverse-N3 (neoverse-n3).
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* Arm Neoverse-V3 (neoverse-v3).
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* Arm Neoverse-V3AE (neoverse-v3ae).
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637640
Android Support
638641
^^^^^^^^^^^^^^^

‎clang/test/Driver/aarch64-mcpu.c

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@@ -64,10 +64,16 @@
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// NEOVERSE-V1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-v1"
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// RUN: %clang --target=aarch64 -mcpu=neoverse-v2 -### -c %s 2>&1 | FileCheck -check-prefix=NEOVERSE-V2 %s
6666
// NEOVERSE-V2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-v2"
67+
// RUN: %clang --target=aarch64 -mcpu=neoverse-v3 -### -c %s 2>&1 | FileCheck -check-prefix=NEOVERSE-V3 %s
68+
// NEOVERSE-V3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-v3"
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// RUN: %clang --target=aarch64 -mcpu=neoverse-v3ae -### -c %s 2>&1 | FileCheck -check-prefix=NEOVERSE-V3AE %s
70+
// NEOVERSE-V3AE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-v3ae"
6771
// RUN: %clang --target=aarch64 -mcpu=neoverse-n1 -### -c %s 2>&1 | FileCheck -check-prefix=NEOVERSE-N1 %s
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// NEOVERSE-N1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-n1"
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// RUN: %clang --target=aarch64 -mcpu=neoverse-n2 -### -c %s 2>&1 | FileCheck -check-prefix=NEOVERSE-N2 %s
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// NEOVERSE-N2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-n2"
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// RUN: %clang --target=aarch64 -mcpu=neoverse-n3 -### -c %s 2>&1 | FileCheck -check-prefix=NEOVERSE-N3 %s
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// NEOVERSE-N3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-n3"
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// RUN: %clang --target=aarch64 -mcpu=neoverse-512tvb -### -c %s 2>&1 | FileCheck -check-prefix=NEOVERSE-512TVB %s
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// NEOVERSE-512TVB: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-512tvb"
7379
// RUN: %clang --target=aarch64 -mcpu=cortex-a520 -### -c %s 2>&1 | FileCheck -check-prefix=CORTEX-A520 %s

‎clang/test/Misc/target-invalid-cpu-note.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,11 +5,11 @@
55

66
// RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix AARCH64
77
// AARCH64: error: unknown target CPU 'not-a-cpu'
8-
// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, cobalt-100, grace{{$}}
8+
// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, cobalt-100, grace{{$}}
99

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// RUN: not %clang_cc1 -triple arm64--- -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE_AARCH64
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// TUNE_AARCH64: error: unknown target CPU 'not-a-cpu'
12-
// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, cobalt-100, grace{{$}}
12+
// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, cobalt-100, grace{{$}}
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// RUN: not %clang_cc1 -triple i386--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix X86
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// X86: error: unknown target CPU 'not-a-cpu'

‎llvm/docs/ReleaseNotes.rst

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@@ -69,7 +69,8 @@ Changes to Interprocedural Optimizations
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Changes to the AArch64 Backend
7070
------------------------------
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72-
* Added support for Cortex-A78AE, Cortex-A520AE and Cortex-A720AE CPUs.
72+
* Added support for Cortex-A78AE, Cortex-A520AE, Cortex-A720AE,
73+
Neoverse-N3, Neoverse-V3 and Neoverse-V3AE CPUs.
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Changes to the AMDGPU Backend
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-----------------------------

‎llvm/include/llvm/TargetParser/AArch64TargetParser.h

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@@ -677,6 +677,13 @@ inline constexpr CpuInfo CpuInfos[] = {
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AArch64::AEK_FP16FML, AArch64::AEK_I8MM, AArch64::AEK_MTE,
678678
AArch64::AEK_SB, AArch64::AEK_SSBS, AArch64::AEK_SVE,
679679
AArch64::AEK_SVE2, AArch64::AEK_SVE2BITPERM})},
680+
{"neoverse-n3", ARMV9_2A,
681+
AArch64::ExtensionBitset({AArch64::AEK_MTE, AArch64::AEK_SSBS,
682+
AArch64::AEK_SB, AArch64::AEK_PREDRES,
683+
AArch64::AEK_FP16FML, AArch64::AEK_PAUTH,
684+
AArch64::AEK_FLAGM, AArch64::AEK_PERFMON,
685+
AArch64::AEK_RAND, AArch64::AEK_SVE2BITPERM,
686+
AArch64::AEK_PROFILE, AArch64::AEK_PERFMON})},
680687
{"neoverse-512tvb", ARMV8_4A,
681688
AArch64::ExtensionBitset(
682689
{AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_SHA3,
@@ -697,6 +704,20 @@ inline constexpr CpuInfo CpuInfos[] = {
697704
AArch64::AEK_FP16, AArch64::AEK_BF16, AArch64::AEK_RAND,
698705
AArch64::AEK_DOTPROD, AArch64::AEK_PROFILE, AArch64::AEK_SVE2BITPERM,
699706
AArch64::AEK_FP16FML, AArch64::AEK_I8MM, AArch64::AEK_MTE})},
707+
{"neoverse-v3", ARMV9_2A,
708+
AArch64::ExtensionBitset(
709+
{AArch64::AEK_PROFILE, AArch64::AEK_MTE, AArch64::AEK_SSBS,
710+
AArch64::AEK_SB, AArch64::AEK_PREDRES, AArch64::AEK_LS64,
711+
AArch64::AEK_BRBE, AArch64::AEK_PAUTH, AArch64::AEK_FLAGM,
712+
AArch64::AEK_PERFMON, AArch64::AEK_RAND, AArch64::AEK_SVE2BITPERM,
713+
AArch64::AEK_FP16FML})},
714+
{"neoverse-v3ae", ARMV9_2A,
715+
(AArch64::ExtensionBitset(
716+
{AArch64::AEK_PROFILE, AArch64::AEK_MTE, AArch64::AEK_SSBS,
717+
AArch64::AEK_SB, AArch64::AEK_PREDRES, AArch64::AEK_LS64,
718+
AArch64::AEK_BRBE, AArch64::AEK_PAUTH, AArch64::AEK_FLAGM,
719+
AArch64::AEK_PERFMON, AArch64::AEK_RAND, AArch64::AEK_SVE2BITPERM,
720+
AArch64::AEK_FP16FML}))},
700721
{"cyclone", ARMV8A,
701722
AArch64::ExtensionBitset(
702723
{AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_NONE})},

‎llvm/lib/Target/AArch64/AArch64Processors.td

Lines changed: 46 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -447,6 +447,16 @@ def TuneNeoverseN2 : SubtargetFeature<"neoversen2", "ARMProcFamily", "NeoverseN2
447447
FeatureEnableSelectOptimize,
448448
FeaturePredictableSelectIsExpensive]>;
449449

450+
def TuneNeoverseN3 : SubtargetFeature<"neoversen3", "ARMProcFamily", "NeoverseN3",
451+
"Neoverse N3 ARM processors", [
452+
FeatureFuseAES,
453+
FeaturePostRAScheduler,
454+
FeatureCmpBccFusion,
455+
FeatureALULSLFast,
456+
FeatureFuseAdrpAdd,
457+
FeatureEnableSelectOptimize,
458+
FeaturePredictableSelectIsExpensive]>;
459+
450460
def TuneNeoverse512TVB : SubtargetFeature<"neoverse512tvb", "ARMProcFamily", "Neoverse512TVB",
451461
"Neoverse 512-TVB ARM processors", [
452462
FeatureFuseAES,
@@ -476,6 +486,24 @@ def TuneNeoverseV2 : SubtargetFeature<"neoversev2", "ARMProcFamily", "NeoverseV2
476486
FeatureEnableSelectOptimize,
477487
FeaturePredictableSelectIsExpensive]>;
478488

489+
def TuneNeoverseV3 : SubtargetFeature<"neoversev3", "ARMProcFamily", "NeoverseV3",
490+
"Neoverse V3 ARM processors", [
491+
FeatureFuseAES,
492+
FeatureALULSLFast,
493+
FeatureFuseAdrpAdd,
494+
FeaturePostRAScheduler,
495+
FeatureEnableSelectOptimize,
496+
FeaturePredictableSelectIsExpensive]>;
497+
498+
def TuneNeoverseV3AE : SubtargetFeature<"neoversev3AE", "ARMProcFamily", "NeoverseV3",
499+
"Neoverse V3AE ARM processors", [
500+
FeatureFuseAES,
501+
FeatureALULSLFast,
502+
FeatureFuseAdrpAdd,
503+
FeaturePostRAScheduler,
504+
FeatureEnableSelectOptimize,
505+
FeaturePredictableSelectIsExpensive]>;
506+
479507
def TuneSaphira : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira",
480508
"Qualcomm Saphira processors", [
481509
FeaturePostRAScheduler,
@@ -715,6 +743,10 @@ def ProcessorFeatures {
715743
FeatureMatMulInt8, FeatureMTE, FeatureSVE2,
716744
FeatureSVE2BitPerm, FeatureTRBE,
717745
FeaturePerfMon];
746+
list<SubtargetFeature> NeoverseN3 = [HasV9_2aOps, FeatureETE, FeatureFP16FML,
747+
FeatureFullFP16, FeatureMTE, FeaturePerfMon,
748+
FeatureRandGen, FeatureSPE, FeatureSPE_EEF,
749+
FeatureSVE2BitPerm];
718750
list<SubtargetFeature> Neoverse512TVB = [HasV8_4aOps, FeatureBF16, FeatureCacheDeepPersist,
719751
FeatureCrypto, FeatureFPARMv8, FeatureFP16FML,
720752
FeatureFullFP16, FeatureMatMulInt8, FeatureNEON,
@@ -729,6 +761,14 @@ def ProcessorFeatures {
729761
FeaturePerfMon, FeatureETE, FeatureMatMulInt8,
730762
FeatureNEON, FeatureSVE2BitPerm, FeatureFP16FML,
731763
FeatureMTE, FeatureRandGen];
764+
list<SubtargetFeature> NeoverseV3 = [HasV9_2aOps, FeatureETE, FeatureFP16FML,
765+
FeatureFullFP16, FeatureLS64, FeatureMTE,
766+
FeaturePerfMon, FeatureRandGen, FeatureSPE,
767+
FeatureSPE_EEF, FeatureSVE2BitPerm, FeatureBRBE];
768+
list<SubtargetFeature> NeoverseV3AE = [HasV9_2aOps, FeatureETE, FeatureFP16FML,
769+
FeatureFullFP16, FeatureLS64, FeatureMTE,
770+
FeaturePerfMon, FeatureRandGen, FeatureSPE,
771+
FeatureSPE_EEF, FeatureSVE2BitPerm, FeatureBRBE];
732772
list<SubtargetFeature> Saphira = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8,
733773
FeatureNEON, FeatureSPE, FeaturePerfMon];
734774
list<SubtargetFeature> ThunderX = [HasV8_0aOps, FeatureCRC, FeatureCrypto,
@@ -831,12 +871,18 @@ def : ProcessorModel<"neoverse-n1", NeoverseN1Model,
831871
ProcessorFeatures.NeoverseN1, [TuneNeoverseN1]>;
832872
def : ProcessorModel<"neoverse-n2", NeoverseN2Model,
833873
ProcessorFeatures.NeoverseN2, [TuneNeoverseN2]>;
874+
def : ProcessorModel<"neoverse-n3", NeoverseN2Model,
875+
ProcessorFeatures.NeoverseN3, [TuneNeoverseN3]>;
834876
def : ProcessorModel<"neoverse-512tvb", NeoverseV1Model,
835877
ProcessorFeatures.Neoverse512TVB, [TuneNeoverse512TVB]>;
836878
def : ProcessorModel<"neoverse-v1", NeoverseV1Model,
837879
ProcessorFeatures.NeoverseV1, [TuneNeoverseV1]>;
838880
def : ProcessorModel<"neoverse-v2", NeoverseV2Model,
839881
ProcessorFeatures.NeoverseV2, [TuneNeoverseV2]>;
882+
def : ProcessorModel<"neoverse-v3", NeoverseV2Model,
883+
ProcessorFeatures.NeoverseV3, [TuneNeoverseV3]>;
884+
def : ProcessorModel<"neoverse-v3ae", NeoverseV2Model,
885+
ProcessorFeatures.NeoverseV3AE, [TuneNeoverseV3AE]>;
840886
def : ProcessorModel<"exynos-m3", ExynosM3Model, ProcessorFeatures.ExynosM3,
841887
[TuneExynosM3]>;
842888
def : ProcessorModel<"exynos-m4", ExynosM4Model, ProcessorFeatures.ExynosM4,

‎llvm/lib/Target/AArch64/AArch64Subtarget.cpp

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Original file line numberDiff line numberDiff line change
@@ -234,7 +234,9 @@ void AArch64Subtarget::initializeProperties(bool HasMinSize) {
234234
MaxBytesForLoopAlignment = 16;
235235
break;
236236
case NeoverseN2:
237+
case NeoverseN3:
237238
case NeoverseV2:
239+
case NeoverseV3:
238240
PrefFunctionAlignment = Align(16);
239241
PrefLoopAlignment = Align(32);
240242
MaxBytesForLoopAlignment = 16;

‎llvm/lib/TargetParser/Host.cpp

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Original file line numberDiff line numberDiff line change
@@ -245,8 +245,11 @@ StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) {
245245
.Case("0xd4a", "neoverse-e1")
246246
.Case("0xd0c", "neoverse-n1")
247247
.Case("0xd49", "neoverse-n2")
248+
.Case("0xd8e", "neoverse-n3")
248249
.Case("0xd40", "neoverse-v1")
249250
.Case("0xd4f", "neoverse-v2")
251+
.Case("0xd84", "neoverse-v3")
252+
.Case("0xd83", "neoverse-v3ae")
250253
.Default("generic");
251254
}
252255

‎llvm/unittests/TargetParser/TargetParserTest.cpp

Lines changed: 57 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1345,6 +1345,44 @@ INSTANTIATE_TEST_SUITE_P(
13451345
AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
13461346
AArch64::AEK_PAUTH}),
13471347
"9-A"),
1348+
ARMCPUTestParams<AArch64::ExtensionBitset>(
1349+
"neoverse-v3", "armv9.2-a", "neon-fp-armv8",
1350+
AArch64::ExtensionBitset(
1351+
{AArch64::AEK_BF16, AArch64::AEK_I8MM,
1352+
AArch64::AEK_SVE, AArch64::AEK_SVE2,
1353+
AArch64::AEK_FP16, AArch64::AEK_DOTPROD,
1354+
AArch64::AEK_LSE, AArch64::AEK_RDM,
1355+
AArch64::AEK_SIMD, AArch64::AEK_RCPC,
1356+
AArch64::AEK_RAS, AArch64::AEK_CRC,
1357+
AArch64::AEK_FP, AArch64::AEK_PROFILE,
1358+
AArch64::AEK_MTE, AArch64::AEK_SSBS,
1359+
AArch64::AEK_SB, AArch64::AEK_PREDRES,
1360+
AArch64::AEK_LS64, AArch64::AEK_BRBE,
1361+
AArch64::AEK_PAUTH, AArch64::AEK_FLAGM,
1362+
AArch64::AEK_PERFMON, AArch64::AEK_RAND,
1363+
AArch64::AEK_SVE2BITPERM, AArch64::AEK_FP16FML,
1364+
AArch64::AEK_PROFILE, AArch64::AEK_JSCVT,
1365+
AArch64::AEK_FCMA}),
1366+
"9.2-A"),
1367+
ARMCPUTestParams<AArch64::ExtensionBitset>(
1368+
"neoverse-v3ae", "armv9.2-a", "neon-fp-armv8",
1369+
AArch64::ExtensionBitset(
1370+
{AArch64::AEK_BF16, AArch64::AEK_I8MM,
1371+
AArch64::AEK_SVE, AArch64::AEK_SVE2,
1372+
AArch64::AEK_FP16, AArch64::AEK_DOTPROD,
1373+
AArch64::AEK_LSE, AArch64::AEK_RDM,
1374+
AArch64::AEK_SIMD, AArch64::AEK_RCPC,
1375+
AArch64::AEK_RAS, AArch64::AEK_CRC,
1376+
AArch64::AEK_FP, AArch64::AEK_PROFILE,
1377+
AArch64::AEK_MTE, AArch64::AEK_SSBS,
1378+
AArch64::AEK_SB, AArch64::AEK_PREDRES,
1379+
AArch64::AEK_LS64, AArch64::AEK_BRBE,
1380+
AArch64::AEK_PAUTH, AArch64::AEK_FLAGM,
1381+
AArch64::AEK_PERFMON, AArch64::AEK_RAND,
1382+
AArch64::AEK_SVE2BITPERM, AArch64::AEK_FP16FML,
1383+
AArch64::AEK_PROFILE, AArch64::AEK_JSCVT,
1384+
AArch64::AEK_FCMA}),
1385+
"9.2-A"),
13481386
ARMCPUTestParams<AArch64::ExtensionBitset>(
13491387
"cortex-r82", "armv8-r", "crypto-neon-fp-armv8",
13501388
AArch64::ExtensionBitset(
@@ -1636,6 +1674,24 @@ INSTANTIATE_TEST_SUITE_P(
16361674
AArch64::AEK_FCMA, AArch64::AEK_PAUTH,
16371675
AArch64::AEK_FP16FML}),
16381676
"9-A"),
1677+
ARMCPUTestParams<AArch64::ExtensionBitset>(
1678+
"neoverse-n3", "armv9.2-a", "neon-fp-armv8",
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AArch64::ExtensionBitset(
1680+
{AArch64::AEK_BF16, AArch64::AEK_I8MM,
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AArch64::AEK_SVE, AArch64::AEK_SVE2,
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AArch64::AEK_FP16, AArch64::AEK_DOTPROD,
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AArch64::AEK_LSE, AArch64::AEK_RDM,
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AArch64::AEK_SIMD, AArch64::AEK_RCPC,
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AArch64::AEK_RAS, AArch64::AEK_CRC,
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AArch64::AEK_FP, AArch64::AEK_PROFILE,
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AArch64::AEK_MTE, AArch64::AEK_SSBS,
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AArch64::AEK_SB, AArch64::AEK_PREDRES,
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AArch64::AEK_FCMA, AArch64::AEK_PAUTH,
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AArch64::AEK_FLAGM, AArch64::AEK_PERFMON,
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AArch64::AEK_RAND, AArch64::AEK_SVE2BITPERM,
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AArch64::AEK_FP16FML, AArch64::AEK_PROFILE,
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AArch64::AEK_JSCVT}),
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"9.2-A"),
16391695
ARMCPUTestParams<AArch64::ExtensionBitset>(
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"ampere1", "armv8.6-a", "crypto-neon-fp-armv8",
16411697
AArch64::ExtensionBitset(
@@ -1750,7 +1806,7 @@ INSTANTIATE_TEST_SUITE_P(
17501806
ARMCPUTestParams<AArch64::ExtensionBitset>::PrintToStringParamName);
17511807

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// Note: number of CPUs includes aliases.
1753-
static constexpr unsigned NumAArch64CPUArchs = 72;
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static constexpr unsigned NumAArch64CPUArchs = 75;
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TEST(TargetParserTest, testAArch64CPUArchList) {
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SmallVector<StringRef, NumAArch64CPUArchs> List;

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