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michaelmaitlandmichaelmaitland
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[RISCV][RegAlloc] Add getCSRFirstUseCost for RISC-V (#131349)
This is based off of 63efd8e. The following table shows the percent change to the dynamic instruction count when the function in this patch returns 0 (default) versus other values. | benchmark | % speedup 1 over 0 | % speedup 4 over 0 | % speedup 16 over 0 | % speedup 64 over 0 | % speedup 128 over 0 | | --------------- | ---------------------- | --------------------- | --------------------- | -------------------- | -------------------- | | 500.perlbench_r | 0.001018570165 | 0.001049508358 | 0.001001106529 | 0.03382582818 | 0.03395354577 | | 502.gcc_r | 0.02850551412 | 0.02170512371 | 0.01453021263 | 0.06011008637 | 0.1215691521 | | 505.mcf_r | -0.00009506373338 | -0.00009090057642 | -0.0000860991497 | -0.00005027849766 | 0.00001251173791 | | 520.omnetpp_r | 0.2958940288 | 0.2959715925 | 0.2961141505 | 0.2959823497 | 0.2963124341 | | 523.xalancbmk_r | -0.0327074721 | -0.01037021046 | -0.3226810542 | 0.02127133714 | 0.02765388389 | | 525.x264_r | 0.0000001381714403 | -0.00000007041540345 | -0.00000002156399465 | 0.0000002108993364 | 0.0000002463382874 | | 531.deepsjeng_r | 0.00000000339777238 | 0.000000003874652714 | 0.000000003636212547 | 0.000000003874652714 | 0.000000003159332213 | | 541.leela_r | 0.0009186059953 | -0.000424159199 | 0.0004984456879 | 0.274948447 | 0.8135521414 | | 557.xz_r | -0.000000003547118854 | -0.00004896449559 | -0.00004910691576 | -0.0000491109983 | -0.00004895599589 | | geomean | 0.03265937388 | 0.03424232324 | -0.00107917442 | 0.07629116165 | 0.1439913192 | The following table shows the percent change to the runtime when the function in this patch returns 0 (default) versus other values. | benchmark | % speedup 1 over 0 | % speedup 4 over 0 | % speedup 16 over 0 | % speedup 64 over 0 | %speedup 128 over 0 | | --------------- | ------------------ | ------------------ | ------------------- | ------------------- | ------------------- | | 500.perlbench_r | 0.1722356761 | 0.2269681109 | 0.2596825578 | 0.361573851 | 1.15041305 | | 502.gcc_r | -0.548415855 | -0.06187002799 | -0.5553684674 | -0.8876686237 | -0.4668665535 | | 505.mcf_r | -0.8786414258 | -0.4150938441 | -1.035517726 | -0.1860770377 | -0.01904825648 | | 520.omnetpp_r | 0.4130256072 | 0.6595976188 | 0.897332171 | 0.6252625622 | 0.3869467278 | | 523.xalancbmk_r | 1.318132014 | -0.003927574 | 1.025962975 | 1.090320253 | -0.789206202 | | 525.x264_r | -0.03112871796 | -0.00167557587 | 0.06932423155 | -0.1919840015 | -0.1203585732 | | 531.deepsjeng_r | -0.259516072 | -0.01973455652 | -0.2723227894 | -0.005417022257 | -0.02222388177 | | 541.leela_r | -0.3497178495 | -0.3510447393 | 0.1274508001 | 0.6485542452 | 0.2880651727 | | 557.xz_r | 0.7683565263 | -0.2197509447 | -0.0431183874 | 0.07518130872 | 0.5236853039 | | geomean | 0.06506952742 | -0.0211865386 | 0.05072694648 | 0.1684530637 | 0.1020533557 | I chose to set the value to 5 on RISC-V because it has improvement to both the dynamic IC and the runtime and because it showed good results empirically and had a similar effect as setting it to higher numbers. I looked at some diff and it seems like this patch leads to two things: 1. Less spilling -- not spilling the CSR led to better register allocation and helped us avoid spills down the line 2. Avoid spilling CSR but spill more on paths that static heuristics estimate as cold.
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lines changed

‎llvm/lib/CodeGen/RegAllocGreedy.cpp

+5-3
Original file line numberDiff line numberDiff line change
@@ -2375,10 +2375,12 @@ void RAGreedy::aboutToRemoveInterval(const LiveInterval &LI) {
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}
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void RAGreedy::initializeCSRCost() {
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// We use the larger one out of the command-line option and the value report
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// by TRI.
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// We use the command-line option if it is explicitly set, otherwise use the
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// larger one out of the command-line option and the value reported by TRI.
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CSRCost = BlockFrequency(
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std::max((unsigned)CSRFirstTimeCost, TRI->getCSRFirstUseCost()));
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CSRFirstTimeCost.getNumOccurrences()
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? CSRFirstTimeCost
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: std::max((unsigned)CSRFirstTimeCost, TRI->getCSRFirstUseCost()));
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if (!CSRCost.getFrequency())
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return;
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‎llvm/lib/Target/RISCV/RISCVRegisterInfo.h

+7
Original file line numberDiff line numberDiff line change
@@ -61,6 +61,13 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
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const uint32_t *getCallPreservedMask(const MachineFunction &MF,
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CallingConv::ID) const override;
6363

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unsigned getCSRFirstUseCost() const override {
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// The cost will be compared against BlockFrequency where entry has the
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// value of 1 << 14. A value of 5 will choose to spill or split cold
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// path instead of using a callee-saved register.
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return 5;
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}
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const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
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const MCPhysReg *getIPRACSRegs(const MachineFunction *MF) const override;

‎llvm/test/CodeGen/RISCV/csr-first-use-cost.ll

+107
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,107 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=riscv64 -regalloc-csr-first-time-cost=0 < %s | FileCheck %s -check-prefix=ZERO-COST
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; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=DEFAULT-COST
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define fastcc void @Perl_sv_setnv(i8 %c, ptr %.str.54.3682) nounwind {
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; ZERO-COST-LABEL: Perl_sv_setnv:
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; ZERO-COST: # %bb.0: # %entry
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; ZERO-COST-NEXT: addi sp, sp, -32
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; ZERO-COST-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
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; ZERO-COST-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
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; ZERO-COST-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
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; ZERO-COST-NEXT: andi a0, a0, 255
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; ZERO-COST-NEXT: li a2, 2
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; ZERO-COST-NEXT: blt a2, a0, .LBB0_3
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; ZERO-COST-NEXT: # %bb.1: # %entry
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; ZERO-COST-NEXT: beqz a0, .LBB0_4
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; ZERO-COST-NEXT: # %bb.2: # %entry
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; ZERO-COST-NEXT: mv s0, a1
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; ZERO-COST-NEXT: li a1, 1
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; ZERO-COST-NEXT: beq a0, a1, .LBB0_6
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; ZERO-COST-NEXT: j .LBB0_7
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; ZERO-COST-NEXT: .LBB0_3: # %entry
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; ZERO-COST-NEXT: li a2, 3
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; ZERO-COST-NEXT: bne a0, a2, .LBB0_5
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; ZERO-COST-NEXT: .LBB0_4: # %sw.bb3
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; ZERO-COST-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
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; ZERO-COST-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
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; ZERO-COST-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
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; ZERO-COST-NEXT: addi sp, sp, 32
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; ZERO-COST-NEXT: ret
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; ZERO-COST-NEXT: .LBB0_5: # %entry
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; ZERO-COST-NEXT: mv s0, a1
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; ZERO-COST-NEXT: li a1, 12
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; ZERO-COST-NEXT: bne a0, a1, .LBB0_7
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; ZERO-COST-NEXT: .LBB0_6: # %sw.bb34.i
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; ZERO-COST-NEXT: li s0, 0
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; ZERO-COST-NEXT: .LBB0_7: # %Perl_sv_reftype.exit
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; ZERO-COST-NEXT: li s1, 0
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; ZERO-COST-NEXT: li a0, 0
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; ZERO-COST-NEXT: li a1, 0
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; ZERO-COST-NEXT: jalr s1
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; ZERO-COST-NEXT: li a0, 0
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; ZERO-COST-NEXT: mv a1, s0
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; ZERO-COST-NEXT: li a2, 0
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; ZERO-COST-NEXT: jalr s1
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;
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; DEFAULT-COST-LABEL: Perl_sv_setnv:
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; DEFAULT-COST: # %bb.0: # %entry
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; DEFAULT-COST-NEXT: addi sp, sp, -32
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; DEFAULT-COST-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
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; DEFAULT-COST-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
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; DEFAULT-COST-NEXT: andi a0, a0, 255
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; DEFAULT-COST-NEXT: li a2, 2
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; DEFAULT-COST-NEXT: blt a2, a0, .LBB0_3
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; DEFAULT-COST-NEXT: # %bb.1: # %entry
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; DEFAULT-COST-NEXT: beqz a0, .LBB0_4
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; DEFAULT-COST-NEXT: # %bb.2: # %entry
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; DEFAULT-COST-NEXT: sd a1, 8(sp) # 8-byte Folded Spill
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; DEFAULT-COST-NEXT: li a1, 1
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; DEFAULT-COST-NEXT: beq a0, a1, .LBB0_6
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; DEFAULT-COST-NEXT: j .LBB0_7
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; DEFAULT-COST-NEXT: .LBB0_3: # %entry
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; DEFAULT-COST-NEXT: li a2, 3
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; DEFAULT-COST-NEXT: bne a0, a2, .LBB0_5
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; DEFAULT-COST-NEXT: .LBB0_4: # %sw.bb3
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; DEFAULT-COST-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
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; DEFAULT-COST-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
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; DEFAULT-COST-NEXT: addi sp, sp, 32
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; DEFAULT-COST-NEXT: ret
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; DEFAULT-COST-NEXT: .LBB0_5: # %entry
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; DEFAULT-COST-NEXT: sd a1, 8(sp) # 8-byte Folded Spill
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; DEFAULT-COST-NEXT: li a1, 12
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; DEFAULT-COST-NEXT: bne a0, a1, .LBB0_7
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; DEFAULT-COST-NEXT: .LBB0_6: # %sw.bb34.i
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; DEFAULT-COST-NEXT: sd zero, 8(sp) # 8-byte Folded Spill
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; DEFAULT-COST-NEXT: .LBB0_7: # %Perl_sv_reftype.exit
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; DEFAULT-COST-NEXT: li s0, 0
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; DEFAULT-COST-NEXT: li a0, 0
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; DEFAULT-COST-NEXT: li a1, 0
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; DEFAULT-COST-NEXT: jalr s0
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; DEFAULT-COST-NEXT: li a0, 0
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; DEFAULT-COST-NEXT: ld a1, 8(sp) # 8-byte Folded Reload
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; DEFAULT-COST-NEXT: li a2, 0
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; DEFAULT-COST-NEXT: jalr s0
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entry:
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switch i8 %c, label %Perl_sv_reftype.exit [
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i8 1, label %sw.bb4
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i8 12, label %sw.bb34.i
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i8 3, label %sw.bb3
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i8 0, label %sw.bb3
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]
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sw.bb3: ; preds = %entry, %entry
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ret void
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sw.bb4: ; preds = %entry
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br label %Perl_sv_reftype.exit
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sw.bb34.i: ; preds = %entry
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br label %Perl_sv_reftype.exit
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Perl_sv_reftype.exit: ; preds = %sw.bb34.i, %sw.bb4, %entry
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%retval.0.i = phi ptr [ null, %sw.bb34.i ], [ null, %sw.bb4 ], [ %.str.54.3682, %entry ]
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%call17 = tail call fastcc i64 null(ptr null, i32 0)
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tail call void (ptr, ...) null(ptr null, ptr %retval.0.i, ptr null)
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unreachable
107+
}

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