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DAG: Expose all MMO flags in getTgtMemIntrinsic
Rather than adding more bits to express every MMO flag you could want, just directly use the MMO flags. Also fixes using a bunch of bool arguments to getMemIntrinsicNode. On AMDGPU, buffer and image intrinsics should always have MODereferencable set, but currently there is no way to do that directly during the initial intrinsic lowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320746 91177308-0d34-0410-b5e6-96231b3b80d8
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12 files changed

+82
-154
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12 files changed

+82
-154
lines changed

‎include/llvm/CodeGen/SelectionDAG.h

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -988,11 +988,14 @@ class SelectionDAG {
988988
/// result and takes a list of operands. Opcode may be INTRINSIC_VOID,
989989
/// INTRINSIC_W_CHAIN, or a target-specific opcode with a value not
990990
/// less than FIRST_TARGET_MEMORY_OPCODE.
991-
SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList,
992-
ArrayRef<SDValue> Ops, EVT MemVT,
993-
MachinePointerInfo PtrInfo, unsigned Align = 0,
994-
bool Vol = false, bool ReadMem = true,
995-
bool WriteMem = true, unsigned Size = 0);
991+
SDValue getMemIntrinsicNode(
992+
unsigned Opcode, const SDLoc &dl, SDVTList VTList,
993+
ArrayRef<SDValue> Ops, EVT MemVT,
994+
MachinePointerInfo PtrInfo,
995+
unsigned Align = 0,
996+
MachineMemOperand::Flags Flags
997+
= MachineMemOperand::MOLoad | MachineMemOperand::MOStore,
998+
unsigned Size = 0);
996999

9971000
SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList,
9981001
ArrayRef<SDValue> Ops, EVT MemVT,

‎include/llvm/CodeGen/TargetLowering.h

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -707,10 +707,8 @@ class TargetLoweringBase {
707707
unsigned size = 0; // the size of the memory location
708708
// (taken from memVT if zero)
709709
unsigned align = 1; // alignment
710-
bool vol = false; // is volatile?
711-
bool readMem = false; // reads memory?
712-
bool writeMem = false; // writes memory?
713710

711+
MachineMemOperand::Flags flags = MachineMemOperand::MONone;
714712
IntrinsicInfo() = default;
715713
};
716714

‎lib/CodeGen/GlobalISel/IRTranslator.cpp

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -852,13 +852,9 @@ bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) {
852852
TargetLowering::IntrinsicInfo Info;
853853
// TODO: Add a GlobalISel version of getTgtMemIntrinsic.
854854
if (TLI.getTgtMemIntrinsic(Info, CI, ID)) {
855-
MachineMemOperand::Flags Flags =
856-
Info.vol ? MachineMemOperand::MOVolatile : MachineMemOperand::MONone;
857-
Flags |=
858-
Info.readMem ? MachineMemOperand::MOLoad : MachineMemOperand::MOStore;
859855
uint64_t Size = Info.memVT.getStoreSize();
860856
MIB.addMemOperand(MF->getMachineMemOperand(MachinePointerInfo(Info.ptrVal),
861-
Flags, Size, Info.align));
857+
Info.flags, Size, Info.align));
862858
}
863859

864860
return true;

‎lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 4 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -5777,21 +5777,15 @@ SDValue SelectionDAG::getMergeValues(ArrayRef<SDValue> Ops, const SDLoc &dl) {
57775777

57785778
SDValue SelectionDAG::getMemIntrinsicNode(
57795779
unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef<SDValue> Ops,
5780-
EVT MemVT, MachinePointerInfo PtrInfo, unsigned Align, bool Vol,
5781-
bool ReadMem, bool WriteMem, unsigned Size) {
5780+
EVT MemVT, MachinePointerInfo PtrInfo, unsigned Align,
5781+
MachineMemOperand::Flags Flags, unsigned Size) {
57825782
if (Align == 0) // Ensure that codegen never sees alignment 0
57835783
Align = getEVTAlignment(MemVT);
57845784

5785-
MachineFunction &MF = getMachineFunction();
5786-
auto Flags = MachineMemOperand::MONone;
5787-
if (WriteMem)
5788-
Flags |= MachineMemOperand::MOStore;
5789-
if (ReadMem)
5790-
Flags |= MachineMemOperand::MOLoad;
5791-
if (Vol)
5792-
Flags |= MachineMemOperand::MOVolatile;
57935785
if (!Size)
57945786
Size = MemVT.getStoreSize();
5787+
5788+
MachineFunction &MF = getMachineFunction();
57955789
MachineMemOperand *MMO =
57965790
MF.getMachineMemOperand(PtrInfo, Flags, Size, Align);
57975791

‎lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Lines changed: 6 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -4240,11 +4240,10 @@ void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
42404240
SDValue Result;
42414241
if (IsTgtIntrinsic) {
42424242
// This is target intrinsic that touches memory
4243-
Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(),
4244-
VTs, Ops, Info.memVT,
4245-
MachinePointerInfo(Info.ptrVal, Info.offset),
4246-
Info.align, Info.vol,
4247-
Info.readMem, Info.writeMem, Info.size);
4243+
Result = DAG.getMemIntrinsicNode(Info.opc, getCurSDLoc(), VTs,
4244+
Ops, Info.memVT,
4245+
MachinePointerInfo(Info.ptrVal, Info.offset), Info.align,
4246+
Info.flags, Info.size);
42484247
} else if (!HasChain) {
42494248
Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurSDLoc(), VTs, Ops);
42504249
} else if (!I.getType()->isVoidTy()) {
@@ -5823,6 +5822,7 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
58235822
case Intrinsic::prefetch: {
58245823
SDValue Ops[5];
58255824
unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
5825+
auto Flags = rw == 0 ? MachineMemOperand::MOLoad :MachineMemOperand::MOStore;
58265826
Ops[0] = getRoot();
58275827
Ops[1] = getValue(I.getArgOperand(0));
58285828
Ops[2] = getValue(I.getArgOperand(1));
@@ -5833,9 +5833,7 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
58335833
EVT::getIntegerVT(*Context, 8),
58345834
MachinePointerInfo(I.getArgOperand(0)),
58355835
0, /* align */
5836-
false, /* volatile */
5837-
rw==0, /* read */
5838-
rw==1)); /* write */
5836+
Flags));
58395837
return nullptr;
58405838
}
58415839
case Intrinsic::lifetime_start:

‎lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 8 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -7393,9 +7393,8 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
73937393
Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
73947394
Info.offset = 0;
73957395
Info.align = 0;
7396-
Info.vol = false; // volatile loads with NEON intrinsics not supported
7397-
Info.readMem = true;
7398-
Info.writeMem = false;
7396+
// volatile loads with NEON intrinsics not supported
7397+
Info.flags = MachineMemOperand::MOLoad;
73997398
return true;
74007399
}
74017400
case Intrinsic::aarch64_neon_st2:
@@ -7420,9 +7419,8 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
74207419
Info.ptrVal = I.getArgOperand(I.getNumArgOperands() - 1);
74217420
Info.offset = 0;
74227421
Info.align = 0;
7423-
Info.vol = false; // volatile stores with NEON intrinsics not supported
7424-
Info.readMem = false;
7425-
Info.writeMem = true;
7422+
// volatile stores with NEON intrinsics not supported
7423+
Info.flags = MachineMemOperand::MOStore;
74267424
return true;
74277425
}
74287426
case Intrinsic::aarch64_ldaxr:
@@ -7433,9 +7431,7 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
74337431
Info.ptrVal = I.getArgOperand(0);
74347432
Info.offset = 0;
74357433
Info.align = DL.getABITypeAlignment(PtrTy->getElementType());
7436-
Info.vol = true;
7437-
Info.readMem = true;
7438-
Info.writeMem = false;
7434+
Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile;
74397435
return true;
74407436
}
74417437
case Intrinsic::aarch64_stlxr:
@@ -7446,9 +7442,7 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
74467442
Info.ptrVal = I.getArgOperand(1);
74477443
Info.offset = 0;
74487444
Info.align = DL.getABITypeAlignment(PtrTy->getElementType());
7449-
Info.vol = true;
7450-
Info.readMem = false;
7451-
Info.writeMem = true;
7445+
Info.flags = MachineMemOperand::MOStore | MachineMemOperand::MOVolatile;
74527446
return true;
74537447
}
74547448
case Intrinsic::aarch64_ldaxp:
@@ -7458,9 +7452,7 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
74587452
Info.ptrVal = I.getArgOperand(0);
74597453
Info.offset = 0;
74607454
Info.align = 16;
7461-
Info.vol = true;
7462-
Info.readMem = true;
7463-
Info.writeMem = false;
7455+
Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile;
74647456
return true;
74657457
case Intrinsic::aarch64_stlxp:
74667458
case Intrinsic::aarch64_stxp:
@@ -7469,9 +7461,7 @@ bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
74697461
Info.ptrVal = I.getArgOperand(2);
74707462
Info.offset = 0;
74717463
Info.align = 16;
7472-
Info.vol = true;
7473-
Info.readMem = false;
7474-
Info.writeMem = true;
7464+
Info.flags = MachineMemOperand::MOStore | MachineMemOperand::MOVolatile;
74757465
return true;
74767466
default:
74777467
break;

‎lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -566,11 +566,12 @@ bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
566566
Info.memVT = MVT::getVT(CI.getType());
567567
Info.ptrVal = CI.getOperand(0);
568568
Info.align = 0;
569+
Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
569570

570571
const ConstantInt *Vol = dyn_cast<ConstantInt>(CI.getOperand(4));
571-
Info.vol = !Vol || !Vol->isZero();
572-
Info.readMem = true;
573-
Info.writeMem = true;
572+
if (!Vol || !Vol->isZero())
573+
Info.flags |= MachineMemOperand::MOVolatile;
574+
574575
return true;
575576
}
576577
default:

‎lib/Target/ARM/ARMISelLowering.cpp

Lines changed: 8 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -13606,9 +13606,8 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
1360613606
Info.offset = 0;
1360713607
Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
1360813608
Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
13609-
Info.vol = false; // volatile loads with NEON intrinsics not supported
13610-
Info.readMem = true;
13611-
Info.writeMem = false;
13609+
// volatile loads with NEON intrinsics not supported
13610+
Info.flags = MachineMemOperand::MOLoad;
1361213611
return true;
1361313612
}
1361413613
case Intrinsic::arm_neon_vst1:
@@ -13633,9 +13632,8 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
1363313632
Info.offset = 0;
1363413633
Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
1363513634
Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
13636-
Info.vol = false; // volatile stores with NEON intrinsics not supported
13637-
Info.readMem = false;
13638-
Info.writeMem = true;
13635+
// volatile stores with NEON intrinsics not supported
13636+
Info.flags = MachineMemOperand::MOStore;
1363913637
return true;
1364013638
}
1364113639
case Intrinsic::arm_ldaex:
@@ -13647,9 +13645,7 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
1364713645
Info.ptrVal = I.getArgOperand(0);
1364813646
Info.offset = 0;
1364913647
Info.align = DL.getABITypeAlignment(PtrTy->getElementType());
13650-
Info.vol = true;
13651-
Info.readMem = true;
13652-
Info.writeMem = false;
13648+
Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile;
1365313649
return true;
1365413650
}
1365513651
case Intrinsic::arm_stlex:
@@ -13661,9 +13657,7 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
1366113657
Info.ptrVal = I.getArgOperand(1);
1366213658
Info.offset = 0;
1366313659
Info.align = DL.getABITypeAlignment(PtrTy->getElementType());
13664-
Info.vol = true;
13665-
Info.readMem = false;
13666-
Info.writeMem = true;
13660+
Info.flags = MachineMemOperand::MOStore | MachineMemOperand::MOVolatile;
1366713661
return true;
1366813662
}
1366913663
case Intrinsic::arm_stlexd:
@@ -13673,9 +13667,7 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
1367313667
Info.ptrVal = I.getArgOperand(2);
1367413668
Info.offset = 0;
1367513669
Info.align = 8;
13676-
Info.vol = true;
13677-
Info.readMem = false;
13678-
Info.writeMem = true;
13670+
Info.flags = MachineMemOperand::MOStore | MachineMemOperand::MOVolatile;
1367913671
return true;
1368013672

1368113673
case Intrinsic::arm_ldaexd:
@@ -13685,9 +13677,7 @@ bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
1368513677
Info.ptrVal = I.getArgOperand(0);
1368613678
Info.offset = 0;
1368713679
Info.align = 8;
13688-
Info.vol = true;
13689-
Info.readMem = true;
13690-
Info.writeMem = false;
13680+
Info.flags = MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile;
1369113681
return true;
1369213682

1369313683
default:

‎lib/Target/Hexagon/HexagonISelLowering.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2282,9 +2282,9 @@ bool HexagonTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
22822282
Info.ptrVal = I.getArgOperand(0);
22832283
Info.offset = 0;
22842284
Info.align = M.getDataLayout().getTypeAllocSizeInBits(VecTy) / 8;
2285-
Info.vol = true;
2286-
Info.readMem = true;
2287-
Info.writeMem = true;
2285+
Info.flags = MachineMemOperand::MOLoad |
2286+
MachineMemOperand::MOStore |
2287+
MachineMemOperand::MOVolatile;
22882288
return true;
22892289
}
22902290
default:

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