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[X86] Add WriteBitScan/WriteLZCNT/WriteTZCNT/WritePOPCNT scheduler classes (PR36881)
Give the bit count instructions their own scheduler classes instead of forcing them into existing classes. These were mostly overridden anyway, but I had to add in costs from Agner for silvermont and znver1 and the Fam16h SoG for btver2 (Jaguar). Differential Revision: https://reviews.llvm.org/D44879 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328566 91177308-0d34-0410-b5e6-96231b3b80d8
1 parent a9c6c33 commit 33b38a2

15 files changed

+18398
-18430
lines changed

‎lib/Target/X86/X86InstrInfo.td

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -1341,52 +1341,52 @@ let Defs = [EFLAGS] in {
13411341
def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
13421342
"bsf{w}\t{$src, $dst|$dst, $src}",
13431343
[(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))],
1344-
IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>;
1344+
IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteBitScan]>;
13451345
def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
13461346
"bsf{w}\t{$src, $dst|$dst, $src}",
13471347
[(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))],
1348-
IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>;
1348+
IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteBitScanLd]>;
13491349
def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
13501350
"bsf{l}\t{$src, $dst|$dst, $src}",
13511351
[(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))],
1352-
IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>;
1352+
IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteBitScan]>;
13531353
def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
13541354
"bsf{l}\t{$src, $dst|$dst, $src}",
13551355
[(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))],
1356-
IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>;
1356+
IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteBitScanLd]>;
13571357
def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
13581358
"bsf{q}\t{$src, $dst|$dst, $src}",
13591359
[(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))],
1360-
IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>;
1360+
IIC_BIT_SCAN_REG>, PS, Sched<[WriteBitScan]>;
13611361
def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
13621362
"bsf{q}\t{$src, $dst|$dst, $src}",
13631363
[(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))],
1364-
IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>;
1364+
IIC_BIT_SCAN_MEM>, PS, Sched<[WriteBitScanLd]>;
13651365

13661366
def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
13671367
"bsr{w}\t{$src, $dst|$dst, $src}",
13681368
[(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))],
1369-
IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>;
1369+
IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteBitScan]>;
13701370
def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
13711371
"bsr{w}\t{$src, $dst|$dst, $src}",
13721372
[(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))],
1373-
IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>;
1373+
IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteBitScanLd]>;
13741374
def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
13751375
"bsr{l}\t{$src, $dst|$dst, $src}",
13761376
[(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))],
1377-
IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>;
1377+
IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteBitScan]>;
13781378
def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
13791379
"bsr{l}\t{$src, $dst|$dst, $src}",
13801380
[(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))],
1381-
IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>;
1381+
IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteBitScanLd]>;
13821382
def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
13831383
"bsr{q}\t{$src, $dst|$dst, $src}",
13841384
[(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))],
1385-
IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>;
1385+
IIC_BIT_SCAN_REG>, PS, Sched<[WriteBitScan]>;
13861386
def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
13871387
"bsr{q}\t{$src, $dst|$dst, $src}",
13881388
[(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))],
1389-
IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>;
1389+
IIC_BIT_SCAN_MEM>, PS, Sched<[WriteBitScanLd]>;
13901390
} // Defs = [EFLAGS]
13911391

13921392
let SchedRW = [WriteMicrocoded] in {
@@ -2269,32 +2269,32 @@ let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
22692269
def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
22702270
"lzcnt{w}\t{$src, $dst|$dst, $src}",
22712271
[(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)],
2272-
IIC_LZCNT_RR>, XS, OpSize16, Sched<[WriteIMul]>;
2272+
IIC_LZCNT_RR>, XS, OpSize16, Sched<[WriteLZCNT]>;
22732273
def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
22742274
"lzcnt{w}\t{$src, $dst|$dst, $src}",
22752275
[(set GR16:$dst, (ctlz (loadi16 addr:$src))),
22762276
(implicit EFLAGS)], IIC_LZCNT_RM>, XS, OpSize16,
2277-
Sched<[WriteIMulLd]>;
2277+
Sched<[WriteLZCNTLd]>;
22782278

22792279
def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
22802280
"lzcnt{l}\t{$src, $dst|$dst, $src}",
22812281
[(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)],
2282-
IIC_LZCNT_RR>, XS, OpSize32, Sched<[WriteIMul]>;
2282+
IIC_LZCNT_RR>, XS, OpSize32, Sched<[WriteLZCNT]>;
22832283
def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
22842284
"lzcnt{l}\t{$src, $dst|$dst, $src}",
22852285
[(set GR32:$dst, (ctlz (loadi32 addr:$src))),
22862286
(implicit EFLAGS)], IIC_LZCNT_RM>, XS, OpSize32,
2287-
Sched<[WriteIMulLd]>;
2287+
Sched<[WriteLZCNTLd]>;
22882288

22892289
def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
22902290
"lzcnt{q}\t{$src, $dst|$dst, $src}",
22912291
[(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)],
2292-
IIC_LZCNT_RR>, XS, Sched<[WriteIMul]>;
2292+
IIC_LZCNT_RR>, XS, Sched<[WriteLZCNT]>;
22932293
def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
22942294
"lzcnt{q}\t{$src, $dst|$dst, $src}",
22952295
[(set GR64:$dst, (ctlz (loadi64 addr:$src))),
22962296
(implicit EFLAGS)], IIC_LZCNT_RM>, XS,
2297-
Sched<[WriteIMulLd]>;
2297+
Sched<[WriteLZCNTLd]>;
22982298
}
22992299

23002300
//===----------------------------------------------------------------------===//
@@ -2304,32 +2304,32 @@ let Predicates = [HasBMI], Defs = [EFLAGS] in {
23042304
def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
23052305
"tzcnt{w}\t{$src, $dst|$dst, $src}",
23062306
[(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)],
2307-
IIC_TZCNT_RR>, XS, OpSize16, Sched<[WriteIMul]>;
2307+
IIC_TZCNT_RR>, XS, OpSize16, Sched<[WriteTZCNT]>;
23082308
def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
23092309
"tzcnt{w}\t{$src, $dst|$dst, $src}",
23102310
[(set GR16:$dst, (cttz (loadi16 addr:$src))),
23112311
(implicit EFLAGS)], IIC_TZCNT_RM>, XS, OpSize16,
2312-
Sched<[WriteIMulLd]>;
2312+
Sched<[WriteTZCNTLd]>;
23132313

23142314
def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
23152315
"tzcnt{l}\t{$src, $dst|$dst, $src}",
23162316
[(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)],
2317-
IIC_TZCNT_RR>, XS, OpSize32, Sched<[WriteIMul]>;
2317+
IIC_TZCNT_RR>, XS, OpSize32, Sched<[WriteTZCNT]>;
23182318
def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
23192319
"tzcnt{l}\t{$src, $dst|$dst, $src}",
23202320
[(set GR32:$dst, (cttz (loadi32 addr:$src))),
23212321
(implicit EFLAGS)], IIC_TZCNT_RM>, XS, OpSize32,
2322-
Sched<[WriteIMulLd]>;
2322+
Sched<[WriteTZCNTLd]>;
23232323

23242324
def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
23252325
"tzcnt{q}\t{$src, $dst|$dst, $src}",
23262326
[(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)],
2327-
IIC_TZCNT_RR>, XS, Sched<[WriteIMul]>;
2327+
IIC_TZCNT_RR>, XS, Sched<[WriteTZCNT]>;
23282328
def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
23292329
"tzcnt{q}\t{$src, $dst|$dst, $src}",
23302330
[(set GR64:$dst, (cttz (loadi64 addr:$src))),
23312331
(implicit EFLAGS)], IIC_TZCNT_RM>, XS,
2332-
Sched<[WriteIMulLd]>;
2332+
Sched<[WriteTZCNTLd]>;
23332333
}
23342334

23352335
multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM,

‎lib/Target/X86/X86InstrSSE.td

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -6227,35 +6227,35 @@ let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
62276227
def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
62286228
"popcnt{w}\t{$src, $dst|$dst, $src}",
62296229
[(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)],
6230-
IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
6230+
IIC_SSE_POPCNT_RR>, Sched<[WritePOPCNT]>,
62316231
OpSize16, XS;
62326232
def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
62336233
"popcnt{w}\t{$src, $dst|$dst, $src}",
62346234
[(set GR16:$dst, (ctpop (loadi16 addr:$src))),
62356235
(implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6236-
Sched<[WriteFAddLd]>, OpSize16, XS;
6236+
Sched<[WritePOPCNTLd]>, OpSize16, XS;
62376237

62386238
def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
62396239
"popcnt{l}\t{$src, $dst|$dst, $src}",
62406240
[(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)],
6241-
IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
6241+
IIC_SSE_POPCNT_RR>, Sched<[WritePOPCNT]>,
62426242
OpSize32, XS;
62436243

62446244
def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
62456245
"popcnt{l}\t{$src, $dst|$dst, $src}",
62466246
[(set GR32:$dst, (ctpop (loadi32 addr:$src))),
62476247
(implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6248-
Sched<[WriteFAddLd]>, OpSize32, XS;
6248+
Sched<[WritePOPCNTLd]>, OpSize32, XS;
62496249

62506250
def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
62516251
"popcnt{q}\t{$src, $dst|$dst, $src}",
62526252
[(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)],
6253-
IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>, XS;
6253+
IIC_SSE_POPCNT_RR>, Sched<[WritePOPCNT]>, XS;
62546254
def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
62556255
"popcnt{q}\t{$src, $dst|$dst, $src}",
62566256
[(set GR64:$dst, (ctpop (loadi64 addr:$src))),
62576257
(implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6258-
Sched<[WriteFAddLd]>, XS;
6258+
Sched<[WritePOPCNTLd]>, XS;
62596259
}
62606260

62616261
// SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.

‎lib/Target/X86/X86SchedBroadwell.td

Lines changed: 7 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -110,6 +110,12 @@ def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, h
110110

111111
def : WriteRes<WriteLEA, [BWPort15]>; // LEA instructions can't fold loads.
112112

113+
// Bit counts.
114+
defm : BWWriteResPair<WriteBitScan, [BWPort1], 3>;
115+
defm : BWWriteResPair<WriteLZCNT, [BWPort1], 3>;
116+
defm : BWWriteResPair<WriteTZCNT, [BWPort1], 3>;
117+
defm : BWWriteResPair<WritePOPCNT, [BWPort1], 3>;
118+
113119
// Integer shifts and rotates.
114120
defm : BWWriteResPair<WriteShift, [BWPort06], 1>;
115121

@@ -851,13 +857,9 @@ def: InstRW<[BWWriteResGroup27], (instrs IMUL8r, MUL8r)>;
851857
def: InstRW<[BWWriteResGroup27], (instregex "ADD_FPrST0",
852858
"ADD_FST0r",
853859
"ADD_FrST0",
854-
"BSF(16|32|64)rr",
855-
"BSR(16|32|64)rr",
856-
"LZCNT(16|32|64)rr",
857860
"MMX_CVTPI2PSirr",
858861
"PDEP(32|64)rr",
859862
"PEXT(32|64)rr",
860-
"POPCNT(16|32|64)rr",
861863
"SHLD(16|32|64)rri8",
862864
"SHRD(16|32|64)rri8",
863865
"SUBR_FPrST0",
@@ -866,7 +868,6 @@ def: InstRW<[BWWriteResGroup27], (instregex "ADD_FPrST0",
866868
"SUB_FPrST0",
867869
"SUB_FST0r",
868870
"SUB_FrST0",
869-
"TZCNT(16|32|64)rr",
870871
"(V?)ADDPD(Y?)rr",
871872
"(V?)ADDPS(Y?)rr",
872873
"(V?)ADDSDrr",
@@ -1889,16 +1890,11 @@ def BWWriteResGroup91 : SchedWriteRes<[BWPort1,BWPort23]> {
18891890
}
18901891
def: InstRW<[BWWriteResGroup91], (instrs IMUL32rm, IMUL32rmi, IMUL32rmi8, IMUL64rm, IMUL64rmi8, IMUL64rmi32)>;
18911892
def: InstRW<[BWWriteResGroup91], (instrs IMUL8m, MUL8m)>;
1892-
def: InstRW<[BWWriteResGroup91], (instregex "BSF(16|32|64)rm",
1893-
"BSR(16|32|64)rm",
1894-
"LZCNT(16|32|64)rm",
1895-
"MMX_CVTPI2PSirm",
1893+
def: InstRW<[BWWriteResGroup91], (instregex "MMX_CVTPI2PSirm",
18961894
"MMX_CVTPS2PIirm",
18971895
"MMX_CVTTPS2PIirm",
18981896
"PDEP(32|64)rm",
18991897
"PEXT(32|64)rm",
1900-
"POPCNT(16|32|64)rm",
1901-
"TZCNT(16|32|64)rm",
19021898
"(V?)ADDPDrm",
19031899
"(V?)ADDPSrm",
19041900
"(V?)ADDSDrm",

‎lib/Target/X86/X86SchedHaswell.td

Lines changed: 7 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -121,6 +121,12 @@ defm : HWWriteResPair<WriteJump, [HWPort06], 1>;
121121
// the port to read all inputs. We don't model that.
122122
def : WriteRes<WriteLEA, [HWPort15]>;
123123

124+
// Bit counts.
125+
defm : HWWriteResPair<WriteBitScan, [HWPort1], 3>;
126+
defm : HWWriteResPair<WriteLZCNT, [HWPort1], 3>;
127+
defm : HWWriteResPair<WriteTZCNT, [HWPort1], 3>;
128+
defm : HWWriteResPair<WritePOPCNT, [HWPort1], 3>;
129+
124130
// This is quite rough, latency depends on the dividend.
125131
defm : HWWriteResPair<WriteIDiv, [HWPort0, HWDivider], 25, [1,10], 1, 4>;
126132
// Scalar and vector floating point.
@@ -1042,20 +1048,15 @@ def HWWriteResGroup12 : SchedWriteRes<[HWPort1,HWPort23]> {
10421048
def: InstRW<[HWWriteResGroup12], (instrs MUL8m, MUL16m,
10431049
IMUL8m, IMUL16m,
10441050
IMUL16rm, IMUL16rmi, IMUL16rmi8, IMUL32rm, IMUL32rmi, IMUL32rmi8, IMUL64rm, IMUL64rmi32, IMUL64rmi8)>;
1045-
def: InstRW<[HWWriteResGroup12], (instregex "BSF(16|32|64)rm",
1046-
"BSR(16|32|64)rm",
1047-
"FCOM32m",
1051+
def: InstRW<[HWWriteResGroup12], (instregex "FCOM32m",
10481052
"FCOM64m",
10491053
"FCOMP32m",
10501054
"FCOMP64m",
1051-
"LZCNT(16|32|64)rm",
10521055
"MMX_CVTPI2PSirm",
10531056
"MMX_CVTPS2PIirm",
10541057
"MMX_CVTTPS2PIirm",
10551058
"PDEP(32|64)rm",
10561059
"PEXT(32|64)rm",
1057-
"POPCNT(16|32|64)rm",
1058-
"TZCNT(16|32|64)rm",
10591060
"(V?)ADDSDrm",
10601061
"(V?)ADDSSrm",
10611062
"(V?)CMPSDrm",
@@ -1779,13 +1780,9 @@ def: InstRW<[HWWriteResGroup50], (instrs MUL8r, IMUL8r, IMUL16rr, IMUL32rr, IMUL
17791780
def: InstRW<[HWWriteResGroup50], (instregex "ADD_FPrST0",
17801781
"ADD_FST0r",
17811782
"ADD_FrST0",
1782-
"BSF(16|32|64)rr",
1783-
"BSR(16|32|64)rr",
1784-
"LZCNT(16|32|64)rr",
17851783
"MMX_CVTPI2PSirr",
17861784
"PDEP(32|64)rr",
17871785
"PEXT(32|64)rr",
1788-
"POPCNT(16|32|64)rr",
17891786
"SHLD(16|32|64)rri8",
17901787
"SHRD(16|32|64)rri8",
17911788
"SUBR_FPrST0",
@@ -1794,7 +1791,6 @@ def: InstRW<[HWWriteResGroup50], (instregex "ADD_FPrST0",
17941791
"SUB_FPrST0",
17951792
"SUB_FST0r",
17961793
"SUB_FrST0",
1797-
"TZCNT(16|32|64)rr",
17981794
"(V?)ADDPD(Y?)rr",
17991795
"(V?)ADDPS(Y?)rr",
18001796
"(V?)ADDSDrr",

‎lib/Target/X86/X86SchedSandyBridge.td

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -112,6 +112,12 @@ defm : SBWriteResPair<WriteJump, [SBPort5], 1>;
112112
// the port to read all inputs. We don't model that.
113113
def : WriteRes<WriteLEA, [SBPort15]>;
114114

115+
// Bit counts.
116+
defm : SBWriteResPair<WriteBitScan, [SBPort1], 3, [1], 1, 5>;
117+
defm : SBWriteResPair<WriteLZCNT, [SBPort1], 3, [1], 1, 5>;
118+
defm : SBWriteResPair<WriteTZCNT, [SBPort1], 3, [1], 1, 5>;
119+
defm : SBWriteResPair<WritePOPCNT, [SBPort1], 3, [1], 1, 5>;
120+
115121
// Scalar and vector floating point.
116122
def : WriteRes<WriteFStore, [SBPort23, SBPort4]>;
117123
def : WriteRes<WriteFLoad, [SBPort23]> { let Latency = 6; }
@@ -672,8 +678,6 @@ def: InstRW<[SBWriteResGroup21], (instrs MUL8r, IMUL16rr, IMUL32rr, IMUL32rri, I
672678
def: InstRW<[SBWriteResGroup21], (instregex "ADD_FPrST0",
673679
"ADD_FST0r",
674680
"ADD_FrST0",
675-
"BSF(16|32|64)rr",
676-
"BSR(16|32|64)rr",
677681
"CRC32r(16|32|64)r8",
678682
"CRC32r(16|32|64)r64",
679683
"MMX_CVTPI2PSirr",
@@ -1412,9 +1416,7 @@ def SBWriteResGroup72 : SchedWriteRes<[SBPort1,SBPort23]> {
14121416
let NumMicroOps = 2;
14131417
let ResourceCycles = [1,1];
14141418
}
1415-
def: InstRW<[SBWriteResGroup72], (instregex "BSF(16|32|64)rm",
1416-
"BSR(16|32|64)rm",
1417-
"CRC32r(16|32|64)m64",
1419+
def: InstRW<[SBWriteResGroup72], (instregex "CRC32r(16|32|64)m64",
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"CRC32r(16|32|64)m8",
14191421
"FCOM32m",
14201422
"FCOM64m",

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