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repkLorenzo Pieralisi
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Lorenzo Pieralisi
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phy: amlogic: Add Amlogic AXG PCIE PHY Driver
This adds support for the PCI PHY found in the Amlogic AXG SoC Family. This will allow to mutualize code in pci-meson.c between AXG and G12A SoC. This PHY also uses and chains an analog PHY, which on AXG platform is needed to have reliable PCIe communication. Signed-off-by: Remi Pommarel <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Neil Armstrong <[email protected]>
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‎drivers/phy/amlogic/Kconfig

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@@ -60,6 +60,17 @@ config PHY_MESON_G12A_USB3_PCIE
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in Meson G12A SoCs.
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If unsure, say N.
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config PHY_MESON_AXG_PCIE
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tristate "Meson AXG PCIE PHY driver"
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default ARCH_MESON
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depends on OF && (ARCH_MESON || COMPILE_TEST)
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select GENERIC_PHY
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select REGMAP_MMIO
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help
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Enable this to support the Meson MIPI + PCIE PHY found
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in Meson AXG SoCs.
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If unsure, say N.
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config PHY_MESON_AXG_MIPI_PCIE_ANALOG
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tristate "Meson AXG MIPI + PCIE analog PHY driver"
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default ARCH_MESON

‎drivers/phy/amlogic/Makefile

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@@ -4,4 +4,5 @@ obj-$(CONFIG_PHY_MESON_GXL_USB2) += phy-meson-gxl-usb2.o
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obj-$(CONFIG_PHY_MESON_G12A_USB2) += phy-meson-g12a-usb2.o
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obj-$(CONFIG_PHY_MESON_GXL_USB3) += phy-meson-gxl-usb3.o
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obj-$(CONFIG_PHY_MESON_G12A_USB3_PCIE) += phy-meson-g12a-usb3-pcie.o
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obj-$(CONFIG_PHY_MESON_AXG_PCIE) += phy-meson-axg-pcie.o
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obj-$(CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG) += phy-meson-axg-mipi-pcie-analog.o

‎drivers/phy/amlogic/phy-meson-axg-pcie.c

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// SPDX-License-Identifier: GPL-2.0
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/*
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* Amlogic AXG PCIE PHY driver
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*
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* Copyright (C) 2020 Remi Pommarel <[email protected]>
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*/
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#include <linux/module.h>
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#include <linux/phy/phy.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include <linux/platform_device.h>
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#include <linux/bitfield.h>
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#include <dt-bindings/phy/phy.h>
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#define MESON_PCIE_REG0 0x00
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#define MESON_PCIE_COMMON_CLK BIT(4)
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#define MESON_PCIE_PORT_SEL GENMASK(3, 2)
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#define MESON_PCIE_CLK BIT(1)
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#define MESON_PCIE_POWERDOWN BIT(0)
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#define MESON_PCIE_TWO_X1 FIELD_PREP(MESON_PCIE_PORT_SEL, 0x3)
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#define MESON_PCIE_COMMON_REF_CLK FIELD_PREP(MESON_PCIE_COMMON_CLK, 0x1)
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#define MESON_PCIE_PHY_INIT (MESON_PCIE_TWO_X1 | \
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MESON_PCIE_COMMON_REF_CLK)
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#define MESON_PCIE_RESET_DELAY 500
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struct phy_axg_pcie_priv {
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struct phy *phy;
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struct phy *analog;
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struct regmap *regmap;
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struct reset_control *reset;
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};
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static const struct regmap_config phy_axg_pcie_regmap_conf = {
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.reg_bits = 8,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = MESON_PCIE_REG0,
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};
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static int phy_axg_pcie_power_on(struct phy *phy)
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{
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struct phy_axg_pcie_priv *priv = phy_get_drvdata(phy);
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int ret;
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ret = phy_power_on(priv->analog);
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if (ret != 0)
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return ret;
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regmap_update_bits(priv->regmap, MESON_PCIE_REG0,
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MESON_PCIE_POWERDOWN, 0);
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return 0;
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}
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static int phy_axg_pcie_power_off(struct phy *phy)
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{
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struct phy_axg_pcie_priv *priv = phy_get_drvdata(phy);
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int ret;
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ret = phy_power_off(priv->analog);
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if (ret != 0)
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return ret;
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regmap_update_bits(priv->regmap, MESON_PCIE_REG0,
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MESON_PCIE_POWERDOWN, 1);
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return 0;
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}
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static int phy_axg_pcie_init(struct phy *phy)
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{
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struct phy_axg_pcie_priv *priv = phy_get_drvdata(phy);
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int ret;
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ret = phy_init(priv->analog);
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if (ret != 0)
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return ret;
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regmap_write(priv->regmap, MESON_PCIE_REG0, MESON_PCIE_PHY_INIT);
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return reset_control_reset(priv->reset);
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}
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static int phy_axg_pcie_exit(struct phy *phy)
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{
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struct phy_axg_pcie_priv *priv = phy_get_drvdata(phy);
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int ret;
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ret = phy_exit(priv->analog);
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if (ret != 0)
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return ret;
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return reset_control_reset(priv->reset);
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}
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static int phy_axg_pcie_reset(struct phy *phy)
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{
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struct phy_axg_pcie_priv *priv = phy_get_drvdata(phy);
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int ret = 0;
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ret = phy_reset(priv->analog);
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if (ret != 0)
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goto out;
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ret = reset_control_assert(priv->reset);
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if (ret != 0)
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goto out;
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udelay(MESON_PCIE_RESET_DELAY);
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ret = reset_control_deassert(priv->reset);
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if (ret != 0)
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goto out;
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udelay(MESON_PCIE_RESET_DELAY);
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out:
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return ret;
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}
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static const struct phy_ops phy_axg_pcie_ops = {
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.init = phy_axg_pcie_init,
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.exit = phy_axg_pcie_exit,
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.power_on = phy_axg_pcie_power_on,
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.power_off = phy_axg_pcie_power_off,
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.reset = phy_axg_pcie_reset,
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.owner = THIS_MODULE,
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};
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static int phy_axg_pcie_probe(struct platform_device *pdev)
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{
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struct phy_provider *pphy;
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struct device *dev = &pdev->dev;
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struct phy_axg_pcie_priv *priv;
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struct device_node *np = dev->of_node;
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struct resource *res;
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void __iomem *base;
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int ret;
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priv = devm_kmalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->phy = devm_phy_create(dev, np, &phy_axg_pcie_ops);
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if (IS_ERR(priv->phy)) {
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ret = PTR_ERR(priv->phy);
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if (ret != -EPROBE_DEFER)
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dev_err(dev, "failed to create PHY\n");
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return ret;
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base = devm_ioremap_resource(dev, res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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priv->regmap = devm_regmap_init_mmio(dev, base,
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&phy_axg_pcie_regmap_conf);
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if (IS_ERR(priv->regmap))
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return PTR_ERR(priv->regmap);
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priv->reset = devm_reset_control_array_get(dev, false, false);
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if (IS_ERR(priv->reset))
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return PTR_ERR(priv->reset);
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priv->analog = devm_phy_get(dev, "analog");
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if (IS_ERR(priv->analog))
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return PTR_ERR(priv->analog);
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phy_set_drvdata(priv->phy, priv);
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dev_set_drvdata(dev, priv);
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pphy = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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return PTR_ERR_OR_ZERO(pphy);
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}
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static const struct of_device_id phy_axg_pcie_of_match[] = {
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{
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.compatible = "amlogic,axg-pcie-phy",
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},
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{ },
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};
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MODULE_DEVICE_TABLE(of, phy_axg_pcie_of_match);
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static struct platform_driver phy_axg_pcie_driver = {
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.probe = phy_axg_pcie_probe,
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.driver = {
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.name = "phy-axg-pcie",
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.of_match_table = phy_axg_pcie_of_match,
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},
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};
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module_platform_driver(phy_axg_pcie_driver);
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MODULE_AUTHOR("Remi Pommarel <[email protected]>");
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MODULE_DESCRIPTION("Amlogic AXG PCIE PHY driver");
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MODULE_LICENSE("GPL v2");

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