Collaboration proposal

[kraigher]

Background

I am the maintainer of the Rust HDL project which implements a VHDL parser and semantic analysis as well as a language server. One of the goals for the Rust HDL project was to work as a complete and high performing foundation of tools for the VHDL language so that the community can come further and stop re-inventing the wheel. My vision is that rather than basing VHDL tools upon slow and incomplete regex in Python people could have access to a very fast and complete VHDL parser. My project was mentioned in this issue a few years back #312

Your project is of precisely the kind that I was hoping could be based upon my work and that is why I am writing here.

Status of my project

Since late 2022 I have made a large development effort and my project can now fully parse and type check all the major open source projects such as OSVVM, VUnit, PoC, NEORV32, Microwatt. It can parse and semantic check 270K lines of VHDL code in just 350 milliseconds. When used as a language server it has smart change detection so only a small subset is re-parsed and analyzed when the user times thus giving a real time syntax and type errors.

Proposal

The VHDL style guide project contains a lot of domain knowledge about the style and design rules for VHDL as well as a way to format VHDL but is lacking performance and completeness of the parsing and semantic analysis. The Rust HDL project does not have a style or design rules and does not yet implement VHDL formatting. Thus I really see the synergy in combining the efforts.

Also for the users I would be very valuable to have style and design rule checking in real time as they type inside their IDE instead of having to push the code to the CI-server to find out that they introduced a violation 3 commits back from the HEAD. I know from experience that checks that are run in CI instead of in real time are always forgotten and frustrating to go back and fixup the commits.

Thus I propose:

• You build a VSG2 in Rust with the style and design rule checks as a separate Rust crate that uses Rust HDL parsing and analysis under the hood.
  • This would be a separate Rust crate and project that could ship its own executable that can run in CI.
  • It could also be integrated in VHDL-LS language server to support real time checks, I would support you with that.
• Help me with developing VHDL auto-formatting support into my vhdl_lang crate.
  • I think formatting cannot be separated from the core VHDL library support so it cannot be a separate project.
  • Ideally we could work together on this.

[sibeov]

Not maintainer here, just fan of both projects!

This would be a fantastic synergy and collaboration!
Gives me a motivation for trying to learn Rust!

[jeremiah-c-leary]

Morning @kraigher,

The VHDL style guide project contains a lot of domain knowledge about the style and design rules for VHDL as well as a way to format VHDL but is lacking performance and completeness of the parsing and semantic analysis. The Rust HDL project does not have a style or design rules and does not yet implement VHDL formatting. Thus I really see the synergy in combining the efforts.

I agree VSG's performance and parsing could be significantly improved. Late last year I attempted to take some time off to decide where to take VSG next. Performance and the internal data structure were at the top of the list. The parsing algorithm works fairly well, but I found I was missing context in some cases which made parsing less than ideal.

I decided something had to change, but I am not sure exactly how to make the changes. I am open to looking into using rust for the performance, but have zero experience in the language.

So I would be open to exploring a collaboration with rustHDL.

Thus I propose:

Maybe we continue this discussion over at rustHDL. I'm sure I have plenty of questions.

Regards,

--Jeremy

[Schottkyc137]

Hi everyone,

I am a maintainer of Rust HDL, and have recently tackled the challenge of enabling formatting in the project. It's going quite well and I think that the required changes can be merged within the next couple of weeks. Here is the relevant pull request for reference. While the skeletal implementation is done, a lot of what's missing in the future is precisely what @kraigher mentioned in this issue; the knowledge and configuration options embedded in this project or similar.
I think not much happened since the last conversation (please correct me, if I'm wrong), so I hope that we can re-initiate the collaboration to bring forward more and better open-source tools for VHDL.

Best,
Lukas

[jeremiah-c-leary]

Morning @Schottkyc137 ,

I think not much happened since the last conversation (please correct me, if I'm wrong), so I hope that we can re-initiate the collaboration to bring forward more and better open-source tools for VHDL.

Not much has happened on the collaboration side. I was starting to learn Rust, but was distracted by other things. I can jump over to your pull request and continue the conversation.

--Jeremy