From 93602370daa60ea76dbfd51ffd39245bf71e4bd4 Mon Sep 17 00:00:00 2001 From: Soumi Manna Date: Tue, 2 Aug 2022 15:47:27 -0700 Subject: [PATCH 1/2] [SYCL][FPGA] Remove support for intel::fpga_pipeline attribute Support for new FPGA attribute called [[intel::fpga_pipeline(N)]] on https://github.com/intel/llvm/pull/6254 is no longer needed. This patch removes the support from frontend. Signed-off-by: Soumi Manna --- clang/include/clang/Basic/Attr.td | 23 ---- clang/include/clang/Basic/AttrDocs.td | 52 --------- clang/include/clang/Sema/Sema.h | 3 - clang/lib/CodeGen/CGLoopInfo.cpp | 22 +--- clang/lib/CodeGen/CGLoopInfo.h | 9 -- clang/lib/Sema/SemaStmtAttr.cpp | 30 ----- clang/lib/Sema/SemaTemplateInstantiate.cpp | 9 -- clang/test/CodeGenSYCL/intel-fpga-loops.cpp | 52 --------- clang/test/SemaSYCL/intel-fpga-loops.cpp | 106 ------------------ .../test/SemaSYCL/intel-fpga-pipeline-ast.cpp | 70 ------------ 10 files changed, 1 insertion(+), 375 deletions(-) delete mode 100644 clang/test/SemaSYCL/intel-fpga-pipeline-ast.cpp diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td index 3c0bb19433369..691b0f3f6922b 100644 --- a/clang/include/clang/Basic/Attr.td +++ b/clang/include/clang/Basic/Attr.td @@ -2331,23 +2331,6 @@ def : MutualExclusions<[SYCLIntelFPGAIVDep, def : MutualExclusions<[SYCLIntelFPGAMaxConcurrency, SYCLIntelFPGADisableLoopPipelining]>; -def SYCLIntelFPGAPipeline : InheritableAttr { - let Spellings = [CXX11<"intel","fpga_pipeline">]; - let Args = [ExprArgument<"Value", /*optional*/1>]; - let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost]; - let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt], - ErrorDiag, "'for', 'while', and 'do' statements">; - let Documentation = [SYCLIntelFPGAPipelineAttrDocs]; - let IsStmtDependent = 1; -} - -def : MutualExclusions<[SYCLIntelFPGAInitiationInterval, - SYCLIntelFPGAPipeline]>; -def : MutualExclusions<[SYCLIntelFPGAIVDep, - SYCLIntelFPGAPipeline]>; -def : MutualExclusions<[SYCLIntelFPGAMaxConcurrency, - SYCLIntelFPGAPipeline]>; - def SYCLIntelFPGALoopCount : StmtAttr { let Spellings = [CXX11<"intel", "loop_count_min">, CXX11<"intel", "loop_count_max">, @@ -2380,9 +2363,6 @@ def SYCLIntelFPGAMaxInterleaving : StmtAttr { def : MutualExclusions<[SYCLIntelFPGADisableLoopPipelining, SYCLIntelFPGAMaxInterleaving]>; -def : MutualExclusions<[SYCLIntelFPGAPipeline, - SYCLIntelFPGAMaxInterleaving]>; - def SYCLIntelFPGASpeculatedIterations : StmtAttr { let Spellings = [CXX11<"intel", "speculated_iterations">]; let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt], @@ -2395,9 +2375,6 @@ def SYCLIntelFPGASpeculatedIterations : StmtAttr { def : MutualExclusions<[SYCLIntelFPGADisableLoopPipelining, SYCLIntelFPGASpeculatedIterations]>; -def : MutualExclusions<[SYCLIntelFPGAPipeline, - SYCLIntelFPGASpeculatedIterations]>; - def SYCLIntelFPGANofusion : StmtAttr { let Spellings = [CXX11<"intel","nofusion">]; let Subjects = SubjectList<[ForStmt, CXXForRangeStmt, WhileStmt, DoStmt], diff --git a/clang/include/clang/Basic/AttrDocs.td b/clang/include/clang/Basic/AttrDocs.td index a55a6ec00d7c9..dc856ceeb39d1 100644 --- a/clang/include/clang/Basic/AttrDocs.td +++ b/clang/include/clang/Basic/AttrDocs.td @@ -3328,58 +3328,6 @@ or ``ivdep``. }]; } -def SYCLIntelFPGAPipelineAttrDocs : Documentation { - let Category = DocCatVariable; - let Heading = "intel::fpga_pipeline"; - let Content = [{ -The ``intel::fpga_pipeline(N)`` attribute applies to a loop and it allows users -to disable or enable pipelining iterations of a loop. The attribute optionally -accepts an integer constant expression that is converted to `bool`. A `true` -value enables pipelining while a `false` value disables pipelining. The -optional argument defaults to `true`. This attribute cannot be applied to a -loop in conjunction with the ``max_interleaving``, ``speculated_iterations``, -``max_concurrency``, ``initiation_interval``, or ``ivdep`` attributes. - -.. code-block:: c++ - - // Disable loop pipelining - void bar() { - int a[10]; - [[[intel::fpga_pipeline(0)]] for (int i = 0; i != 10; ++i) a[i] = 0; - } - - // Enable loop pipelining - void foo() { - int var = 0; - [[intel::fpga_pipeline(1)]] for (int i = 0; i < 10; ++i) var++; - } - - void Array(int *array, size_t n) { - // identical to [[intel::fpga_pipeline(1)]] - [[intel::fpga_pipeline]] for (int i = 0; i < n; ++i) array[i] = 0; - } - - void count () { - int a1[10], int i = 0; - [[intel::fpga_pipeline(1)]] while (i < 10) { - a1[i] += 3; - } - - void check() { - int a = 10; - [[intel::fpga_pipeline(1)]] do { - a = a + 1; - } while (a < 20); - } - - template - void func() { - [[intel::fpga_pipeline(A)]] for(;;) { } - } - - }]; -} - def SYCLIntelFPGALoopCountAttrDocs : Documentation { let Category = DocCatVariable; let Heading = "intel::loop_count_min, intel::loop_count_max, intel::loop_count_avg, intel::loop_count"; diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h index a7854d3d506bd..8b0611da97b3c 100644 --- a/clang/include/clang/Sema/Sema.h +++ b/clang/include/clang/Sema/Sema.h @@ -2288,9 +2288,6 @@ class Sema final { SYCLIntelFPGALoopCoalesceAttr * BuildSYCLIntelFPGALoopCoalesceAttr(const AttributeCommonInfo &CI, Expr *E); - SYCLIntelFPGAPipelineAttr * - BuildSYCLIntelFPGAPipelineAttr(const AttributeCommonInfo &CI, Expr *E); - bool CheckQualifiedFunctionForTypeId(QualType T, SourceLocation Loc); bool CheckFunctionReturnType(QualType T, SourceLocation Loc); diff --git a/clang/lib/CodeGen/CGLoopInfo.cpp b/clang/lib/CodeGen/CGLoopInfo.cpp index 43b995e72d243..3ce45370f75f1 100644 --- a/clang/lib/CodeGen/CGLoopInfo.cpp +++ b/clang/lib/CodeGen/CGLoopInfo.cpp @@ -612,13 +612,6 @@ MDNode *LoopInfo::createMetadata( LoopProperties.push_back(MDNode::get(Ctx, Vals)); } - for (auto &FP : Attrs.SYCLIntelFPGAPipeline) { - Metadata *Vals[] = {MDString::get(Ctx, FP.first), - ConstantAsMetadata::get(ConstantInt::get( - llvm::Type::getInt32Ty(Ctx), FP.second))}; - LoopProperties.push_back(MDNode::get(Ctx, Vals)); - } - LoopProperties.insert(LoopProperties.end(), AdditionalLoopProperties.begin(), AdditionalLoopProperties.end()); return createFullUnrollMetadata(Attrs, LoopProperties, HasUserTransforms); @@ -662,7 +655,6 @@ void LoopAttributes::clear() { PipelineDisabled = false; PipelineInitiationInterval = 0; SYCLNofusionEnable = false; - SYCLIntelFPGAPipeline.clear(); MustProgress = false; } @@ -696,8 +688,7 @@ LoopInfo::LoopInfo(BasicBlock *Header, const LoopAttributes &Attrs, Attrs.UnrollEnable == LoopAttributes::Unspecified && Attrs.UnrollAndJamEnable == LoopAttributes::Unspecified && Attrs.DistributeEnable == LoopAttributes::Unspecified && !StartLoc && - Attrs.SYCLNofusionEnable == false && - Attrs.SYCLIntelFPGAPipeline.empty() && !EndLoc && !Attrs.MustProgress) + Attrs.SYCLNofusionEnable == false && !EndLoc && !Attrs.MustProgress) return; TempLoopID = MDNode::getTemporary(Header->getContext(), None); @@ -1021,8 +1012,6 @@ void LoopInfoStack::push(BasicBlock *Header, clang::ASTContext &Ctx, // emitted // For attribute nofusion: // 'llvm.loop.fusion.disable' metadata will be emitted - // For attribute fpga_pipeline: - // n - 'llvm.loop.intel.pipelining.enable, i32 n' metadata will be emitted for (const auto *A : Attrs) { if (const auto *IntelFPGAIVDep = dyn_cast(A)) addSYCLIVDepInfo(Header->getContext(), IntelFPGAIVDep->getSafelenValue(), @@ -1087,15 +1076,6 @@ void LoopInfoStack::push(BasicBlock *Header, clang::ASTContext &Ctx, if (isa(A)) setSYCLNofusionEnable(); - - if (const auto *IntelFPGAPipeline = - dyn_cast(A)) { - const auto *CE = cast(IntelFPGAPipeline->getValue()); - Optional ArgVal = CE->getResultAsAPSInt(); - unsigned int Value = ArgVal->getBoolValue() ? 1 : 0; - const char *Var = "llvm.loop.intel.pipelining.enable"; - setSYCLIntelFPGAPipeline(Var, Value); - } } setMustProgress(MustProgress); diff --git a/clang/lib/CodeGen/CGLoopInfo.h b/clang/lib/CodeGen/CGLoopInfo.h index a0a2ae1f94292..f48cfb248c3cb 100644 --- a/clang/lib/CodeGen/CGLoopInfo.h +++ b/clang/lib/CodeGen/CGLoopInfo.h @@ -152,10 +152,6 @@ struct LoopAttributes { /// Flag for llvm.loop.fusion.disable metatdata. bool SYCLNofusionEnable; - /// Value for fpga_pipeline variant and metadata. - llvm::SmallVector, 2> - SYCLIntelFPGAPipeline; - /// Value for whether the loop is required to make progress. bool MustProgress; }; @@ -411,11 +407,6 @@ class LoopInfoStack { /// Set flag of nofusion for the next loop pushed. void setSYCLNofusionEnable() { StagedAttrs.SYCLNofusionEnable = true; } - /// Set variant and value of fpga_pipeline for the next loop pushed. - void setSYCLIntelFPGAPipeline(const char *Var, unsigned int Value) { - StagedAttrs.SYCLIntelFPGAPipeline.push_back({Var, Value}); - } - /// Set no progress for the next loop pushed. void setMustProgress(bool P) { StagedAttrs.MustProgress = P; } diff --git a/clang/lib/Sema/SemaStmtAttr.cpp b/clang/lib/Sema/SemaStmtAttr.cpp index fc5a5701af118..27109565b3191 100644 --- a/clang/lib/Sema/SemaStmtAttr.cpp +++ b/clang/lib/Sema/SemaStmtAttr.cpp @@ -219,33 +219,6 @@ static Attr *handleSYCLIntelFPGADisableLoopPipeliningAttr(Sema &S, Stmt *, return new (S.Context) SYCLIntelFPGADisableLoopPipeliningAttr(S.Context, A); } -// Handle [[intel:fpga_pipeline]] attribute. -static Attr *handleSYCLIntelFPGAPipelineAttr(Sema &S, Stmt *, - const ParsedAttr &A) { - // If no attribute argument is specified, set to default value '1'. - Expr *E = A.isArgExpr(0) - ? A.getArgAsExpr(0) - : IntegerLiteral::Create(S.Context, llvm::APInt(32, 1), - S.Context.IntTy, A.getLoc()); - - return S.BuildSYCLIntelFPGAPipelineAttr(A, E); -} - -SYCLIntelFPGAPipelineAttr * -Sema::BuildSYCLIntelFPGAPipelineAttr(const AttributeCommonInfo &A, Expr *E) { - - if (!E->isValueDependent()) { - // Check if the expression is not value dependent. - llvm::APSInt ArgVal; - ExprResult Res = VerifyIntegerConstantExpression(E, &ArgVal); - if (Res.isInvalid()) - return nullptr; - E = Res.get(); - } - - return new (Context) SYCLIntelFPGAPipelineAttr(Context, A, E); -} - static bool checkSYCLIntelFPGAIVDepSafeLen(Sema &S, llvm::APSInt &Value, Expr *E) { // This attribute requires a non-negative value. @@ -855,7 +828,6 @@ static void CheckForIncompatibleSYCLLoopAttributes( CheckForDuplicationSYCLLoopAttribute(S, Attrs, false); CheckRedundantSYCLIntelFPGAIVDepAttrs(S, Attrs); CheckForDuplicationSYCLLoopAttribute(S, Attrs); - CheckForDuplicationSYCLLoopAttribute(S, Attrs); } void CheckForIncompatibleUnrollHintAttributes( @@ -1001,8 +973,6 @@ static Attr *ProcessStmtAttribute(Sema &S, Stmt *St, const ParsedAttr &A, return handleUnlikely(S, St, A, Range); case ParsedAttr::AT_SYCLIntelFPGANofusion: return handleIntelFPGANofusionAttr(S, St, A); - case ParsedAttr::AT_SYCLIntelFPGAPipeline: - return handleSYCLIntelFPGAPipelineAttr(S, St, A); default: // N.B., ClangAttrEmitter.cpp emits a diagnostic helper that ensures a // declaration attribute is not written on a statement, but this code is diff --git a/clang/lib/Sema/SemaTemplateInstantiate.cpp b/clang/lib/Sema/SemaTemplateInstantiate.cpp index 71bba5178fb70..2a0e9421fb55a 100644 --- a/clang/lib/Sema/SemaTemplateInstantiate.cpp +++ b/clang/lib/Sema/SemaTemplateInstantiate.cpp @@ -1112,8 +1112,6 @@ namespace { const SYCLIntelFPGASpeculatedIterationsAttr *SI); const SYCLIntelFPGALoopCountAttr * TransformSYCLIntelFPGALoopCountAttr(const SYCLIntelFPGALoopCountAttr *SI); - const SYCLIntelFPGAPipelineAttr * - TransformSYCLIntelFPGAPipelineAttr(const SYCLIntelFPGAPipelineAttr *SI); ExprResult TransformPredefinedExpr(PredefinedExpr *E); ExprResult TransformDeclRefExpr(DeclRefExpr *E); @@ -1605,13 +1603,6 @@ const LoopUnrollHintAttr *TemplateInstantiator::TransformLoopUnrollHintAttr( return getSema().BuildLoopUnrollHintAttr(*LU, TransformedExpr); } -const SYCLIntelFPGAPipelineAttr * -TemplateInstantiator::TransformSYCLIntelFPGAPipelineAttr( - const SYCLIntelFPGAPipelineAttr *PA) { - Expr *TransformedExpr = getDerived().TransformExpr(PA->getValue()).get(); - return getSema().BuildSYCLIntelFPGAPipelineAttr(*PA, TransformedExpr); -} - ExprResult TemplateInstantiator::transformNonTypeTemplateParmRef( NonTypeTemplateParmDecl *parm, SourceLocation loc, diff --git a/clang/test/CodeGenSYCL/intel-fpga-loops.cpp b/clang/test/CodeGenSYCL/intel-fpga-loops.cpp index cbdfca71c2de9..44306a2660011 100644 --- a/clang/test/CodeGenSYCL/intel-fpga-loops.cpp +++ b/clang/test/CodeGenSYCL/intel-fpga-loops.cpp @@ -20,14 +20,6 @@ // CHECK: br label %for.cond2, !llvm.loop ![[MD_LCA_1:[0-9]+]] // CHECK: br label %for.cond13, !llvm.loop ![[MD_LCA_2:[0-9]+]] // CHECK: br label %for.cond24, !llvm.loop ![[MD_LCA_3:[0-9]+]] -// CHECK: br label %for.cond, !llvm.loop ![[MD_FP:[0-9]+]] -// CHECK: br label %for.cond2, !llvm.loop ![[MD_FP_1:[0-9]+]] -// CHECK: br label %for.cond13, !llvm.loop ![[MD_FP_2:[0-9]+]] -// CHECK: br label %for.cond24, !llvm.loop ![[MD_FP_3:[0-9]+]] -// CHECK: br label %while.cond, !llvm.loop ![[MD_FP_4:[0-9]+]] -// CHECK: br i1 %cmp38, label %do.body, label %do.end, !llvm.loop ![[MD_FP_5:[0-9]+]] -// CHECK: br label %for.cond40, !llvm.loop ![[MD_FP_6:[0-9]+]] -// CHECK: br label %while.cond47, !llvm.loop ![[MD_FP_7:[0-9]+]] void disable_loop_pipelining() { int a[10]; @@ -134,7 +126,6 @@ void speculated_iterations() { a[i] = 0; } -// Add CodeGen tests for FPGA loop attribute: [[intel::fpga_pipeline()]]. template void loop_count_control() { int a[10]; @@ -159,48 +150,6 @@ void loop_count_control() { a[i] = 0; } -// Add CodeGen tests for Loop attribute: [[intel::fpga_pipeline()]]. -template -void fpga_pipeline() { - int a[10]; - // CHECK: ![[MD_FP]] = distinct !{![[MD_FP]], ![[MP]], ![[MD_fpga_pipeline:[0-9]+]]} - // CHECK-NEXT: ![[MD_fpga_pipeline]] = !{!"llvm.loop.intel.pipelining.enable", i32 1} - [[intel::fpga_pipeline(A)]] for (int i = 0; i != 10; ++i) - a[i] = 0; - - // CHECK: ![[MD_FP_1]] = distinct !{![[MD_FP_1]], ![[MP]], ![[MD_fpga_pipeline]]} - [[intel::fpga_pipeline(1)]] for (int i = 0; i != 10; ++i) - a[i] = 0; - - // CHECK: ![[MD_FP_2]] = distinct !{![[MD_FP_2]], ![[MP]], ![[MD_fpga_pipeline]]} - [[intel::fpga_pipeline]] for (int i = 0; i != 10; ++i) - a[i] = 0; - - // CHECK: ![[MD_FP_3]] = distinct !{![[MD_FP_3]], ![[MP]], ![[MD_dlp]]} - [[intel::fpga_pipeline(0)]] for (int i = 0; i != 10; ++i) - a[i] = 0; - - // CHECK: ![[MD_FP_4]] = distinct !{![[MD_FP_4]], ![[MP]], ![[MD_fpga_pipeline]]} - int j = 0; - [[intel::fpga_pipeline]] while (j < 10) { - a[j] += 3; - } - - // CHECK: ![[MD_FP_5]] = distinct !{![[MD_FP_5]], ![[MP]], ![[MD_fpga_pipeline]]} - int b = 10; - [[intel::fpga_pipeline(1)]] do { - b = b + 1; - } while (b < 20); - - // CHECK: ![[MD_FP_6]] = distinct !{![[MD_FP_6]], ![[MD_fpga_pipeline]]} - int c[] = {0, 1, 2, 3, 4, 5}; - [[intel::fpga_pipeline(A)]] for (int n : c) { n *= 2; } - - // CHECK: ![[MD_FP_7]] = distinct !{![[MD_FP_7]], ![[MP]], ![[MD_fpga_pipeline]]} - int k = 0; - [[intel::fpga_pipeline(-1)]] while (k < 20) { a[k] += 2; } -} - template __attribute__((sycl_kernel)) void kernel_single_task(const Func &kernelFunc) { kernelFunc(); @@ -216,7 +165,6 @@ int main() { max_interleaving<3, 0>(); speculated_iterations<4, 0>(); loop_count_control<12>(); - fpga_pipeline<1>(); }); return 0; } diff --git a/clang/test/SemaSYCL/intel-fpga-loops.cpp b/clang/test/SemaSYCL/intel-fpga-loops.cpp index 4a14afbcc0697..87f32d2df271a 100644 --- a/clang/test/SemaSYCL/intel-fpga-loops.cpp +++ b/clang/test/SemaSYCL/intel-fpga-loops.cpp @@ -26,8 +26,6 @@ void foo() { [[intel::loop_count_avg(6)]] int l[10]; // expected-error@+1{{'loop_count' attribute cannot be applied to a declaration}} [[intel::loop_count(8)]] int m[10]; - // expected-error@+1{{'fpga_pipeline' attribute cannot be applied to a declaration}} - [[intel::fpga_pipeline(1)]] int n[10]; } // Test for deprecated spelling of Intel FPGA loop attributes @@ -124,10 +122,6 @@ void boo() { // expected-error@+1 {{'loop_count' attribute takes one argument}} [[intel::loop_count(6, 9)]] for (int i = 0; i != 10; ++i) a[i] = 0; - - // expected-error@+1 {{'fpga_pipeline' attribute takes no more than 1 argument}} - [[intel::fpga_pipeline(1, 2)]] for (int i = 0; i != 10; ++i) - a[i] = 0; } // Test for incorrect argument value for Intel FPGA loop attributes @@ -137,9 +131,6 @@ void goo() { [[intel::disable_loop_pipelining]] for (int i = 0; i != 10; ++i) a[i] = 0; // no diagnostics are expected - [[intel::fpga_pipeline]] for (int i = 0; i != 10; ++i) - a[i] = 0; - // no diagnostics are expected [[intel::max_concurrency(0)]] for (int i = 0; i != 10; ++i) a[i] = 0; // expected-warning@+1 {{'ivdep' attribute with value 0 has no effect; attribute ignored}} @@ -225,16 +216,6 @@ void goo() { // expected-error@+1 {{'loop_count' attribute requires a non-negative integral compile time constant expression}} [[intel::loop_count(-1)]] for (int i = 0; i != 10; ++i) a[i] = 0; - - // no diagnostics are expected - [[intel::fpga_pipeline(0)]] for (int i = 0; i != 10; ++i) - a[i] = 0; - // no diagnostics are expected - [[intel::fpga_pipeline(-1)]] for (int i = 0; i != 10; ++i) - a[i] = 0; - // expected-error@+1 {{integral constant expression must have integral or unscoped enumeration type, not 'const char[4]'}} - [[intel::fpga_pipeline("abc")]] for (int i = 0; i != 10; ++i) - a[i] = 0; } // Test for Intel FPGA loop attributes duplication @@ -276,10 +257,6 @@ void zoo() { // expected-error@+1 {{duplicate Intel FPGA loop attribute 'disable_loop_pipelining'}} [[intel::disable_loop_pipelining]] for (int i = 0; i != 10; ++i) a[i] = 0; - [[intel::fpga_pipeline]] - // expected-error@+1 {{duplicate Intel FPGA loop attribute 'fpga_pipeline'}} - [[intel::fpga_pipeline]] for (int i = 0; i != 10; ++i) - a[i] = 0; [[intel::loop_coalesce(2)]] // expected-error@+2 {{duplicate Intel FPGA loop attribute 'loop_coalesce'}} [[intel::max_interleaving(1)]] @@ -365,9 +342,6 @@ void loop_attrs_compatibility() { // no diagnostics are expected [[intel::disable_loop_pipelining]] [[intel::loop_coalesce]] for (int i = 0; i != 10; ++i) a[i] = 0; - // no diagnostics are expected - [[intel::fpga_pipeline]] [[intel::loop_coalesce]] for (int i = 0; i != 10; ++i) - a[i] = 0; // expected-error@+2 {{'max_interleaving' and 'disable_loop_pipelining' attributes are not compatible}} // expected-note@+1 {{conflicting attribute is here}} [[intel::disable_loop_pipelining]] [[intel::max_interleaving(0)]] for (int i = 0; i != 10; ++i) @@ -380,10 +354,6 @@ void loop_attrs_compatibility() { // expected-note@+1 {{conflicting attribute is here}} [[intel::speculated_iterations(0)]] [[intel::disable_loop_pipelining]] for (int i = 0; i != 10; ++i) a[i] = 0; - // expected-error@+2 {{'fpga_pipeline' and 'speculated_iterations' attributes are not compatible}} - // expected-note@+1 {{conflicting attribute is here}} - [[intel::speculated_iterations(0)]] [[intel::fpga_pipeline]] for (int i = 0; i != 10; ++i) - a[i] = 0; // expected-error@+2 {{'disable_loop_pipelining' and 'initiation_interval' attributes are not compatible}} // expected-note@+1 {{conflicting attribute is here}} [[intel::initiation_interval(10)]] [[intel::disable_loop_pipelining]] for (int i = 0; i != 10; ++i) @@ -392,10 +362,6 @@ void loop_attrs_compatibility() { // expected-note@+1 {{conflicting attribute is here}} [[intel::disable_loop_pipelining]] [[intel::ivdep]] for (int i = 0; i != 10; ++i) a[i] = 0; - // expected-error@+2 {{'fpga_pipeline' and 'initiation_interval' attributes are not compatible}} - // expected-note@+1 {{conflicting attribute is here}} - [[intel::initiation_interval(10)]] [[intel::fpga_pipeline]] for (int i = 0; i != 10; ++i) - a[i] = 0; // no diagnostics are expected [[intel::disable_loop_pipelining]] [[intel::nofusion]] for (int i = 0; i != 10; ++i) a[i] = 0; @@ -408,44 +374,6 @@ void loop_attrs_compatibility() { a[i] = 0; [[intel::loop_count(8)]] for (int i = 0; i != 10; ++i) a[i] = 0; - - // no diagnostics are expected - [[intel::fpga_pipeline]] [[intel::loop_coalesce]] for (int i = 0; i != 10; ++i) - a[i] = 0; - - // no diagnostics are expected - [[intel::fpga_pipeline]] [[intel::nofusion]] for (int i = 0; i != 10; ++i) - a[i] = 0; - // no diagnostics are expected - [[intel::fpga_pipeline]] [[intel::loop_count_avg(8)]] for (int i = 0; i != 10; ++i) - a[i] = 0; - [[intel::loop_count_min(8)]] - for (int i = 0; i != 10; ++i) - a[i] = 0; - [[intel::loop_count_max(8)]] - for (int i = 0; i != 10; ++i) - a[i] = 0; - [[intel::loop_count(8)]] for (int i = 0; i != 10; ++i) - a[i] = 0; - - // expected-error@+2 {{'fpga_pipeline' and 'max_concurrency' attributes are not compatible}} - // expected-note@+1 {{conflicting attribute is here}} - [[intel::max_concurrency(2)]] [[intel::fpga_pipeline(1)]] for (int i = 0; i != 10; ++i) - a[i] = 0; - - // expected-error@+2 {{'fpga_pipeline' and 'max_interleaving' attributes are not compatible}} - // expected-note@+1 {{conflicting attribute is here}} - [[intel::max_interleaving(2)]] [[intel::fpga_pipeline]] for (int i = 0; i != 10; ++i) - a[i] = 0; - - // expected-error@+2 {{'fpga_pipeline' and 'ivdep' attributes are not compatible}} - // expected-note@+1 {{conflicting attribute is here}} - [[intel::ivdep]] [[intel::fpga_pipeline]] for (int i = 0; i != 10; ++i) - a[i] = 0; - - // no diagnostics are expected - [[intel::disable_loop_pipelining]] [[intel::fpga_pipeline]] for (int i = 0; i != 10; ++i) - a[i] = 0; } template @@ -606,17 +534,6 @@ void loop_count_control_dependent() { a[i] = 0; } -template -void fpga_pipeline_dependent() { - int a[10]; - [[intel::fpga_pipeline(C)]] for (int i = 0; i != 10; ++i) - a[i] = 0; - - // expected-error@+1 {{duplicate Intel FPGA loop attribute 'fpga_pipeline'}} - [[intel::fpga_pipeline(A)]] [[intel::fpga_pipeline(B)]] for (int i = 0; i != 10; ++i) - a[i] = 0; -} - void check_max_concurrency_expression() { int a[10]; // Test that checks expression is not a constant expression. @@ -713,22 +630,6 @@ void check_loop_count_expression() { a[i] = 0; } -void check_loop_fpga_pipeline_expression() { - int a[10]; - - // Test that checks expression is not a constant expression. - int foo; // expected-note {{declared here}} - // expected-error@+2{{expression is not an integral constant expression}} - // expected-note@+1{{read of non-const variable 'foo' is not allowed in a constant expression}} - [[intel::fpga_pipeline(foo + 1)]] for (int i = 0; i != 10; ++i) - a[i] = 0; - - // Test that checks expression is a constant expression. - constexpr int bar = 0; - [[intel::fpga_pipeline(bar + 1)]] for (int i = 0; i != 10; ++i) // OK - a[i] = 0; -} - // Test that checks wrong template instantiation and ensures that the type // is checked properly when instantiating from the template definition. struct S {}; @@ -770,11 +671,6 @@ void check_loop_attr_template_instantiation() { // expected-error@+1 {{integral constant expression must have integral or unscoped enumeration type, not 'float'}} [[intel::loop_count(Ty{})]] for (int i = 0; i != 10; ++i) a[i] = 0; - - // expected-error@+2 {{integral constant expression must have integral or unscoped enumeration type, not 'S'}} - // expected-error@+1 {{integral constant expression must have integral or unscoped enumeration type, not 'float'}} - [[intel::fpga_pipeline(Ty{})]] for (int i = 0; i != 10; ++i) - a[i] = 0; } int main() { @@ -797,14 +693,12 @@ int main() { speculated_iterations_dependent<1, 8, -3, 0>(); // expected-note{{in instantiation of function template specialization 'speculated_iterations_dependent<1, 8, -3, 0>' requested here}} loop_coalesce_dependent<-1, 4, 0>(); // expected-note{{in instantiation of function template specialization 'loop_coalesce_dependent<-1, 4, 0>' requested here}} loop_count_control_dependent<3, 2, -1>(); // expected-note{{in instantiation of function template specialization 'loop_count_control_dependent<3, 2, -1>' requested here}} - fpga_pipeline_dependent<1, 1, 0>(); check_max_concurrency_expression(); check_max_interleaving_expression(); check_speculated_iterations_expression(); check_loop_coalesce_expression(); check_initiation_interval_expression(); check_loop_count_expression(); - check_loop_fpga_pipeline_expression(); check_loop_attr_template_instantiation(); //expected-note{{in instantiation of function template specialization 'check_loop_attr_template_instantiation' requested here}} check_loop_attr_template_instantiation(); //expected-note{{in instantiation of function template specialization 'check_loop_attr_template_instantiation' requested here}} }); diff --git a/clang/test/SemaSYCL/intel-fpga-pipeline-ast.cpp b/clang/test/SemaSYCL/intel-fpga-pipeline-ast.cpp deleted file mode 100644 index e2fecd866891d..0000000000000 --- a/clang/test/SemaSYCL/intel-fpga-pipeline-ast.cpp +++ /dev/null @@ -1,70 +0,0 @@ -// RUN: %clang_cc1 -fsycl-is-device -internal-isystem %S/Inputs -fsyntax-only -ast-dump -Wno-sycl-2017-compat -verify %s | FileCheck %s -// expected-no-diagnostics - -// Add AST tests for Loop attribute: [[intel::fpga_pipeline()]]. - -#include "sycl.hpp" - -using namespace cl::sycl; -queue q; - -template -void fpga_pipeline() { - int a1[10], a2[10]; - // CHECK: AttributedStmt - // CHECK-NEXT: SYCLIntelFPGAPipelineAttr - [[intel::fpga_pipeline(A)]] for (int p = 0; p < 10; ++p) { - a1[p] = a2[p] = 0; - } - - // CHECK: AttributedStmt - // CHECK-NEXT: SYCLIntelFPGAPipelineAttr - // CHECK-NEXT: ConstantExpr{{.*}}'int' - // CHECK-NEXT: value: Int 1 - // CHECK-NEXT: IntegerLiteral{{.*}}1{{$}} - int i = 0; - [[intel::fpga_pipeline]] while (i < 10) { - a1[i] += 3; - } - - // CHECK: AttributedStmt - // CHECK-NEXT: SYCLIntelFPGAPipelineAttr - // CHECK-NEXT: ConstantExpr{{.*}}'int' - // CHECK-NEXT: value: Int 1 - // CHECK-NEXT: IntegerLiteral{{.*}}1{{$}} - for (int i = 0; i < 10; ++i) { - [[intel::fpga_pipeline(1)]] for (int j = 0; j < 10; ++j) { - a1[i] += a1[j]; - } - } - - // CHECK: AttributedStmt - // CHECK-NEXT: SYCLIntelFPGAPipelineAttr - // CHECK-NEXT: ConstantExpr{{.*}}'int' - // CHECK-NEXT: value: Int 0 - // CHECK-NEXT: IntegerLiteral{{.*}}0{{$}} - [[intel::fpga_pipeline(0)]] for (int i = 0; i != 10; ++i) - a1[i] = 0; - - // CHECK: AttributedStmt - // CHECK-NEXT: SYCLIntelFPGAPipelineAttr - // CHECK-NEXT: ConstantExpr{{.*}}'int' - // CHECK-NEXT: value: Int 1 - // CHECK-NEXT: IntegerLiteral{{.*}}1{{$}} - int b = 10; - [[intel::fpga_pipeline(1)]] do { - b = b + 1; - } while (b < 20); - - // CHECK: AttributedStmt - // CHECK-NEXT: SYCLIntelFPGAPipelineAttr - int c[] = {0, 1, 2, 3, 4, 5}; - [[intel::fpga_pipeline(A)]] for (int n : c) { n *= 2; } -} - -int main() { - q.submit([&](handler &h) { - h.single_task([]() { fpga_pipeline<1>(); }); - }); - return 0; -} From 1652ef1e8dd89f831ef7632fc23ce3000e88f9b1 Mon Sep 17 00:00:00 2001 From: Soumi Manna Date: Wed, 3 Aug 2022 05:24:30 -0700 Subject: [PATCH 2/2] address comment Signed-off-by: Soumi Manna --- clang/test/CodeGenSYCL/intel-fpga-loops.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/clang/test/CodeGenSYCL/intel-fpga-loops.cpp b/clang/test/CodeGenSYCL/intel-fpga-loops.cpp index 44306a2660011..87e8f2b9e6bb3 100644 --- a/clang/test/CodeGenSYCL/intel-fpga-loops.cpp +++ b/clang/test/CodeGenSYCL/intel-fpga-loops.cpp @@ -126,6 +126,7 @@ void speculated_iterations() { a[i] = 0; } +// Add CodeGen tests for FPGA loop_count attributes. template void loop_count_control() { int a[10];