From f5792ff7beaafa31563317f218a41466de33bcf5 Mon Sep 17 00:00:00 2001 From: Michael D Toguchi Date: Tue, 6 Jul 2021 17:12:25 -0700 Subject: [PATCH] [Driver][SYCL] Enable adding of default device triple for AOT When specifying an AOT enabling triple (spir64_gen, spir64_fpga, spir64_x86_64) without also providing the default triple (spir64), enable the default triple as well as the AOT enabling triple. --- clang/include/clang/Driver/Driver.h | 13 ++++++ clang/include/clang/Driver/Options.td | 3 ++ clang/lib/Driver/Driver.cpp | 40 ++++++++++++++++-- clang/lib/Driver/ToolChains/Clang.cpp | 8 +++- clang/lib/Driver/ToolChains/SYCL.cpp | 41 ++++++++++++++----- clang/lib/Driver/ToolChains/SYCL.h | 10 +++-- clang/test/Driver/sycl-intelfpga-aoco-win.cpp | 8 ++-- clang/test/Driver/sycl-intelfpga-aoco.cpp | 14 +++---- .../test/Driver/sycl-intelfpga-static-lib.cpp | 2 +- .../Driver/sycl-offload-intelfpga-emu.cpp | 28 ++++++------- clang/test/Driver/sycl-offload-intelfpga.cpp | 41 +++++++++---------- clang/test/Driver/sycl-offload-with-split.c | 6 +-- clang/test/Driver/sycl-offload.c | 41 +++++++++++++------ 13 files changed, 171 insertions(+), 84 deletions(-) diff --git a/clang/include/clang/Driver/Driver.h b/clang/include/clang/Driver/Driver.h index cc43503558be0..6fb8f7448ef3d 100644 --- a/clang/include/clang/Driver/Driver.h +++ b/clang/include/clang/Driver/Driver.h @@ -655,6 +655,11 @@ class Driver { FPGAEmulationMode = IsEmulation; } + /// For SYCL w/ AOT, we imply the default device triple (spir64) as well. + /// We need to keep track of this so any use of any generic target option + /// setting is only applied to the user specified triples. + mutable bool SYCLDefaultTripleSet = false; + /// Returns true if an offload static library is found. bool checkForOffloadStaticLib(Compilation &C, llvm::opt::DerivedArgList &Args) const; @@ -714,6 +719,14 @@ class Driver { /// FPGA Emulation. This is only used for SYCL offloading to FPGA device. bool isFPGAEmulationMode() const { return FPGAEmulationMode; }; + /// isSYCLDefaultTripleSet - The default SYCL triple (spir64) has been added + /// along with the user specified AOT triples. + bool isSYCLDefaultTripleSet() const { return SYCLDefaultTripleSet; }; + + void setSYCLDefaultTriple(bool IsDefaultSet) const { + SYCLDefaultTripleSet = IsDefaultSet; + } + /// addIntegrationFiles - Add the integration files that will be populated /// by the device compilation and used by the host compile. void addIntegrationFiles(StringRef IntHeaderName, StringRef IntFooterName, diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 05d6203453c20..b9d554ea66e60 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -2635,6 +2635,9 @@ def fsycl_host_compiler_options_EQ : Joined<["-"], "fsycl-host-compiler-options= def fno_sycl_use_footer : Flag<["-"], "fno-sycl-use-footer">, Flags<[CoreOption]>, HelpText<"Disable usage of the integration footer during SYCL enabled " "compilations.">; +def fno_sycl_default_triple : Flag<["-"], "fno-sycl-default-triple">, + Flags<[CoreOption]>, HelpText<"Disable adding of the default (spir64) triple " + "when building for AOT targets.">; def fsyntax_only : Flag<["-"], "fsyntax-only">, Flags<[NoXarchOption,CoreOption,CC1Option,FC1Option]>, Group; def ftabstop_EQ : Joined<["-"], "ftabstop=">, Group; diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp index fb2ec73acaf4a..098e851a25e99 100644 --- a/clang/lib/Driver/Driver.cpp +++ b/clang/lib/Driver/Driver.cpp @@ -718,6 +718,24 @@ static bool isValidSYCLTriple(llvm::Triple T) { return true; } +static bool addSYCLDefaultTriple(Compilation &C, + SmallVectorImpl &SYCLTriples) { + if (C.getArgs().hasArg(options::OPT_fno_sycl_default_triple)) + return false; + for (const auto &SYCLTriple : SYCLTriples) { + if (SYCLTriple.getSubArch() == llvm::Triple::NoSubArch && + SYCLTriple.isSPIR()) + return false; + // If we encounter a known non-spir* target, do not add the default triple. + if (SYCLTriple.isNVPTX() || SYCLTriple.isAMDGCN()) + return false; + } + // Add the default triple as it was not found. + llvm::Triple DefaultTriple = C.getDriver().MakeSYCLDeviceTriple("spir64"); + SYCLTriples.push_back(DefaultTriple); + return true; +} + void Driver::CreateOffloadingDeviceToolChains(Compilation &C, InputList &Inputs) { @@ -919,8 +937,9 @@ void Driver::CreateOffloadingDeviceToolChains(Compilation &C, // Make sure we don't have a duplicate triple. auto Duplicate = FoundNormalizedTriples.find(NormalizedName); if (Duplicate != FoundNormalizedTriples.end()) { - Diag(clang::diag::warn_drv_sycl_offload_target_duplicate) - << Val << Duplicate->second; + if (!Duplicate->second.equals("spir64")) + Diag(clang::diag::warn_drv_sycl_offload_target_duplicate) + << Val << Duplicate->second; continue; } @@ -929,6 +948,13 @@ void Driver::CreateOffloadingDeviceToolChains(Compilation &C, FoundNormalizedTriples[NormalizedName] = Val; UniqueSYCLTriplesVec.push_back(TT); } + // Scanned the triples. Add the default device triple if it wasn't + // specified by the user. + if (addSYCLDefaultTriple(C, UniqueSYCLTriplesVec)) { + // set variable that the default triple was added. We want to be + // sure that user set generic -Xs* options are not applied. + C.getDriver().setSYCLDefaultTriple(true); + } } else Diag(clang::diag::warn_drv_empty_joined_argument) << SYCLTargetsValues->getAsString(C.getInputArgs()); @@ -987,8 +1013,11 @@ void Driver::CreateOffloadingDeviceToolChains(Compilation &C, else if (HasValidSYCLRuntime) // Triple for -fintelfpga is spir64_fpga-unknown-unknown-sycldevice. SYCLTargetArch = SYCLfpga ? "spir64_fpga" : "spir64"; - if (!SYCLTargetArch.empty()) + if (!SYCLTargetArch.empty()) { UniqueSYCLTriplesVec.push_back(MakeSYCLDeviceTriple(SYCLTargetArch)); + if (addSYCLDefaultTriple(C, UniqueSYCLTriplesVec)) + C.getDriver().setSYCLDefaultTriple(true); + } } // We'll need to use the SYCL and host triples as the key into // getOffloadingDeviceToolChain, because the device toolchains we're @@ -1428,7 +1457,8 @@ Compilation *Driver::BuildCompilation(ArrayRef ArgList) { const ToolChain *TC = SYCLTCRange.first->second; const toolchains::SYCLToolChain *SYCLTC = static_cast(TC); - SYCLTC->TranslateBackendTargetArgs(*TranslatedArgs, TargetArgs); + SYCLTC->TranslateBackendTargetArgs(SYCLTC->getTriple(), *TranslatedArgs, + TargetArgs); for (StringRef ArgString : TargetArgs) { if (ArgString.equals("-hardware") || ArgString.equals("-simulation")) { setFPGAEmulationMode(false); @@ -4666,6 +4696,7 @@ class OffloadingActionBuilder final { if (TT.getSubArch() == llvm::Triple::SPIRSubArch_fpga) SYCLfpgaTriple = true; } + addSYCLDefaultTriple(C, SYCLTripleList); } if (SYCLAddTargets) { for (StringRef Val : SYCLAddTargets->getValues()) { @@ -4688,6 +4719,7 @@ class OffloadingActionBuilder final { const char *SYCLTargetArch = SYCLfpga ? "spir64_fpga" : "spir64"; SYCLTripleList.push_back( C.getDriver().MakeSYCLDeviceTriple(SYCLTargetArch)); + addSYCLDefaultTriple(C, SYCLTripleList); if (SYCLfpga) SYCLfpgaTriple = true; } diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index df01fe9c93c5e..f9384c2d07e6e 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -8274,6 +8274,8 @@ void OffloadBundler::ConstructJobMultipleOutputs( if (getToolChain().getTriple().getSubArch() == llvm::Triple::SPIRSubArch_fpga && Dep.DependentOffloadKind == Action::OFK_SYCL) { + if (J++) + Triples += ','; llvm::Triple TT; TT.setArchName(types::getTypeName(InputType)); TT.setVendorName("intel"); @@ -8284,6 +8286,8 @@ void OffloadBundler::ConstructJobMultipleOutputs( } else if (getToolChain().getTriple().getSubArch() != llvm::Triple::SPIRSubArch_fpga && Dep.DependentOffloadKind == Action::OFK_Host) { + if (J++) + Triples += ','; Triples += Action::GetOffloadKindName(Dep.DependentOffloadKind); Triples += '-'; Triples += Dep.DependentToolChain->getTriple().normalize(); @@ -8442,10 +8446,10 @@ void OffloadWrapper::ConstructJob(Compilation &C, const JobAction &JA, // Only store compile/link opts in the image descriptor for the SPIR-V // target; AOT compilation has already been performed otherwise. TC.AddImpliedTargetArgs(TT, TCArgs, BuildArgs); - TC.TranslateBackendTargetArgs(TCArgs, BuildArgs); + TC.TranslateBackendTargetArgs(TT, TCArgs, BuildArgs); createArgString("-compile-opts="); BuildArgs.clear(); - TC.TranslateLinkerTargetArgs(TCArgs, BuildArgs); + TC.TranslateLinkerTargetArgs(TT, TCArgs, BuildArgs); createArgString("-link-opts="); } diff --git a/clang/lib/Driver/ToolChains/SYCL.cpp b/clang/lib/Driver/ToolChains/SYCL.cpp index 4bbf9b8f7b649..0d3223eb8b70b 100644 --- a/clang/lib/Driver/ToolChains/SYCL.cpp +++ b/clang/lib/Driver/ToolChains/SYCL.cpp @@ -387,8 +387,8 @@ void SYCL::fpga::BackendCompiler::constructOpenCLAOTCommand( llvm::Triple CPUTriple("spir64_x86_64"); TC.AddImpliedTargetArgs(CPUTriple, Args, CmdArgs); // Add the target args passed in - TC.TranslateBackendTargetArgs(Args, CmdArgs); - TC.TranslateLinkerTargetArgs(Args, CmdArgs); + TC.TranslateBackendTargetArgs(CPUTriple, Args, CmdArgs); + TC.TranslateLinkerTargetArgs(CPUTriple, Args, CmdArgs); SmallString<128> ExecPath( getToolChain().GetProgramPath(makeExeName(C, "opencl-aot"))); @@ -414,7 +414,7 @@ void SYCL::fpga::BackendCompiler::ConstructJob( const toolchains::SYCLToolChain &TC = static_cast(getToolChain()); ArgStringList TargetArgs; - TC.TranslateBackendTargetArgs(Args, TargetArgs); + TC.TranslateBackendTargetArgs(TC.getTriple(), Args, TargetArgs); // When performing emulation compilations for FPGA AOT, we want to use // opencl-aot instead of aoc. @@ -534,8 +534,8 @@ void SYCL::fpga::BackendCompiler::ConstructJob( TC.AddImpliedTargetArgs(getToolChain().getTriple(), Args, CmdArgs); // Add -Xsycl-target* options. - TC.TranslateBackendTargetArgs(Args, CmdArgs); - TC.TranslateLinkerTargetArgs(Args, CmdArgs); + TC.TranslateBackendTargetArgs(getToolChain().getTriple(), Args, CmdArgs); + TC.TranslateLinkerTargetArgs(getToolChain().getTriple(), Args, CmdArgs); // Look for -reuse-exe=XX option if (Arg *A = Args.getLastArg(options::OPT_reuse_exe_EQ)) { @@ -581,8 +581,8 @@ void SYCL::gen::BackendCompiler::ConstructJob(Compilation &C, const toolchains::SYCLToolChain &TC = static_cast(getToolChain()); TC.AddImpliedTargetArgs(getToolChain().getTriple(), Args, CmdArgs); - TC.TranslateBackendTargetArgs(Args, CmdArgs); - TC.TranslateLinkerTargetArgs(Args, CmdArgs); + TC.TranslateBackendTargetArgs(getToolChain().getTriple(), Args, CmdArgs); + TC.TranslateLinkerTargetArgs(getToolChain().getTriple(), Args, CmdArgs); SmallString<128> ExecPath( getToolChain().GetProgramPath(makeExeName(C, "ocloc"))); const char *Exec = C.getArgs().MakeArgString(ExecPath); @@ -614,8 +614,8 @@ void SYCL::x86_64::BackendCompiler::ConstructJob( static_cast(getToolChain()); TC.AddImpliedTargetArgs(getToolChain().getTriple(), Args, CmdArgs); - TC.TranslateBackendTargetArgs(Args, CmdArgs); - TC.TranslateLinkerTargetArgs(Args, CmdArgs); + TC.TranslateBackendTargetArgs(getToolChain().getTriple(), Args, CmdArgs); + TC.TranslateLinkerTargetArgs(getToolChain().getTriple(), Args, CmdArgs); SmallString<128> ExecPath( getToolChain().GetProgramPath(makeExeName(C, "opencl-aot"))); const char *Exec = C.getArgs().MakeArgString(ExecPath); @@ -765,7 +765,8 @@ void SYCLToolChain::AddImpliedTargetArgs( } void SYCLToolChain::TranslateBackendTargetArgs( - const llvm::opt::ArgList &Args, llvm::opt::ArgStringList &CmdArgs) const { + const llvm::Triple &Triple, const llvm::opt::ArgList &Args, + llvm::opt::ArgStringList &CmdArgs) const { // Handle -Xs flags. for (auto *A : Args) { // When parsing the target args, the -Xs type option applies to all @@ -775,6 +776,15 @@ void SYCLToolChain::TranslateBackendTargetArgs( // -Xs "-DFOO -DBAR" // -XsDFOO -XsDBAR // All of the above examples will pass -DFOO -DBAR to the backend compiler. + + // Do not add the -Xs to the default SYCL triple (spir64) when we have + // implied the setting along with AOT compilations. + if ((A->getOption().matches(options::OPT_Xs) || + A->getOption().matches(options::OPT_Xs_separate)) && + Triple.getSubArch() == llvm::Triple::NoSubArch && Triple.isSPIR() && + getDriver().isSYCLDefaultTripleSet()) + continue; + if (A->getOption().matches(options::OPT_Xs)) { // Take the arg and create an option out of it. CmdArgs.push_back(Args.MakeArgString(Twine("-") + A->getValue())); @@ -788,13 +798,22 @@ void SYCLToolChain::TranslateBackendTargetArgs( continue; } } + // Do not process -Xsycl-target-backend for implied spir64 for AOT. + if (Triple.getSubArch() == llvm::Triple::NoSubArch && Triple.isSPIR() && + getDriver().isSYCLDefaultTripleSet()) + return; // Handle -Xsycl-target-backend. TranslateTargetOpt(Args, CmdArgs, options::OPT_Xsycl_backend, options::OPT_Xsycl_backend_EQ); } void SYCLToolChain::TranslateLinkerTargetArgs( - const llvm::opt::ArgList &Args, llvm::opt::ArgStringList &CmdArgs) const { + const llvm::Triple &Triple, const llvm::opt::ArgList &Args, + llvm::opt::ArgStringList &CmdArgs) const { + // Do not process -Xsycl-target-linker for implied spir64 for AOT. + if (Triple.getSubArch() == llvm::Triple::NoSubArch && Triple.isSPIR() && + getDriver().isSYCLDefaultTripleSet()) + return; // Handle -Xsycl-target-linker. TranslateTargetOpt(Args, CmdArgs, options::OPT_Xsycl_linker, options::OPT_Xsycl_linker_EQ); diff --git a/clang/lib/Driver/ToolChains/SYCL.h b/clang/lib/Driver/ToolChains/SYCL.h index e6c1ab2ed3966..e767ede212b9b 100644 --- a/clang/lib/Driver/ToolChains/SYCL.h +++ b/clang/lib/Driver/ToolChains/SYCL.h @@ -151,10 +151,12 @@ class LLVM_LIBRARY_VISIBILITY SYCLToolChain : public ToolChain { void AddImpliedTargetArgs(const llvm::Triple &Triple, const llvm::opt::ArgList &Args, llvm::opt::ArgStringList &CmdArgs) const; - void TranslateBackendTargetArgs(const llvm::opt::ArgList &Args, - llvm::opt::ArgStringList &CmdArgs) const; - void TranslateLinkerTargetArgs(const llvm::opt::ArgList &Args, - llvm::opt::ArgStringList &CmdArgs) const; + void TranslateBackendTargetArgs(const llvm::Triple &Triple, + const llvm::opt::ArgList &Args, + llvm::opt::ArgStringList &CmdArgs) const; + void TranslateLinkerTargetArgs(const llvm::Triple &Triple, + const llvm::opt::ArgList &Args, + llvm::opt::ArgStringList &CmdArgs) const; bool useIntegratedAs() const override { return true; } bool isPICDefault() const override { return false; } diff --git a/clang/test/Driver/sycl-intelfpga-aoco-win.cpp b/clang/test/Driver/sycl-intelfpga-aoco-win.cpp index c96b8f2ff9028..6f16547171091 100755 --- a/clang/test/Driver/sycl-intelfpga-aoco-win.cpp +++ b/clang/test/Driver/sycl-intelfpga-aoco-win.cpp @@ -7,9 +7,9 @@ // RUN: clang-offload-wrapper -o %t-aoco.bc -host=x86_64-pc-windows-msvc -kind=sycl -target=fpga_aoco-intel-unknown-sycldevice %t.aoco // RUN: llc -filetype=obj -o %t-aoco.o %t-aoco.bc // RUN: llvm-ar crv %t_aoco.a %t.o %t2.o %t-aoco.o -// RUN: %clang_cl --target=x86_64-pc-windows-msvc -fsycl -fno-sycl-device-lib=all -fintelfpga -Xshardware %t_aoco.a %s -ccc-print-phases 2>&1 \ +// RUN: %clang_cl --target=x86_64-pc-windows-msvc -fsycl -fno-sycl-default-triple -fno-sycl-device-lib=all -fintelfpga -Xshardware %t_aoco.a %s -ccc-print-phases 2>&1 \ // RUN: | FileCheck -check-prefixes=CHK-FPGA-AOCO-PHASES-WIN %s -// RUN: %clangxx -target x86_64-pc-windows-msvc -fsycl -fno-sycl-device-lib=all -fintelfpga -Xshardware %t_aoco.a %s -ccc-print-phases 2>&1 \ +// RUN: %clangxx -target x86_64-pc-windows-msvc -fsycl -fno-sycl-default-triple -fno-sycl-device-lib=all -fintelfpga -Xshardware %t_aoco.a %s -ccc-print-phases 2>&1 \ // RUN: | FileCheck -check-prefixes=CHK-FPGA-AOCO-PHASES-WIN %s // CHK-FPGA-AOCO-PHASES-WIN: 0: input, "[[INPUTA:.+\.a]]", object, (host-sycl) // CHK-FPGA-AOCO-PHASES-WIN: 1: input, "[[INPUTSRC:.+\.cpp]]", c++, (host-sycl) @@ -41,9 +41,9 @@ // CHK-FPGA-AOCO-PHASES-WIN: 27: offload, "host-sycl (x86_64-pc-windows-msvc)" {11}, "device-sycl (spir64_fpga-unknown-unknown-sycldevice)" {26}, image /// aoco test, checking tools -// RUN: %clang_cl --target=x86_64-pc-windows-msvc -fsycl -fno-sycl-device-lib=all -fintelfpga %t_aoco.a -Xshardware -### %s 2>&1 \ +// RUN: %clang_cl --target=x86_64-pc-windows-msvc -fsycl -fno-sycl-default-triple -fno-sycl-device-lib=all -fintelfpga %t_aoco.a -Xshardware -### %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-FPGA-AOCO %s -// RUN: %clang_cl --target=x86_64-pc-windows-msvc -fsycl -fno-sycl-device-lib=all -fintelfpga %t_aoco.a -Xshardware -### %s 2>&1 \ +// RUN: %clang_cl --target=x86_64-pc-windows-msvc -fsycl -fno-sycl-default-triple -fno-sycl-device-lib=all -fintelfpga %t_aoco.a -Xshardware -### %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-FPGA-AOCO %s // CHK-FPGA-AOCO: clang-offload-bundler{{.*}} "-type=a" "-targets=sycl-spir64_fpga-unknown-unknown-sycldevice" "-inputs=[[INPUTLIB:.+\.a]]" "-outputs=[[OUTLIB:.+\.a]]" "-unbundle" // CHK-FPGA-AOCO: llvm-link{{.*}} "[[OUTLIB]]" "-o" "[[LINKEDBC:.+\.bc]]" diff --git a/clang/test/Driver/sycl-intelfpga-aoco.cpp b/clang/test/Driver/sycl-intelfpga-aoco.cpp index 2ba6edfbe2700..034a315f54557 100755 --- a/clang/test/Driver/sycl-intelfpga-aoco.cpp +++ b/clang/test/Driver/sycl-intelfpga-aoco.cpp @@ -13,7 +13,7 @@ // RUN: llc -filetype=obj -o %t-aoco_cl.o %t-aoco_cl.bc // RUN: llvm-ar crv %t_aoco.a %t.o %t2.o %t-aoco.o // RUN: llvm-ar crv %t_aoco_cl.a %t.o %t2_cl.o %t-aoco_cl.o -// RUN: %clangxx -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-device-lib=all -fintelfpga -Xshardware %t_aoco.a %s -ccc-print-phases 2>&1 \ +// RUN: %clangxx -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-default-triple -fno-sycl-device-lib=all -fintelfpga -Xshardware %t_aoco.a %s -ccc-print-phases 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-FPGA-AOCO-PHASES %s // CHK-FPGA-AOCO-PHASES: 0: input, "[[INPUTA:.+\.a]]", object, (host-sycl) // CHK-FPGA-AOCO-PHASES: 1: input, "[[INPUTCPP:.+\.cpp]]", c++, (host-sycl) @@ -45,13 +45,13 @@ // CHK-FPGA-AOCO-PHASES: 27: offload, "host-sycl (x86_64-unknown-linux-gnu)" {11}, "device-sycl (spir64_fpga-unknown-unknown-sycldevice)" {26}, image /// aoco test, checking tools -// RUN: %clangxx -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-device-lib=all -fintelfpga -Xshardware -foffload-static-lib=%t_aoco.a -### %s 2>&1 \ +// RUN: %clangxx -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-default-triple -fno-sycl-device-lib=all -fintelfpga -Xshardware -foffload-static-lib=%t_aoco.a -### %s 2>&1 \ // RUN: | FileCheck -check-prefixes=CHK-FPGA-AOCO,CHK-FPGA-AOCO-LIN %s -// RUN: %clangxx -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-device-lib=all -fintelfpga -Xshardware %t_aoco.a -### %s 2>&1 \ +// RUN: %clangxx -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-default-triple -fno-sycl-device-lib=all -fintelfpga -Xshardware %t_aoco.a -### %s 2>&1 \ // RUN: | FileCheck -check-prefixes=CHK-FPGA-AOCO,CHK-FPGA-AOCO-LIN %s -// RUN: %clang_cl -fsycl -fno-sycl-device-lib=all -fintelfpga -Xshardware -foffload-static-lib=%t_aoco_cl.a -### %s 2>&1 \ +// RUN: %clang_cl -fsycl -fno-sycl-default-triple -fno-sycl-device-lib=all -fintelfpga -Xshardware -foffload-static-lib=%t_aoco_cl.a -### %s 2>&1 \ // RUN: | FileCheck -check-prefixes=CHK-FPGA-AOCO,CHK-FPGA-AOCO-WIN %s -// RUN: %clang_cl -fsycl -fno-sycl-device-lib=all -fintelfpga -Xshardware %t_aoco_cl.a -### %s 2>&1 \ +// RUN: %clang_cl -fsycl -fno-sycl-default-triple -fno-sycl-device-lib=all -fintelfpga -Xshardware %t_aoco_cl.a -### %s 2>&1 \ // RUN: | FileCheck -check-prefixes=CHK-FPGA-AOCO,CHK-FPGA-AOCO-WIN %s // CHK-FPGA-AOCO: clang-offload-bundler{{.*}} "-type=a" "-targets=sycl-spir64_fpga-unknown-unknown-sycldevice" "-inputs=[[INPUTLIB:.+\.a]]" "-outputs=[[OUTLIB:.+\.a]]" "-unbundle" // CHK-FPGA-AOCO: llvm-link{{.*}} "[[OUTLIB]]" "-o" "[[LINKEDBC:.+\.bc]]" @@ -68,7 +68,7 @@ // CHK-FPGA-AOCO-WIN: link.exe{{.*}} "{{.*}}[[INPUTLIB]]" {{.*}} "[[FINALOBJW]]" /// aoco archive check with emulation -// RUN: %clangxx -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-device-lib=all -fintelfpga %t_aoco.a %s -ccc-print-phases 2>&1 \ +// RUN: %clangxx -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-default-triple -fno-sycl-device-lib=all -fintelfpga %t_aoco.a %s -ccc-print-phases 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-FPGA-AOCO-PHASES-EMU %s // CHK-FPGA-AOCO-PHASES-EMU: 0: input, "[[INPUTA:.+\.a]]", object, (host-sycl) // CHK-FPGA-AOCO-PHASES-EMU: 1: input, "[[INPUTCPP:.+\.cpp]]", c++, (host-sycl) @@ -102,7 +102,7 @@ // RUN: | FileCheck -check-prefixes=CHK-FPGA-AOCO-EMU,CHK-FPGA-AOCO-EMU-LIN %s // RUN: %clang_cl -fsycl -fno-sycl-device-lib=all -fintelfpga %t_aoco_cl.a -### %s 2>&1 \ // RUN: | FileCheck -check-prefixes=CHK-FPGA-AOCO-EMU,CHK-FPGA-AOCO-EMU-WIN %s -// CHK-FPGA-AOCO-EMU: clang-offload-bundler{{.*}} "-type=a" "-targets=sycl-spir64_fpga-unknown-unknown-sycldevice" "-inputs=[[INPUTLIB:.+\.a]]" "-outputs=[[OUTLIB:.+\.a]]" "-unbundle" +// CHK-FPGA-AOCO-EMU: clang-offload-bundler{{.*}} "-type=a" "-targets=sycl-spir64_fpga-unknown-unknown-sycldevice,{{.*}}" "-inputs=[[INPUTLIB:.+\.a]]" "-outputs=[[OUTLIB:.+\.a]],{{.*.a}}" "-unbundle" // CHK-FPGA-AOCO-EMU: llvm-link{{.*}} "[[OUTLIB]]" "-o" "[[LINKEDBC:.+\.bc]]" // CHK-FPGA-AOCO-EMU: sycl-post-link{{.*}} "-split-esimd"{{.*}} "-O2" "-spec-const=default" "-o" "[[SPLTABLE:.+\.table]]" "[[LINKEDBC]]" // CHK-FPGA-AOCO-EMU: file-table-tform{{.*}} "-o" "[[TABLEOUT:.+\.txt]]" "[[SPLTABLE]]" diff --git a/clang/test/Driver/sycl-intelfpga-static-lib.cpp b/clang/test/Driver/sycl-intelfpga-static-lib.cpp index 98bde770261b9..d64e686a85162 100644 --- a/clang/test/Driver/sycl-intelfpga-static-lib.cpp +++ b/clang/test/Driver/sycl-intelfpga-static-lib.cpp @@ -10,7 +10,7 @@ // RUN: llvm-ar cr %t.a %t1_bundle.o /// Check phases with static lib -// RUN: %clangxx -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-device-lib=all -fintelfpga %t.a -ccc-print-phases 2>&1 \ +// RUN: %clangxx -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-default-triple -fno-sycl-device-lib=all -fintelfpga %t.a -ccc-print-phases 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK_PHASES %s // CHECK_PHASES: 0: input, "[[INPUT:.+\.a]]", object, (host-sycl) // CHECK_PHASES: 1: linker, {0}, image, (host-sycl) diff --git a/clang/test/Driver/sycl-offload-intelfpga-emu.cpp b/clang/test/Driver/sycl-offload-intelfpga-emu.cpp index d0b21760dcb1b..1d9791b373ad8 100644 --- a/clang/test/Driver/sycl-offload-intelfpga-emu.cpp +++ b/clang/test/Driver/sycl-offload-intelfpga-emu.cpp @@ -13,7 +13,7 @@ // RUN: | FileCheck -check-prefixes=CHK-FPGA-LINK,CHK-FPGA-IMAGE %s // RUN: %clangxx -### -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-device-lib=all -fsycl-targets=spir64_fpga-unknown-unknown-sycldevice -g -fsycl-link=image %t.o -o libfoo.a 2>&1 \ // RUN: | FileCheck -check-prefixes=CHK-FPGA-LINK,CHK-FPGA-IMAGE %s -// CHK-FPGA-LINK: clang-offload-bundler{{.*}} "-type=o" "-targets=sycl-spir64_fpga-unknown-unknown-sycldevice" "-inputs=[[INPUT:.+\.o]]" "-outputs=[[OUTPUT1:.+\.o]]" "-unbundle" +// CHK-FPGA-LINK: clang-offload-bundler{{.*}} "-type=o" "-targets=sycl-spir64_fpga-unknown-unknown-sycldevice,{{.*}}" "-inputs=[[INPUT:.+\.o]]" "-outputs=[[OUTPUT1:.+\.o]],{{.*.o}}" "-unbundle" // CHK-FPGA-LINK: llvm-link{{.*}} "[[OUTPUT1]]" "-o" "[[OUTPUT2_1:.+\.bc]]" // CHK-FPGA-LINK: sycl-post-link{{.*}} "-O2" "-spec-const=default" "-o" "[[OUTPUT2:.+\.table]]" "[[OUTPUT2_1]]" // CHK-FPGA-LINK: file-table-tform{{.*}} "-o" "[[TABLEOUT:.+\.txt]]" "[[OUTPUT2]]" @@ -35,7 +35,7 @@ // RUN: | FileCheck -check-prefixes=CHK-FPGA-LINK-WIN %s // RUN: %clang_cl -### -fsycl -fintelfpga -fno-sycl-device-lib=all -fsycl-link %t.obj -o libfoo.lib 2>&1 \ // RUN: | FileCheck -check-prefixes=CHK-FPGA-LINK-WIN %s -// CHK-FPGA-LINK-WIN: clang-offload-bundler{{.*}} "-type=o" "-targets=sycl-spir64_fpga-unknown-unknown-sycldevice{{.*}}" "-inputs=[[INPUT:.+\.obj]]" "-outputs=[[OUTPUT1:.+\.obj]]" "-unbundle" +// CHK-FPGA-LINK-WIN: clang-offload-bundler{{.*}} "-type=o" "-targets=sycl-spir64_fpga-unknown-unknown-sycldevice{{.*}}" "-inputs=[[INPUT:.+\.obj]]" "-outputs=[[OUTPUT1:.+\.obj]],{{.*.obj}}" "-unbundle" // CHK-FPGA-LINK-WIN: llvm-link{{.*}} "[[OUTPUT1]]" "-o" "[[OUTPUT2_1:.+\.bc]]" // CHK-FPGA-LINK-WIN: sycl-post-link{{.*}} "-O2" "-spec-const=default" "-o" "[[OUTPUT2:.+\.table]]" "[[OUTPUT2_1]]" // CHK-FPGA-LINK-WIN: file-table-tform{{.*}} "-o" "[[TABLEOUT:.+\.txt]]" "[[OUTPUT2]]" @@ -61,7 +61,7 @@ // RUN: %clangxx -### -target x86_64-unknown-linux-gnu -fsycl -fintelfpga -fsycl-link=early %t-aocr.a 2>&1 \ // RUN: | FileCheck -check-prefixes=CHK-FPGA-LINK-LIB,CHK-FPGA-LINK-LIB-EARLY %s // CHK-FPGA-LINK-LIB: clang-offload-bundler{{.*}} "-type=ao" "-targets=sycl-fpga_aocr_emu-intel-unknown-sycldevice" "-inputs={{.*}}" "-check-section" -// CHK-FPGA-LINK-LIB: clang-offload-bundler{{.*}} "-type=aocr" "-targets=sycl-fpga_aocr_emu-intel-unknown-sycldevice" "-inputs=[[INPUT:.+\.a]]" "-outputs=[[OUTPUT2:.+\.aocr]]" "-unbundle" +// CHK-FPGA-LINK-LIB: clang-offload-bundler{{.*}} "-type=aocr" "-targets=sycl-fpga_aocr_emu-intel-unknown-sycldevice{{.*}}" "-inputs=[[INPUT:.+\.a]]" "-outputs=[[OUTPUT2:.+\.aocr]],{{.*.aocr}}" "-unbundle" // CHK-FPGA-LINK-LIB-IMAGE: llvm-foreach{{.*}} "--out-ext=aocx" "--in-file-list=[[OUTPUT2]]" "--in-replace=[[OUTPUT2]]" "--out-file-list=[[OUTPUT3:.+\.aocx]]" "--out-replace=[[OUTPUT3]]" "--" "{{.*}}opencl-aot{{.*}} "-device=fpga_fast_emu" "-spv=[[OUTPUT2]]" "-ir=[[OUTPUT3]]" "--bo=-g" // CHK-FPGA-LINK-LIB-IMAGE: file-table-tform{{.*}} "-rename=0,Code" "-o" "[[OUTPUT4:.+\.txt]]" "[[OUTPUT3]]" // CHK-FPGA-LINK-LIB-IMAGE: clang-offload-wrapper{{.*}} "-host=x86_64-unknown-linux-gnu" "--emit-reg-funcs=0" "-target=fpga_aocx_emu-intel-unknown-sycldevice" "-kind=sycl" "-batch" "[[OUTPUT4]]" @@ -84,12 +84,12 @@ // RUN: touch %t2.o // RUN: %clangxx -### -target x86_64-unknown-linux-gnu -fno-sycl-device-lib=all -fsycl -fintelfpga %t-aocr.a %t2.o 2>&1 \ // RUN: | FileCheck -check-prefixes=CHK-FPGA %s -// CHK-FPGA: clang-offload-bundler{{.*}} "-type=aocr" "-targets=sycl-fpga_aocr_emu-intel-unknown-sycldevice" "-inputs=[[INPUT:.+\.a]]" "-outputs=[[OUTPUT2:.+\.aocr]]" "-unbundle" +// CHK-FPGA: clang-offload-bundler{{.*}} "-type=aocr" "-targets=sycl-fpga_aocr_emu-intel-unknown-sycldevice{{.*}}" "-inputs=[[INPUT:.+\.a]]" "-outputs=[[OUTPUT2:.+\.aocr]],{{.*.aocr}}" "-unbundle" // CHK-FPGA: llvm-foreach{{.*}} "--out-ext=aocx" "--in-file-list=[[OUTPUT2]]" "--in-replace=[[OUTPUT2]]" "--out-file-list=[[OUTPUT3:.+\.aocx]]" "--out-replace=[[OUTPUT3]]" "--" "{{.*}}opencl-aot{{.*}} "-device=fpga_fast_emu" "-spv=[[OUTPUT2]]" "-ir=[[OUTPUT3]]" "--bo=-g" // CHK-FPGA: file-table-tform{{.*}} "-rename=0,Code" "-o" "[[OUTPUT4:.+\.txt]]" "[[OUTPUT3]]" // CHK-FPGA: clang-offload-wrapper{{.*}} "-o=[[OUTPUT_AOCX_BC:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" "-target=spir64_fpga" "-kind=sycl" "-batch" "[[OUTPUT4]]" // CHK-FPGA: llc{{.*}} "-filetype=obj" "-o" "[[FINALLINK:.+\.o]]" "[[OUTPUT_AOCX_BC]]" -// CHK-FPGA: clang-offload-bundler{{.*}} "-type=o" "-targets=host-x86_64-unknown-linux-gnu,sycl-spir64_fpga-unknown-unknown-sycldevice" {{.*}} "-outputs=[[FINALLINK2:.+\.o]],[[OUTPUT1:.+\.o]]" "-unbundle" +// CHK-FPGA: clang-offload-bundler{{.*}} "-type=o" "-targets=host-x86_64-unknown-linux-gnu,sycl-spir64_fpga-unknown-unknown-sycldevice,sycl-spir64-unknown-unknown-sycldevice" {{.*}} "-outputs=[[FINALLINK2:.+\.o]],[[OUTPUT1:.+\.o]],{{.*.o}}" "-unbundle" // CHK-FPGA: llvm-link{{.*}} "[[OUTPUT1]]" "-o" "[[OUTPUT2_BC:.+\.bc]]" // CHK-FPGA: sycl-post-link{{.*}} "-O2" "-spec-const=default" "-o" "[[OUTPUT2:.+\.table]]" "[[OUTPUT2_BC]]" // CHK-FPGA: file-table-tform{{.*}} "-o" "[[TABLEOUT:.+\.txt]]" "[[OUTPUT2]]" @@ -110,9 +110,9 @@ // RUN: clang-offload-wrapper -o %t-aocx.bc -host=x86_64-unknown-linux-gnu -kind=sycl -target=fpga_aocx_emu-intel-unknown-sycldevice %t.aocx // RUN: llc -filetype=obj -o %t-aocx.o %t-aocx.bc // RUN: llvm-ar crv %t_aocx.a %t.o %t-aocx.o -// RUN: %clangxx -target x86_64-unknown-linux-gnu -fsycl -fintelfpga %t_aocx.a -ccc-print-phases 2>&1 \ +// RUN: %clangxx -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-default-triple -fintelfpga %t_aocx.a -ccc-print-phases 2>&1 \ // RUN: | FileCheck -check-prefixes=CHK-FPGA-AOCX-PHASES %s -// RUN: %clang_cl -fsycl -fintelfpga %t_aocx.a -ccc-print-phases 2>&1 \ +// RUN: %clang_cl -fsycl -fno-sycl-default-triple -fintelfpga %t_aocx.a -ccc-print-phases 2>&1 \ // RUN: | FileCheck -check-prefixes=CHK-FPGA-AOCX-PHASES %s // CHK-FPGA-AOCX-PHASES: 0: input, "{{.*}}", fpga_aocx_emu, (host-sycl) // CHK-FPGA-AOCX-PHASES: 1: linker, {0}, image, (host-sycl) @@ -125,7 +125,7 @@ // RUN: | FileCheck -check-prefixes=CHK-FPGA-AOCX,CHK-FPGA-AOCX-LIN %s // RUN: %clang_cl -fsycl -fintelfpga %t_aocx.a -### 2>&1 \ // RUN: | FileCheck -check-prefixes=CHK-FPGA-AOCX,CHK-FPGA-AOCX-WIN %s -// CHK-FPGA-AOCX: clang-offload-bundler{{.*}} "-type=aocx" "-targets=sycl-fpga_aocx_emu-intel-unknown-sycldevice" "-inputs=[[LIBINPUT:.+\.a]]" "-outputs=[[BUNDLEOUT:.+\.aocx]]" "-unbundle" +// CHK-FPGA-AOCX: clang-offload-bundler{{.*}} "-type=aocx" "-targets=sycl-fpga_aocx_emu-intel-unknown-sycldevice,{{.*}}" "-inputs=[[LIBINPUT:.+\.a]]" "-outputs=[[BUNDLEOUT:.+\.aocx]],{{.*.aocx}}" "-unbundle" // CHK-FPGA-AOCX: file-table-tform{{.*}} "-rename=0,Code" "-o" "[[TABLEOUT:.+\.txt]]" "[[BUNDLEOUT]]" // CHK-FPGA-AOCX: clang-offload-wrapper{{.*}} "-o=[[WRAPOUT:.+\.bc]]" {{.*}} "-target=spir64_fpga" "-kind=sycl" "-batch" "[[TABLEOUT]]" // CHK-FPGA-AOCX-LIN: llc{{.*}} "-filetype=obj" "-o" "[[LLCOUT:.+\.o]]" "[[WRAPOUT]]" @@ -139,7 +139,7 @@ // RUN: | FileCheck -check-prefixes=CHK-FPGA-AOCX-SRC,CHK-FPGA-AOCX-SRC-LIN %s // RUN: %clang_cl -fsycl -fno-sycl-device-lib=all -fintelfpga %s %t_aocx.a -### 2>&1 \ // RUN: | FileCheck -check-prefixes=CHK-FPGA-AOCX-SRC,CHK-FPGA-AOCX-SRC-WIN %s -// CHK-FPGA-AOCX-SRC: clang-offload-bundler{{.*}} "-type=aocx" "-targets=sycl-fpga_aocx_emu-intel-unknown-sycldevice" "-inputs=[[LIBINPUT:.+\.a]]" "-outputs=[[BUNDLEOUT:.+\.aocx]]" "-unbundle" +// CHK-FPGA-AOCX-SRC: clang-offload-bundler{{.*}} "-type=aocx" "-targets=sycl-fpga_aocx_emu-intel-unknown-sycldevice,{{.*}}" "-inputs=[[LIBINPUT:.+\.a]]" "-outputs=[[BUNDLEOUT:.+\.aocx]],{{.*.aocx}}" "-unbundle" // CHK-FPGA-AOCX-SRC: file-table-tform{{.*}} "-rename=0,Code" "-o" "[[TABLEOUT:.+\.txt]]" "[[BUNDLEOUT]]" // CHK-FPGA-AOCX-SRC: clang-offload-wrapper{{.*}} "-o=[[WRAPOUT:.+\.bc]]" {{.*}} "-target=spir64_fpga" "-kind=sycl" "-batch" "[[TABLEOUT]]" // CHK-FPGA-AOCX-SRC: llc{{.*}} "-filetype=obj" "-o" "[[LLCOUT:.+\.(o|obj)]]" "[[WRAPOUT]]" @@ -162,13 +162,13 @@ // RUN: | FileCheck -check-prefixes=CHK-FPGA-AOCX-OBJ,CHK-FPGA-AOCX-OBJ-LIN %s // RUN: %clang_cl -fsycl -fno-sycl-device-lib=all -fintelfpga %t.o %t_aocx.a -### 2>&1 \ // RUN: | FileCheck -check-prefixes=CHK-FPGA-AOCX-OBJ,CHK-FPGA-AOCX-OBJ-WIN %s -// CHK-FPGA-AOCX-OBJ: clang-offload-bundler{{.*}} "-type=aocx" "-targets=sycl-fpga_aocx_emu-intel-unknown-sycldevice" "-inputs=[[LIBINPUT:.+\.a]]" "-outputs=[[BUNDLEOUT:.+\.aocx]]" "-unbundle" +// CHK-FPGA-AOCX-OBJ: clang-offload-bundler{{.*}} "-type=aocx" "-targets=sycl-fpga_aocx_emu-intel-unknown-sycldevice,{{.*}}" "-inputs=[[LIBINPUT:.+\.a]]" "-outputs=[[BUNDLEOUT:.+\.aocx]],{{.*.aocx}}" "-unbundle" // CHK-FPGA-AOCX-OBJ: file-table-tform{{.*}} "-rename=0,Code" "-o" "[[TABLEOUT:.+\.txt]]" "[[BUNDLEOUT]]" // CHK-FPGA-AOCX-OBJ: clang-offload-wrapper{{.*}} "-o=[[WRAPOUT:.+\.bc]]" {{.*}} "-target=spir64_fpga" "-kind=sycl" "-batch" "[[TABLEOUT]]" // CHK-FPGA-AOCX-OBJ: llc{{.*}} "-filetype=obj" "-o" "[[LLCOUT:.+\.(o|obj)]]" "[[WRAPOUT]]" -// CHK-FPGA-AOCX-OBJ: clang-offload-bundler{{.*}} "-type=o" {{.*}} "-outputs=[[HOSTOBJ:.+\.(o|obj)]],[[DEVICEOBJ:.+\.(o|obj)]]" "-unbundle" +// CHK-FPGA-AOCX-OBJ: clang-offload-bundler{{.*}} "-type=o" {{.*}} "-outputs=[[HOSTOBJ:.+\.(o|obj)]],[[DEVICEOBJ:.+\.(o|obj)]],{{.*.(o|obj)}}" "-unbundle" // CHK-FPGA-AOCX-OBJ: llvm-link{{.*}} "[[DEVICEOBJ]]" "-o" "[[LLVMLINKOUT:.+\.bc]]" "--suppress-warnings" -// CHK-FPGA-AOCX-OBJ: sycl-post-link{{.*}} "-O2" "-spec-const=default" "-o" "[[OUTPUT2:.+\.table]]" "[[LLVMLINKOUT]]" +// CHK-FPGA-AOCX-OBJ: sycl-post-link{{.*}} "-O2" "-spec-const={{.*}}" "-o" "[[OUTPUT2:.+\.table]]" "[[LLVMLINKOUT]]" // CHK-FPGA-AOCX-OBJ: file-table-tform{{.*}} "-o" "[[TABLEOUT:.+\.txt]]" "[[OUTPUT2]]" // CHK-FPGA-AOCX-OBJ: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.txt]]" "-spirv-max-version={{.*}}"{{.*}} "[[TABLEOUT]]" // CHK-FPGA-AOCX-OBJ: opencl-aot{{.*}} "-device=fpga_fast_emu" "-spv=[[OUTPUT3]]" "-ir=[[OUTPUT4:.+\.aocx]]" "--bo=-g" @@ -180,9 +180,9 @@ /// -fintelfpga -fsycl-link from source // RUN: touch %t.cpp -// RUN: %clangxx -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-device-lib=all -fintelfpga -fsycl-link=early %t.cpp -ccc-print-phases 2>&1 \ +// RUN: %clangxx -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-default-triple -fno-sycl-device-lib=all -fintelfpga -fsycl-link=early %t.cpp -ccc-print-phases 2>&1 \ // RUN: | FileCheck -check-prefixes=CHK-FPGA-LINK-SRC %s -// RUN: %clang_cl --target=x86_64-unknown-linux-gnu -fsycl -fno-sycl-device-lib=all -fintelfpga -fsycl-link=early %t.cpp -ccc-print-phases 2>&1 \ +// RUN: %clang_cl --target=x86_64-unknown-linux-gnu -fsycl -fno-sycl-default-triple -fno-sycl-device-lib=all -fintelfpga -fsycl-link=early %t.cpp -ccc-print-phases 2>&1 \ // RUN: | FileCheck -check-prefixes=CHK-FPGA-LINK-SRC %s // CHK-FPGA-LINK-SRC: 0: input, "[[INPUT:.+\.cpp]]", c++, (host-sycl) // CHK-FPGA-LINK-SRC: 1: append-footer, {0}, c++, (host-sycl) diff --git a/clang/test/Driver/sycl-offload-intelfpga.cpp b/clang/test/Driver/sycl-offload-intelfpga.cpp index 1a035f866b5e7..e064f04f47e51 100644 --- a/clang/test/Driver/sycl-offload-intelfpga.cpp +++ b/clang/test/Driver/sycl-offload-intelfpga.cpp @@ -47,7 +47,7 @@ // RUN: %clangxx -### -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-device-lib=all -fsycl-targets=spir64_fpga-unknown-unknown-sycldevice -fsycl-link=image -Xshardware %t.o -o libfoo.a 2>&1 \ // RUN: | FileCheck -check-prefixes=CHK-FPGA-LINK,CHK-FPGA-IMAGE %s // CHK-FPGA-LINK-NOT: clang-offload-bundler{{.*}} "-check-section" -// CHK-FPGA-LINK: clang-offload-bundler{{.*}} "-type=o" "-targets=sycl-spir64_fpga-unknown-unknown-sycldevice" "-inputs=[[INPUT:.+\.o]]" "-outputs=[[OUTPUT1:.+\.o]]" "-unbundle" +// CHK-FPGA-LINK: clang-offload-bundler{{.*}} "-type=o" "-targets=sycl-spir64_fpga-unknown-unknown-sycldevice,{{.*}}" "-inputs=[[INPUT:.+\.o]]" "-outputs=[[OUTPUT1:.+\.o]],{{.*.o}}" "-unbundle" // CHK-FPGA-LINK-NOT: clang-offload-bundler{{.*}} // CHK-FPGA-LINK: llvm-link{{.*}} "[[OUTPUT1]]" "-o" "[[OUTPUT2_1:.+\.bc]]" // CHK-FPGA-LINK: sycl-post-link{{.*}} "-O2" "-spec-const=default" "-o" "[[OUTPUT2:.+\.table]]" "[[OUTPUT2_1]]" @@ -80,7 +80,7 @@ // RUN: | FileCheck -check-prefixes=CHK-FPGA-LINK-WIN %s // RUN: %clang_cl -### -fsycl -fintelfpga -fno-sycl-device-lib=all -fsycl-link -Xshardware %t.obj -o libfoo.lib 2>&1 \ // RUN: | FileCheck -check-prefixes=CHK-FPGA-LINK-WIN %s -// CHK-FPGA-LINK-WIN: clang-offload-bundler{{.*}} "-type=o" "-targets=sycl-spir64_fpga-unknown-unknown-sycldevice{{.*}}" "-inputs=[[INPUT:.+\.obj]]" "-outputs=[[OUTPUT1:.+\.obj]]" "-unbundle" +// CHK-FPGA-LINK-WIN: clang-offload-bundler{{.*}} "-type=o" "-targets=sycl-spir64_fpga-unknown-unknown-sycldevice{{.*}}" "-inputs=[[INPUT:.+\.obj]]" "-outputs=[[OUTPUT1:.+\.obj]],{{.*.obj}}" "-unbundle" // CHK-FPGA-LINK-WIN-NOT: clang-offload-bundler{{.*}} // CHK-FPGA-LINK-WIN: llvm-link{{.*}} "[[OUTPUT1]]" "-o" "[[OUTPUT2_1:.+\.bc]]" // CHK-FPGA-LINK-WIN: sycl-post-link{{.*}} "-O2" "-spec-const=default" "-o" "[[OUTPUT2:.+\.table]]" "[[OUTPUT2_1]]" @@ -107,7 +107,7 @@ // RUN: | FileCheck -check-prefixes=CHK-FPGA-LINK-LIB,CHK-FPGA-LINK-LIB-EARLY %s // CHK-FPGA-LINK-LIB: clang-offload-bundler{{.*}} "-type=ao" "-targets=sycl-fpga_aocx-intel-unknown-sycldevice" "-inputs={{.*}}" "-check-section" // CHK-FPGA-LINK-LIB: clang-offload-bundler{{.*}} "-type=ao" "-targets=sycl-fpga_aocr-intel-unknown-sycldevice" "-inputs={{.*}}" "-check-section" -// CHK-FPGA-LINK-LIB: clang-offload-bundler{{.*}} "-type=aocr" "-targets=sycl-fpga_aocr-intel-unknown-sycldevice" "-inputs=[[INPUT:.+\.a]]" "-outputs=[[OUTPUT2:.+\.aocr]]" "-unbundle" +// CHK-FPGA-LINK-LIB: clang-offload-bundler{{.*}} "-type=aocr" "-targets=sycl-fpga_aocr-intel-unknown-sycldevice,{{.*}}" "-inputs=[[INPUT:.+\.a]]" "-outputs=[[OUTPUT2:.+\.aocr]],{{.*.aocr}}" "-unbundle" // CHK-FPGA-LINK-LIB-IMAGE: llvm-foreach{{.*}} "--out-ext=aocx" "--in-file-list=[[OUTPUT2]]" "--in-replace=[[OUTPUT2]]" "--out-file-list=[[OUTPUT3:.+\.aocx]]" "--out-replace=[[OUTPUT3]]" "--out-increment={{.*}}-aocr.prj" "--" "{{.*}}aoc{{.*}}" "-o" "[[OUTPUT3]]" "[[OUTPUT2]]" "-sycl" "-output-report-folder={{.*}}-aocr.prj" "-g" // CHK-FPGA-LINK-LIB-IMAGE: file-table-tform{{.*}} "-rename=0,Code" "-o" "[[OUTPUT4:.+\.txt]]" "[[OUTPUT3]]" // CHK-FPGA-LINK-LIB-IMAGE: clang-offload-wrapper{{.*}} "-host=x86_64-unknown-linux-gnu" "--emit-reg-funcs=0" "-target=fpga_aocx-intel-unknown-sycldevice" "-kind=sycl" "-batch" "[[OUTPUT4]]" @@ -140,12 +140,12 @@ // RUN: touch %t2.o // RUN: %clangxx -### -target x86_64-unknown-linux-gnu -fno-sycl-device-lib=all -fsycl -fintelfpga -Xshardware %t-aocr.a %t2.o 2>&1 \ // RUN: | FileCheck -check-prefixes=CHK-FPGA %s -// CHK-FPGA: clang-offload-bundler{{.*}} "-type=aocr" "-targets=sycl-fpga_aocr-intel-unknown-sycldevice" "-inputs=[[INPUT:.+\.a]]" "-outputs=[[OUTPUT2:.+\.aocr]]" "-unbundle" +// CHK-FPGA: clang-offload-bundler{{.*}} "-type=aocr" "-targets=sycl-fpga_aocr-intel-unknown-sycldevice,{{.*}}" "-inputs=[[INPUT:.+\.a]]" "-outputs=[[OUTPUT2:.+\.aocr]],{{.*.aocr}}" "-unbundle" // CHK-FPGA: llvm-foreach{{.*}} "--out-ext=aocx" "--in-file-list=[[OUTPUT2]]" "--in-replace=[[OUTPUT2]]" "--out-file-list=[[OUTPUT3:.+\.aocx]]" "--out-replace=[[OUTPUT3]]" "--out-increment={{.*}}" "--" "{{.*}}aoc{{.*}}" "-o" "[[OUTPUT3]]" "[[OUTPUT2]]" "-sycl" {{.*}} "-g" // CHK-FPGA: file-table-tform{{.*}} "-rename=0,Code" "-o" "[[OUTPUT4:.+\.txt]]" "[[OUTPUT3]]" // CHK-FPGA: clang-offload-wrapper{{.*}} "-o=[[OUTPUT_AOCX_BC:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" "-target=spir64_fpga" "-kind=sycl" "-batch" "[[OUTPUT4]]" // CHK-FPGA: llc{{.*}} "-filetype=obj" "-o" "[[FINALLINK:.+\.o]]" "[[OUTPUT_AOCX_BC]]" -// CHK-FPGA: clang-offload-bundler{{.*}} "-type=o" "-targets=host-x86_64-unknown-linux-gnu,sycl-spir64_fpga-unknown-unknown-sycldevice" {{.*}} "-outputs=[[FINALLINK2:.+\.o]],[[OUTPUT1:.+\.o]]" "-unbundle" +// CHK-FPGA: clang-offload-bundler{{.*}} "-type=o" "-targets=host-x86_64-unknown-linux-gnu,sycl-spir64_fpga-unknown-unknown-sycldevice,{{.*}}" {{.*}} "-outputs=[[FINALLINK2:.+\.o]],[[OUTPUT1:.+\.o]],{{.*.o}}" "-unbundle" // CHK-FPGA: llvm-link{{.*}} "[[OUTPUT1]]" "-o" "[[OUTPUT2_BC:.+\.bc]]" // CHK-FPGA: sycl-post-link{{.*}} "-O2" "-spec-const=default" "-o" "[[OUTPUT3_TABLE:.+\.table]]" "[[OUTPUT2_BC]]" // CHK-FPGA: file-table-tform{{.*}} "-o" "[[TABLEOUT:.+\.txt]]" "[[OUTPUT3_TABLE]]" @@ -172,9 +172,9 @@ // RUN: clang-offload-wrapper -o %t-aocx.bc -host=x86_64-unknown-linux-gnu -kind=sycl -target=fpga_aocx-intel-unknown-sycldevice %t.aocx // RUN: llc -filetype=obj -o %t-aocx.o %t-aocx.bc // RUN: llvm-ar crv %t_aocx.a %t.o %t-aocx.o -// RUN: %clangxx -target x86_64-unknown-linux-gnu -Xshardware -fsycl -fintelfpga %t_aocx.a -ccc-print-phases 2>&1 \ +// RUN: %clangxx -target x86_64-unknown-linux-gnu -Xshardware -fsycl -fno-sycl-default-triple -fintelfpga %t_aocx.a -ccc-print-phases 2>&1 \ // RUN: | FileCheck -check-prefixes=CHK-FPGA-AOCX-PHASES %s -// RUN: %clang_cl --target=x86_64-pc-windows-msvc -Xshardware -fsycl -fintelfpga %t_aocx.a -ccc-print-phases 2>&1 \ +// RUN: %clang_cl --target=x86_64-pc-windows-msvc -Xshardware -fsycl -fno-sycl-default-triple -fintelfpga %t_aocx.a -ccc-print-phases 2>&1 \ // RUN: | FileCheck -check-prefixes=CHK-FPGA-AOCX-PHASES %s // CHK-FPGA-AOCX-PHASES: 0: input, "{{.*}}", fpga_aocx, (host-sycl) // CHK-FPGA-AOCX-PHASES: 1: linker, {0}, image, (host-sycl) @@ -187,7 +187,7 @@ // RUN: | FileCheck -check-prefixes=CHK-FPGA-AOCX,CHK-FPGA-AOCX-LIN %s // RUN: %clang_cl -fsycl -fintelfpga -Xshardware %t_aocx.a -### 2>&1 \ // RUN: | FileCheck -check-prefixes=CHK-FPGA-AOCX,CHK-FPGA-AOCX-WIN %s -// CHK-FPGA-AOCX: clang-offload-bundler{{.*}} "-type=aocx" "-targets=sycl-fpga_aocx-intel-unknown-sycldevice" "-inputs=[[LIBINPUT:.+\.a]]" "-outputs=[[BUNDLEOUT:.+\.aocx]]" "-unbundle" +// CHK-FPGA-AOCX: clang-offload-bundler{{.*}} "-type=aocx" "-targets=sycl-fpga_aocx-intel-unknown-sycldevice,{{.*}}" "-inputs=[[LIBINPUT:.+\.a]]" "-outputs=[[BUNDLEOUT:.+\.aocx]],{{.*.aocx}}" "-unbundle" // CHK-FPGA-AOCX: file-table-tform{{.*}} "-rename=0,Code" "-o" "[[TABLEOUT:.+\.txt]]" "[[BUNDLEOUT]]" // CHK-FPGA-AOCX: clang-offload-wrapper{{.*}} "-o=[[WRAPOUT:.+\.bc]]" {{.*}} "-target=spir64_fpga" "-kind=sycl" "-batch" "[[TABLEOUT]]" // CHK-FPGA-AOCX-LIN: llc{{.*}} "-filetype=obj" "-o" "[[LLCOUT:.+\.o]]" "[[WRAPOUT]]" @@ -201,7 +201,7 @@ // RUN: | FileCheck -check-prefixes=CHK-FPGA-AOCX-SRC,CHK-FPGA-AOCX-SRC-LIN %s // RUN: %clang_cl -fsycl -fno-sycl-device-lib=all -Xshardware -fintelfpga %s %t_aocx.a -### 2>&1 \ // RUN: | FileCheck -check-prefixes=CHK-FPGA-AOCX-SRC,CHK-FPGA-AOCX-SRC-WIN %s -// CHK-FPGA-AOCX-SRC: clang-offload-bundler{{.*}} "-type=aocx" "-targets=sycl-fpga_aocx-intel-unknown-sycldevice" "-inputs=[[LIBINPUT:.+\.a]]" "-outputs=[[BUNDLEOUT:.+\.aocx]]" "-unbundle" +// CHK-FPGA-AOCX-SRC: clang-offload-bundler{{.*}} "-type=aocx" "-targets=sycl-fpga_aocx-intel-unknown-sycldevice,{{.*}}" "-inputs=[[LIBINPUT:.+\.a]]" "-outputs=[[BUNDLEOUT:.+\.aocx]],{{.*.aocx}}" "-unbundle" // CHK-FPGA-AOCX-SRC: file-table-tform{{.*}} "-rename=0,Code" "-o" "[[TABLEOUT:.+\.txt]]" "[[BUNDLEOUT]]" // CHK-FPGA-AOCX-SRC: clang-offload-wrapper{{.*}} "-o=[[WRAPOUT:.+\.bc]]" {{.*}} "-target=spir64_fpga" "-kind=sycl" "-batch" "[[TABLEOUT]]" // CHK-FPGA-AOCX-SRC: llc{{.*}} "-filetype=obj" "-o" "[[LLCOUT:.+\.(o|obj)]]" "[[WRAPOUT]]" @@ -224,11 +224,11 @@ // RUN: | FileCheck -check-prefixes=CHK-FPGA-AOCX-OBJ,CHK-FPGA-AOCX-OBJ-LIN %s // RUN: %clang_cl -fsycl -fno-sycl-device-lib=all -fintelfpga -Xshardware %t.o %t_aocx.a -### 2>&1 \ // RUN: | FileCheck -check-prefixes=CHK-FPGA-AOCX-OBJ,CHK-FPGA-AOCX-OBJ-WIN %s -// CHK-FPGA-AOCX-OBJ: clang-offload-bundler{{.*}} "-type=aocx" "-targets=sycl-fpga_aocx-intel-unknown-sycldevice" "-inputs=[[LIBINPUT:.+\.a]]" "-outputs=[[BUNDLEOUT:.+\.aocx]]" "-unbundle" +// CHK-FPGA-AOCX-OBJ: clang-offload-bundler{{.*}} "-type=aocx" "-targets=sycl-fpga_aocx-intel-unknown-sycldevice,{{.*}}" "-inputs=[[LIBINPUT:.+\.a]]" "-outputs=[[BUNDLEOUT:.+\.aocx]],{{.*.aocx}}" "-unbundle" // CHK-FPGA-AOCX-OBJ: file-table-tform{{.*}} "-rename=0,Code" "-o" "[[TABLEOUT:.+\.txt]]" "[[BUNDLEOUT]]" // CHK-FPGA-AOCX-OBJ: clang-offload-wrapper{{.*}} "-o=[[WRAPOUT:.+\.bc]]" {{.*}} "-target=spir64_fpga" "-kind=sycl" "-batch" "[[TABLEOUT]]" // CHK-FPGA-AOCX-OBJ: llc{{.*}} "-filetype=obj" "-o" "[[LLCOUT:.+\.(o|obj)]]" "[[WRAPOUT]]" -// CHK-FPGA-AOCX-OBJ: clang-offload-bundler{{.*}} "-type=o" {{.*}} "-outputs=[[HOSTOBJ:.+\.(o|obj)]],[[DEVICEOBJ:.+\.(o|obj)]]" "-unbundle" +// CHK-FPGA-AOCX-OBJ: clang-offload-bundler{{.*}} "-type=o" {{.*}} "-outputs=[[HOSTOBJ:.+\.(o|obj)]],[[DEVICEOBJ:.+\.(o|obj)]],{{.*.(o|obj)}}" "-unbundle" // CHK-FPGA-AOCX-OBJ: llvm-link{{.*}} "[[DEVICEOBJ]]" "-o" "[[LLVMLINKOUT:.+\.bc]]" "--suppress-warnings" // CHK-FPGA-AOCX-OBJ: sycl-post-link{{.*}} "-O2" "-spec-const=default" "-o" "[[POSTLINKOUT:.+\.table]]" "[[LLVMLINKOUT]] // CHK-FPGA-AOCX-OBJ: file-table-tform{{.*}} "-o" "[[TABLEOUT:.+\.txt]]" "[[POSTLINKOUT]]" @@ -242,9 +242,9 @@ /// -fintelfpga -fsycl-link from source // RUN: touch %t.cpp -// RUN: %clangxx -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-device-lib=all -fintelfpga -fsycl-link=early %t.cpp -ccc-print-phases 2>&1 \ +// RUN: %clangxx -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-default-triple -fno-sycl-device-lib=all -fintelfpga -fsycl-link=early %t.cpp -ccc-print-phases 2>&1 \ // RUN: | FileCheck -check-prefixes=CHK-FPGA-LINK-SRC %s -// RUN: %clang_cl --target=x86_64-unknown-linux-gnu -fsycl -fno-sycl-device-lib=all -fintelfpga -fsycl-link=early %t.cpp -ccc-print-phases 2>&1 \ +// RUN: %clang_cl --target=x86_64-unknown-linux-gnu -fsycl -fno-sycl-default-triple -fno-sycl-device-lib=all -fintelfpga -fsycl-link=early %t.cpp -ccc-print-phases 2>&1 \ // RUN: | FileCheck -check-prefixes=CHK-FPGA-LINK-SRC %s // CHK-FPGA-LINK-SRC: 0: input, "[[INPUT:.+\.cpp]]", c++, (host-sycl) // CHK-FPGA-LINK-SRC: 1: append-footer, {0}, c++, (host-sycl) @@ -303,9 +303,9 @@ // CHK-FPGA-DEP-FILES-HOST: clang{{.*}} "-fsycl-is-host"{{.*}} "-dependency-file" /// -fintelfpga dependency file generation test to object -// RUN: %clangxx -### -fsycl -fintelfpga -target x86_64-unknown-linux-gnu %t-1.cpp %t-2.cpp -c 2>&1 \ +// RUN: %clangxx -### -fsycl -fno-sycl-default-triple -fintelfpga -target x86_64-unknown-linux-gnu %t-1.cpp %t-2.cpp -c 2>&1 \ // RUN: | FileCheck -check-prefixes=CHK-FPGA-DEP-FILES2,CHK-FPGA-DEP-FILES2-LIN %s -// RUN: %clang_cl -### -fsycl -fintelfpga --target=x86_64-pc-windows-msvc %t-1.cpp %t-2.cpp -c 2>&1 \ +// RUN: %clang_cl -### -fsycl -fno-sycl-default-triple -fintelfpga --target=x86_64-pc-windows-msvc %t-1.cpp %t-2.cpp -c 2>&1 \ // RUN: | FileCheck -check-prefixes=CHK-FPGA-DEP-FILES2,CHK-FPGA-DEP-FILES2-WIN %s // CHK-FPGA-DEP-FILES2: clang{{.*}} "-dependency-file" "[[INPUT1:.+\.d]]" // CHK-FPGA-DEP-FILES2-LIN: clang-offload-bundler{{.*}} "-type=o" "-targets=sycl-spir64_fpga-unknown-unknown-sycldevice,host-x86_64-unknown-linux-gnu,sycl-fpga_dep" {{.*}} "-inputs={{.*}}.bc,{{.*}}.o,[[INPUT1]]" @@ -316,11 +316,11 @@ /// -fintelfpga dependency file test to object with output designator // RUN: touch %t-1.cpp -// RUN: %clangxx -### -target x86_64-unknown-linux-gnu -fsycl -fintelfpga %t-1.cpp -c -o dummy.o 2>&1 \ +// RUN: %clangxx -### -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-default-triple -fintelfpga %t-1.cpp -c -o dummy.o 2>&1 \ // RUN: | FileCheck -check-prefixes=CHK-FPGA-DEP-FILES3,CHK-FPGA-DEP-FILES3-LIN %s -// RUN: %clangxx -### -target x86_64-unknown-linux-gnu -fsycl -fintelfpga %t-1.cpp -c -MMD -MF"dummy.d" 2>&1 \ +// RUN: %clangxx -### -target x86_64-unknown-linux-gnu -fsycl -fno-sycl-default-triple -fintelfpga %t-1.cpp -c -MMD -MF"dummy.d" 2>&1 \ // RUN: | FileCheck -check-prefixes=CHK-FPGA-DEP-FILES3,CHK-FPGA-DEP-FILES3-LIN %s -// RUN: %clang_cl -### --target=x86_64-pc-windows-msvc -fsycl -fintelfpga %t-1.cpp -c -Fodummy.obj 2>&1 \ +// RUN: %clang_cl -### --target=x86_64-pc-windows-msvc -fsycl -fno-sycl-default-triple -fintelfpga %t-1.cpp -c -Fodummy.obj 2>&1 \ // RUN: | FileCheck -check-prefixes=CHK-FPGA-DEP-FILES3,CHK-FPGA-DEP-FILES3-WIN %s // CHK-FPGA-DEP-FILES3: clang{{.*}} "-dependency-file" "[[OUTPUT:.+\.d]]" // CHK-FPGA-DEP-FILES3-LIN: clang-offload-bundler{{.*}} "-type=o" "-targets=sycl-spir64_fpga-unknown-unknown-sycldevice,host-x86_64-unknown-linux-gnu,sycl-fpga_dep" {{.*}} "-inputs={{.*}}.bc,{{.*}}.o,[[OUTPUT]]" @@ -339,9 +339,9 @@ /// -fintelfpga dependency file use from object phases test // RUN: touch %t-1.o -// RUN: %clangxx -fsycl -fno-sycl-device-lib=all -fintelfpga -ccc-print-phases %t-1.o 2>&1 \ +// RUN: %clangxx -fsycl -fno-sycl-default-triple -fno-sycl-device-lib=all -fintelfpga -ccc-print-phases %t-1.o 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-FPGA-DEP-FILES-OBJ-PHASES %s -// RUN: %clang_cl -fsycl -fno-sycl-device-lib=all -fintelfpga -ccc-print-phases %t-1.o 2>&1 \ +// RUN: %clang_cl -fsycl -fno-sycl-default-triple -fno-sycl-device-lib=all -fintelfpga -ccc-print-phases %t-1.o 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-FPGA-DEP-FILES-OBJ-PHASES %s // CHK-FPGA-DEP-FILES-OBJ-PHASES: 0: input, "{{.*}}-1.o", object, (host-sycl) // CHK-FPGA-DEP-FILES-OBJ-PHASES: 1: clang-offload-unbundler, {0}, object, (host-sycl) @@ -356,7 +356,6 @@ // CHK-FPGA-DEP-FILES-OBJ-PHASES: 10: clang-offload-wrapper, {9}, object, (device-sycl) // CHK-FPGA-DEP-FILES-OBJ-PHASES: 11: offload, "host-sycl ({{.*}})" {2}, "device-sycl (spir64_fpga-unknown-unknown-sycldevice)" {10}, image - /// -fintelfpga output report file test // RUN: mkdir -p %t_dir // RUN: %clangxx -### -fsycl -fintelfpga -Xshardware %s -o %t_dir/file.out 2>&1 \ diff --git a/clang/test/Driver/sycl-offload-with-split.c b/clang/test/Driver/sycl-offload-with-split.c index ae5c9beb8330a..54a7233235ddc 100644 --- a/clang/test/Driver/sycl-offload-with-split.c +++ b/clang/test/Driver/sycl-offload-with-split.c @@ -161,11 +161,11 @@ /// ########################################################################### /// Ahead of Time compilation for fpga, gen, cpu -// RUN: %clang -target x86_64-unknown-linux-gnu -ccc-print-phases -fsycl -fno-sycl-device-lib=all -fsycl-device-code-split -fsycl-targets=spir64_fpga-unknown-unknown-sycldevice %s 2>&1 \ +// RUN: %clang -target x86_64-unknown-linux-gnu -ccc-print-phases -fsycl -fno-sycl-default-triple -fno-sycl-device-lib=all -fsycl-device-code-split -fsycl-targets=spir64_fpga-unknown-unknown-sycldevice %s 2>&1 \ // RUN: | FileCheck %s -check-prefixes=CHK-PHASES-AOT,CHK-PHASES-FPGA -// RUN: %clang -target x86_64-unknown-linux-gnu -ccc-print-phases -fsycl -fno-sycl-device-lib=all -fsycl-device-code-split -fsycl-targets=spir64_gen-unknown-unknown-sycldevice %s 2>&1 \ +// RUN: %clang -target x86_64-unknown-linux-gnu -ccc-print-phases -fsycl -fno-sycl-default-triple -fno-sycl-device-lib=all -fsycl-device-code-split -fsycl-targets=spir64_gen-unknown-unknown-sycldevice %s 2>&1 \ // RUN: | FileCheck %s -check-prefixes=CHK-PHASES-AOT,CHK-PHASES-GEN -// RUN: %clang -target x86_64-unknown-linux-gnu -ccc-print-phases -fsycl -fno-sycl-device-lib=all -fsycl-device-code-split -fsycl-targets=spir64_x86_64-unknown-unknown-sycldevice %s 2>&1 \ +// RUN: %clang -target x86_64-unknown-linux-gnu -ccc-print-phases -fsycl -fno-sycl-default-triple -fno-sycl-device-lib=all -fsycl-device-code-split -fsycl-targets=spir64_x86_64-unknown-unknown-sycldevice %s 2>&1 \ // RUN: | FileCheck %s -check-prefixes=CHK-PHASES-AOT,CHK-PHASES-CPU // CHK-PHASES-AOT: 0: input, "[[INPUT:.+\.c]]", c++, (host-sycl) // CHK-PHASES-AOT: 1: append-footer, {0}, c++, (host-sycl) diff --git a/clang/test/Driver/sycl-offload.c b/clang/test/Driver/sycl-offload.c index 8b1819d0f1b65..cdbaa458380c7 100644 --- a/clang/test/Driver/sycl-offload.c +++ b/clang/test/Driver/sycl-offload.c @@ -626,14 +626,20 @@ // RUN: | FileCheck %s -check-prefixes=CHK-PHASES-AOT,CHK-PHASES-FPGA // RUN: %clang -target x86_64-unknown-linux-gnu -ccc-print-phases -fsycl -fno-sycl-device-lib=all -fsycl-targets=spir64_fpga %s 2>&1 \ // RUN: | FileCheck %s -check-prefixes=CHK-PHASES-AOT,CHK-PHASES-FPGA +// RUN: %clang -target x86_64-unknown-linux-gnu -ccc-print-phases -fsycl -fno-sycl-device-lib=all -fsycl-targets=spir64_fpga,spir64 %s 2>&1 \ +// RUN: | FileCheck %s -check-prefixes=CHK-PHASES-AOT,CHK-PHASES-FPGA // RUN: %clang -target x86_64-unknown-linux-gnu -ccc-print-phases -fsycl -fno-sycl-device-lib=all -fsycl-targets=spir64_gen-unknown-unknown-sycldevice %s 2>&1 \ // RUN: | FileCheck %s -check-prefixes=CHK-PHASES-AOT,CHK-PHASES-GEN // RUN: %clang -target x86_64-unknown-linux-gnu -ccc-print-phases -fsycl -fno-sycl-device-lib=all -fsycl-targets=spir64_gen %s 2>&1 \ // RUN: | FileCheck %s -check-prefixes=CHK-PHASES-AOT,CHK-PHASES-GEN +// RUN: %clang -target x86_64-unknown-linux-gnu -ccc-print-phases -fsycl -fno-sycl-device-lib=all -fsycl-targets=spir64_gen,spir64 %s 2>&1 \ +// RUN: | FileCheck %s -check-prefixes=CHK-PHASES-AOT,CHK-PHASES-GEN // RUN: %clang -target x86_64-unknown-linux-gnu -ccc-print-phases -fsycl -fno-sycl-device-lib=all -fsycl-targets=spir64_x86_64-unknown-unknown-sycldevice %s 2>&1 \ // RUN: | FileCheck %s -check-prefixes=CHK-PHASES-AOT,CHK-PHASES-CPU // RUN: %clang -target x86_64-unknown-linux-gnu -ccc-print-phases -fsycl -fno-sycl-device-lib=all -fsycl-targets=spir64_x86_64 %s 2>&1 \ // RUN: | FileCheck %s -check-prefixes=CHK-PHASES-AOT,CHK-PHASES-CPU +// RUN: %clang -target x86_64-unknown-linux-gnu -ccc-print-phases -fsycl -fno-sycl-device-lib=all -fsycl-targets=spir64_x86_64,spir64 %s 2>&1 \ +// RUN: | FileCheck %s -check-prefixes=CHK-PHASES-AOT,CHK-PHASES-CPU // CHK-PHASES-AOT: 0: input, "[[INPUT:.+\.c]]", c++, (host-sycl) // CHK-PHASES-AOT: 1: append-footer, {0}, c++, (host-sycl) // CHK-PHASES-AOT: 2: preprocessor, {1}, c++-cpp-output, (host-sycl) @@ -647,18 +653,27 @@ // CHK-PHASES-AOT: 8: backend, {7}, assembler, (host-sycl) // CHK-PHASES-AOT: 9: assembler, {8}, object, (host-sycl) // CHK-PHASES-AOT: 10: linker, {9}, image, (host-sycl) -// CHK-PHASES-AOT: 11: linker, {5}, ir, (device-sycl) -// CHK-PHASES-AOT: 12: sycl-post-link, {11}, tempfiletable, (device-sycl) -// CHK-PHASES-AOT: 13: file-table-tform, {12}, tempfilelist, (device-sycl) -// CHK-PHASES-AOT: 14: llvm-spirv, {13}, tempfilelist, (device-sycl) -// CHK-PHASES-FPGA: 15: backend-compiler, {14}, fpga_aocx, (device-sycl) -// CHK-PHASES-GEN: 15: backend-compiler, {14}, image, (device-sycl) -// CHK-PHASES-CPU: 15: backend-compiler, {14}, image, (device-sycl) -// CHK-PHASES-AOT: 16: file-table-tform, {12, 15}, tempfiletable, (device-sycl) -// CHK-PHASES-AOT: 17: clang-offload-wrapper, {16}, object, (device-sycl) -// CHK-PHASES-FPGA: 18: offload, "host-sycl (x86_64-unknown-linux-gnu)" {10}, "device-sycl (spir64_fpga-unknown-unknown-sycldevice)" {17}, image -// CHK-PHASES-GEN: 18: offload, "host-sycl (x86_64-unknown-linux-gnu)" {10}, "device-sycl (spir64_gen-unknown-unknown-sycldevice)" {17}, image -// CHK-PHASES-CPU: 18: offload, "host-sycl (x86_64-unknown-linux-gnu)" {10}, "device-sycl (spir64_x86_64-unknown-unknown-sycldevice)" {17}, image +// CHK-PHASES-AOT: 11: input, "[[INPUT]]", c++, (device-sycl) +// CHK-PHASES-AOT: 12: preprocessor, {11}, c++-cpp-output, (device-sycl) +// CHK-PHASES-AOT: 13: compiler, {12}, ir, (device-sycl) +// CHK-PHASES-AOT: 14: linker, {13}, ir, (device-sycl) +// CHK-PHASES-AOT: 15: sycl-post-link, {14}, tempfiletable, (device-sycl) +// CHK-PHASES-AOT: 16: file-table-tform, {15}, tempfilelist, (device-sycl) +// CHK-PHASES-AOT: 17: llvm-spirv, {16}, tempfilelist, (device-sycl) +// CHK-PHASES-FPGA: 18: backend-compiler, {17}, fpga_aocx, (device-sycl) +// CHK-PHASES-GEN: 18: backend-compiler, {17}, image, (device-sycl) +// CHK-PHASES-CPU: 18: backend-compiler, {17}, image, (device-sycl) +// CHK-PHASES-AOT: 19: file-table-tform, {15, 18}, tempfiletable, (device-sycl) +// CHK-PHASES-AOT: 20: clang-offload-wrapper, {19}, object, (device-sycl) +// CHK-PHASES-AOT: 21: linker, {5}, ir, (device-sycl) +// CHK-PHASES-AOT: 22: sycl-post-link, {21}, tempfiletable, (device-sycl) +// CHK-PHASES-AOT: 23: file-table-tform, {22}, tempfilelist, (device-sycl) +// CHK-PHASES-AOT: 24: llvm-spirv, {23}, tempfilelist, (device-sycl) +// CHK-PHASES-AOT: 25: file-table-tform, {22, 24}, tempfiletable, (device-sycl) +// CHK-PHASES-AOT: 26: clang-offload-wrapper, {25}, object, (device-sycl) +// CHK-PHASES-FPGA: 27: offload, "host-sycl (x86_64-unknown-linux-gnu)" {10}, "device-sycl (spir64_fpga-unknown-unknown-sycldevice)" {20}, "device-sycl (spir64-unknown-unknown-sycldevice)" {26}, image +// CHK-PHASES-GEN: 27: offload, "host-sycl (x86_64-unknown-linux-gnu)" {10}, "device-sycl (spir64_gen-unknown-unknown-sycldevice)" {20}, "device-sycl (spir64-unknown-unknown-sycldevice)" {26}, image +// CHK-PHASES-CPU: 27: offload, "host-sycl (x86_64-unknown-linux-gnu)" {10}, "device-sycl (spir64_x86_64-unknown-unknown-sycldevice)" {20}, "device-sycl (spir64-unknown-unknown-sycldevice)" {26}, image /// ########################################################################### @@ -739,7 +754,7 @@ // RUN: %clang -### -target x86_64-unknown-linux-gnu -fsycl -fintelfpga -Xs "-DFOO1 -DFOO2" -Xshardware %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-TOOLS-FPGA-OPTS %s // CHK-TOOLS-FPGA-OPTS: aoc{{.*}} "-o" {{.*}} "-DFOO1" "-DFOO2" -// CHK-TOOLS-FPGA-OPTS-NOT: clang-offload-wrapper{{.*}} "-compile-opts={{.*}} +// CHK-TOOLS-FPGA-OPTS-NOT: clang-offload-wrapper{{.*}} "-compile-opts={{.*-DFOO1.*}}" // RUN: %clang -### -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=spir64_gen-unknown-unknown-sycldevice -Xsycl-target-backend "-DFOO1 -DFOO2" %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-TOOLS-GEN-OPTS %s