diff --git a/llvm/lib/SYCLLowerIR/LowerESIMD.cpp b/llvm/lib/SYCLLowerIR/LowerESIMD.cpp
index 38cec50ac814e..b6f7b5c0e941d 100644
--- a/llvm/lib/SYCLLowerIR/LowerESIMD.cpp
+++ b/llvm/lib/SYCLLowerIR/LowerESIMD.cpp
@@ -1180,7 +1180,7 @@ void SYCLLowerESIMDLegacyPass::collectGenXVolatileType(Module &M) {
     if (!PTy)
       continue;
     auto GTy = dyn_cast<StructType>(PTy->getPointerElementType());
-    if (!GTy || !GTy->getName().endswith("cl::sycl::intel::gpu::simd"))
+    if (!GTy || !GTy->getName().endswith("cl::sycl::INTEL::gpu::simd"))
       continue;
     assert(GTy->getNumContainedTypes() == 1);
     auto VTy = GTy->getContainedType(0);
@@ -1238,7 +1238,7 @@ PreservedAnalyses SYCLLowerESIMDPass::run(Function &F,
 
     // process ESIMD builtins that go through special handling instead of
     // the translation procedure
-    if (Name.startswith("N2cl4sycl5intel3gpu8slm_init")) {
+    if (Name.startswith("N2cl4sycl5INTEL3gpu8slm_init")) {
       // tag the kernel with meta-data SLMSize, and remove this builtin
       translateSLMInit(*CI);
       ESIMDToErases.push_back(CI);
diff --git a/llvm/test/SYCLLowerIR/esimd_global.ll b/llvm/test/SYCLLowerIR/esimd_global.ll
index ab86858fe4da7..c6a30cfb055be 100644
--- a/llvm/test/SYCLLowerIR/esimd_global.ll
+++ b/llvm/test/SYCLLowerIR/esimd_global.ll
@@ -6,18 +6,18 @@
 target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64"
 target triple = "spir64-unknown-unknown-sycldevice"
 
-%"class._ZTSN2cl4sycl5intel3gpu4simdIiLi16EEE.cl::sycl::intel::gpu::simd" = type { <16 x i32> }
+%"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd" = type { <16 x i32> }
 
 $"_ZTSZZ4mainENK3$_0clERN2cl4sycl7handlerEE4Test" = comdat any
 
 ; CHECK: [[NEWGLOBAL:[@a-zA-Z0-9_]*]] = dso_local global <16 x i32> zeroinitializer, align 64 #0
-@0 = dso_local global %"class._ZTSN2cl4sycl5intel3gpu4simdIiLi16EEE.cl::sycl::intel::gpu::simd" zeroinitializer, align 64 #0
+@0 = dso_local global %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd" zeroinitializer, align 64 #0
 
 ; Function Attrs: norecurse
 define weak_odr dso_local spir_kernel void @"_ZTSZZ4mainENK3$_0clERN2cl4sycl7handlerEE4Test"(i32 addrspace(1)* %_arg_) local_unnamed_addr #1 comdat !kernel_arg_addr_space !8 !kernel_arg_access_qual !9 !kernel_arg_type !10 !kernel_arg_base_type !10 !kernel_arg_type_qual !11 !sycl_explicit_simd !12 !intel_reqd_sub_group_size !8 {
 entry:
-  %vc.i = alloca %"class._ZTSN2cl4sycl5intel3gpu4simdIiLi16EEE.cl::sycl::intel::gpu::simd", align 64
-  %agg.tmp.i = alloca %"class._ZTSN2cl4sycl5intel3gpu4simdIiLi16EEE.cl::sycl::intel::gpu::simd", align 64
+  %vc.i = alloca %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd", align 64
+  %agg.tmp.i = alloca %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd", align 64
   %call.esimd.i.i.i.i.i = call <3 x i32> @llvm.genx.local.id.v3i32() #5
   %local_id.y.i.i.i.i.i = extractelement <3 x i32> %call.esimd.i.i.i.i.i, i32 1
   %local_id.y.cast.ty.i.i.i.i.i = zext i32 %local_id.y.i.i.i.i.i to i64
@@ -36,15 +36,15 @@ entry:
   %group.id.x.cast.ty.i.i.i.i.i = zext i32 %group.id.x.i.i.i.i.i to i64
   %mul.i4.i.i.i.i = mul nuw i64 %group.id.x.cast.ty.i.i.i.i.i, %wgsize.x.cast.ty.i.i.i.i.i
   %add.i5.i.i.i.i = add i64 %mul.i4.i.i.i.i, %local_id.x.cast.ty.i.i.i.i.i
-  %0 = bitcast %"class._ZTSN2cl4sycl5intel3gpu4simdIiLi16EEE.cl::sycl::intel::gpu::simd"* %agg.tmp.i to i8*
+  %0 = bitcast %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd"* %agg.tmp.i to i8*
   call void @llvm.lifetime.start.p0i8(i64 64, i8* nonnull %0)
-  %1 = bitcast %"class._ZTSN2cl4sycl5intel3gpu4simdIiLi16EEE.cl::sycl::intel::gpu::simd"* %vc.i to i8*
+  %1 = bitcast %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd"* %vc.i to i8*
   call void @llvm.lifetime.start.p0i8(i64 64, i8* nonnull %1) #5
   %conv.i = trunc i64 %add.i5.i.i.i.i to i32
-  %2 = addrspacecast %"class._ZTSN2cl4sycl5intel3gpu4simdIiLi16EEE.cl::sycl::intel::gpu::simd"* %vc.i to %"class._ZTSN2cl4sycl5intel3gpu4simdIiLi16EEE.cl::sycl::intel::gpu::simd" addrspace(4)*
+  %2 = addrspacecast %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd"* %vc.i to %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd" addrspace(4)*
   %splat.splatinsert.i.i = insertelement <16 x i32> undef, i32 %conv.i, i32 0
   %splat.splat.i.i = shufflevector <16 x i32> %splat.splatinsert.i.i, <16 x i32> undef, <16 x i32> zeroinitializer
-  %M_data.i13.i = getelementptr inbounds %"class._ZTSN2cl4sycl5intel3gpu4simdIiLi16EEE.cl::sycl::intel::gpu::simd", %"class._ZTSN2cl4sycl5intel3gpu4simdIiLi16EEE.cl::sycl::intel::gpu::simd" addrspace(4)* %2, i64 0, i32 0
+  %M_data.i13.i = getelementptr inbounds %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd", %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd" addrspace(4)* %2, i64 0, i32 0
   store <16 x i32> %splat.splat.i.i, <16 x i32> addrspace(4)* %M_data.i13.i, align 64, !tbaa !13
   %conv3.i = trunc i64 %add.i.i.i.i.i to i32
   %splat.splatinsert.i20.i = insertelement <8 x i32> undef, i32 %conv3.i, i32 0
@@ -56,17 +56,17 @@ entry:
   %..i = select i1 %cmp.i, i64 %add.i5.i.i.i.i, i64 %add.i.i.i.i.i
   %conv9.i = trunc i64 %..i to i32
 ; CHECK: store <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, <16 x i32> addrspace(4)* addrspacecast (<16 x i32>* getelementptr inbounds ({{.+}}, {{.+}}* bitcast (<16 x i32>* [[NEWGLOBAL]] to {{.+}}*), i64 0, i32 0) to <16 x i32> addrspace(4)*), align 64, !tbaa.struct !16
-  store <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, <16 x i32> addrspace(4)* addrspacecast (<16 x i32>* getelementptr inbounds (%"class._ZTSN2cl4sycl5intel3gpu4simdIiLi16EEE.cl::sycl::intel::gpu::simd", %"class._ZTSN2cl4sycl5intel3gpu4simdIiLi16EEE.cl::sycl::intel::gpu::simd"* @0, i64 0, i32 0) to <16 x i32> addrspace(4)*), align 64, !tbaa.struct !16
+  store <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, <16 x i32> addrspace(4)* addrspacecast (<16 x i32>* getelementptr inbounds (%"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd", %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd"* @0, i64 0, i32 0) to <16 x i32> addrspace(4)*), align 64, !tbaa.struct !16
   %mul.i = shl nsw i32 %conv9.i, 4
   %idx.ext.i = sext i32 %mul.i to i64
   %add.ptr.i16 = getelementptr inbounds i32, i32 addrspace(1)* %_arg_, i64 %idx.ext.i
   %add.ptr.i = addrspacecast i32 addrspace(1)* %add.ptr.i16 to i32 addrspace(4)*
-  %3 = addrspacecast %"class._ZTSN2cl4sycl5intel3gpu4simdIiLi16EEE.cl::sycl::intel::gpu::simd"* %agg.tmp.i to %"class._ZTSN2cl4sycl5intel3gpu4simdIiLi16EEE.cl::sycl::intel::gpu::simd" addrspace(4)*
+  %3 = addrspacecast %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd"* %agg.tmp.i to %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd" addrspace(4)*
   %call.esimd.i.i.i = call <16 x i32> @llvm.genx.vload.v16i32.p4v16i32(<16 x i32> addrspace(4)* %M_data.i13.i) #5
-  %M_data.i2.i.i = getelementptr inbounds %"class._ZTSN2cl4sycl5intel3gpu4simdIiLi16EEE.cl::sycl::intel::gpu::simd", %"class._ZTSN2cl4sycl5intel3gpu4simdIiLi16EEE.cl::sycl::intel::gpu::simd" addrspace(4)* %3, i64 0, i32 0
+  %M_data.i2.i.i = getelementptr inbounds %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd", %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd" addrspace(4)* %3, i64 0, i32 0
   call void @llvm.genx.vstore.v16i32.p4v16i32(<16 x i32> %call.esimd.i.i.i, <16 x i32> addrspace(4)* %M_data.i2.i.i) #5
-  call spir_func void @_Z3fooPiN2cl4sycl5intel3gpu4simdIiLi16EEE(i32 addrspace(4)* %add.ptr.i, %"class._ZTSN2cl4sycl5intel3gpu4simdIiLi16EEE.cl::sycl::intel::gpu::simd"* nonnull %agg.tmp.i) #5
-  store <16 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>, <16 x i32> addrspace(4)* addrspacecast (<16 x i32>* getelementptr inbounds (%"class._ZTSN2cl4sycl5intel3gpu4simdIiLi16EEE.cl::sycl::intel::gpu::simd", %"class._ZTSN2cl4sycl5intel3gpu4simdIiLi16EEE.cl::sycl::intel::gpu::simd"* @0, i64 0, i32 0) to <16 x i32> addrspace(4)*), align 64, !tbaa.struct !16
+  call spir_func void @_Z3fooPiN2cl4sycl5INTEL3gpu4simdIiLi16EEE(i32 addrspace(4)* %add.ptr.i, %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd"* nonnull %agg.tmp.i) #5
+  store <16 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>, <16 x i32> addrspace(4)* addrspacecast (<16 x i32>* getelementptr inbounds (%"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd", %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd"* @0, i64 0, i32 0) to <16 x i32> addrspace(4)*), align 64, !tbaa.struct !16
   call void @llvm.lifetime.end.p0i8(i64 64, i8* nonnull %1) #5
   call void @llvm.lifetime.end.p0i8(i64 64, i8* nonnull %0)
   ret void
@@ -79,17 +79,17 @@ declare void @llvm.lifetime.start.p0i8(i64 immarg %0, i8* nocapture %1) #2
 declare void @llvm.lifetime.end.p0i8(i64 immarg %0, i8* nocapture %1) #2
 
 ; Function Attrs: noinline norecurse nounwind
-define dso_local spir_func void @_Z3fooPiN2cl4sycl5intel3gpu4simdIiLi16EEE(i32 addrspace(4)* %C, %"class._ZTSN2cl4sycl5intel3gpu4simdIiLi16EEE.cl::sycl::intel::gpu::simd"* %v) local_unnamed_addr #3 !sycl_explicit_simd !12 {
+define dso_local spir_func void @_Z3fooPiN2cl4sycl5INTEL3gpu4simdIiLi16EEE(i32 addrspace(4)* %C, %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd"* %v) local_unnamed_addr #3 !sycl_explicit_simd !12 {
 entry:
-  %agg.tmp = alloca %"class._ZTSN2cl4sycl5intel3gpu4simdIiLi16EEE.cl::sycl::intel::gpu::simd", align 64
-  %0 = addrspacecast %"class._ZTSN2cl4sycl5intel3gpu4simdIiLi16EEE.cl::sycl::intel::gpu::simd"* %v to %"class._ZTSN2cl4sycl5intel3gpu4simdIiLi16EEE.cl::sycl::intel::gpu::simd" addrspace(4)*
-  %1 = addrspacecast %"class._ZTSN2cl4sycl5intel3gpu4simdIiLi16EEE.cl::sycl::intel::gpu::simd"* %agg.tmp to %"class._ZTSN2cl4sycl5intel3gpu4simdIiLi16EEE.cl::sycl::intel::gpu::simd" addrspace(4)*
-  %M_data.i.i = getelementptr inbounds %"class._ZTSN2cl4sycl5intel3gpu4simdIiLi16EEE.cl::sycl::intel::gpu::simd", %"class._ZTSN2cl4sycl5intel3gpu4simdIiLi16EEE.cl::sycl::intel::gpu::simd" addrspace(4)* %0, i64 0, i32 0
+  %agg.tmp = alloca %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd", align 64
+  %0 = addrspacecast %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd"* %v to %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd" addrspace(4)*
+  %1 = addrspacecast %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd"* %agg.tmp to %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd" addrspace(4)*
+  %M_data.i.i = getelementptr inbounds %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd", %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd" addrspace(4)* %0, i64 0, i32 0
   %call.esimd.i.i = call <16 x i32> @llvm.genx.vload.v16i32.p4v16i32(<16 x i32> addrspace(4)* %M_data.i.i), !noalias !17
 ; CHECK: {{.+}} = call <16 x i32> @llvm.genx.vload.v16i32.p4v16i32(<16 x i32> addrspace(4)* getelementptr ({{.+}}, {{.+}} addrspace(4)* addrspacecast ({{.+}}* bitcast (<16 x i32>* [[NEWGLOBAL]] to {{.+}}*) to {{.+}} addrspace(4)*), i64 0, i32 0)), !noalias !17
-  %call.esimd.i8.i = call <16 x i32> @llvm.genx.vload.v16i32.p4v16i32(<16 x i32> addrspace(4)* getelementptr (%"class._ZTSN2cl4sycl5intel3gpu4simdIiLi16EEE.cl::sycl::intel::gpu::simd", %"class._ZTSN2cl4sycl5intel3gpu4simdIiLi16EEE.cl::sycl::intel::gpu::simd" addrspace(4)* addrspacecast (%"class._ZTSN2cl4sycl5intel3gpu4simdIiLi16EEE.cl::sycl::intel::gpu::simd"* @0 to %"class._ZTSN2cl4sycl5intel3gpu4simdIiLi16EEE.cl::sycl::intel::gpu::simd" addrspace(4)*), i64 0, i32 0)), !noalias !17
+  %call.esimd.i8.i = call <16 x i32> @llvm.genx.vload.v16i32.p4v16i32(<16 x i32> addrspace(4)* getelementptr (%"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd", %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd" addrspace(4)* addrspacecast (%"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd"* @0 to %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd" addrspace(4)*), i64 0, i32 0)), !noalias !17
   %add.i = add <16 x i32> %call.esimd.i8.i, %call.esimd.i.i
-  %M_data.i.i.i = getelementptr inbounds %"class._ZTSN2cl4sycl5intel3gpu4simdIiLi16EEE.cl::sycl::intel::gpu::simd", %"class._ZTSN2cl4sycl5intel3gpu4simdIiLi16EEE.cl::sycl::intel::gpu::simd" addrspace(4)* %1, i64 0, i32 0
+  %M_data.i.i.i = getelementptr inbounds %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd", %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd" addrspace(4)* %1, i64 0, i32 0
   call void @llvm.genx.vstore.v16i32.p4v16i32(<16 x i32> %add.i, <16 x i32> addrspace(4)* %M_data.i.i.i)
   %2 = ptrtoint i32 addrspace(4)* %C to i64
   %call.esimd.i.i2 = call <16 x i32> @llvm.genx.vload.v16i32.p4v16i32(<16 x i32> addrspace(4)* %M_data.i.i.i)
@@ -153,8 +153,8 @@ attributes #5 = { nounwind }
 !15 = !{!"Simple C++ TBAA"}
 !16 = !{i64 0, i64 64, !13}
 !17 = !{!18}
-!18 = distinct !{!18, !19, !"_ZNK2cl4sycl5intel3gpu4simdIiLi16EEplERKS4_: %agg.result"}
-!19 = distinct !{!19, !"_ZNK2cl4sycl5intel3gpu4simdIiLi16EEplERKS4_"}
+!18 = distinct !{!18, !19, !"_ZNK2cl4sycl5INTEL3gpu4simdIiLi16EEplERKS4_: %agg.result"}
+!19 = distinct !{!19, !"_ZNK2cl4sycl5INTEL3gpu4simdIiLi16EEplERKS4_"}
 !20 = !{i32 8275}
 !21 = !{i32 8268}
 !22 = !{i32 8269}
diff --git a/llvm/test/SYCLLowerIR/esimd_lower_intrins.ll b/llvm/test/SYCLLowerIR/esimd_lower_intrins.ll
index 5ed90614a675b..1e5e5754c8976 100644
--- a/llvm/test/SYCLLowerIR/esimd_lower_intrins.ll
+++ b/llvm/test/SYCLLowerIR/esimd_lower_intrins.ll
@@ -165,7 +165,7 @@ define dso_local spir_func void  @FUNC_29() !sycl_explicit_simd !1 {
 
 define dso_local spir_kernel void  @FUNC_30() !sycl_explicit_simd !1 {
 ; CHECK: define dso_local spir_kernel void  @FUNC_30() !sycl_explicit_simd !1
-  call spir_func void @_ZN2cl4sycl5intel3gpu8slm_initEj(i32 1023)
+  call spir_func void @_ZN2cl4sycl5INTEL3gpu8slm_initEj(i32 1023)
   ret void
 ; CHECK-NEXT: ret void
 }
@@ -210,7 +210,7 @@ declare dso_local spir_func <32 x i32> @_Z24__esimd_media_block_loadIiLi4ELi8E14
 declare dso_local spir_func void @_Z25__esimd_media_block_storeIiLi4ELi8E14ocl_image2d_woEvjT2_jjjjN2cm3gen13__vector_typeIT_XmlT0_T1_EE4typeE(i32 %0, %opencl.image2d_wo_t addrspace(1)* %1, i32 %2, i32 %3, i32 %4, i32 %5, <32 x i32> %6)
 declare dso_local spir_func <32 x i32> @_Z13__esimd_vloadIiLi32EEN2cm3gen13__vector_typeIT_XT0_EE4typeEPKS5_(<32 x i32> addrspace(4)* %0)
 declare dso_local spir_func void @_Z14__esimd_vstoreIfLi16EEvPN2cm3gen13__vector_typeIT_XT0_EE4typeES5_(<16 x float> addrspace(4)* %0, <16 x float> %1)
-declare dso_local spir_func void @_ZN2cl4sycl5intel3gpu8slm_initEj(i32)
+declare dso_local spir_func void @_ZN2cl4sycl5INTEL3gpu8slm_initEj(i32)
 
 attributes #0 = { "genx_byte_offset"="192" "genx_volatile" }
 
diff --git a/sycl/include/CL/sycl/intel/esimd.hpp b/sycl/include/CL/sycl/INTEL/esimd.hpp
similarity index 80%
rename from sycl/include/CL/sycl/intel/esimd.hpp
rename to sycl/include/CL/sycl/INTEL/esimd.hpp
index 7f4b7886d2d2c..5bef244eabd48 100644
--- a/sycl/include/CL/sycl/intel/esimd.hpp
+++ b/sycl/include/CL/sycl/INTEL/esimd.hpp
@@ -10,10 +10,10 @@
 
 #pragma once
 
-#include <CL/sycl/intel/esimd/esimd.hpp>
-#include <CL/sycl/intel/esimd/esimd_math.hpp>
-#include <CL/sycl/intel/esimd/esimd_memory.hpp>
-#include <CL/sycl/intel/esimd/esimd_view.hpp>
+#include <CL/sycl/INTEL/esimd/esimd.hpp>
+#include <CL/sycl/INTEL/esimd/esimd_math.hpp>
+#include <CL/sycl/INTEL/esimd/esimd_memory.hpp>
+#include <CL/sycl/INTEL/esimd/esimd_view.hpp>
 
 #ifdef __SYCL_DEVICE_ONLY__
 #define SYCL_ESIMD_KERNEL __attribute__((sycl_explicit_simd))
diff --git a/sycl/include/CL/sycl/intel/esimd/detail/esimd_host_util.hpp b/sycl/include/CL/sycl/INTEL/esimd/detail/esimd_host_util.hpp
similarity index 100%
rename from sycl/include/CL/sycl/intel/esimd/detail/esimd_host_util.hpp
rename to sycl/include/CL/sycl/INTEL/esimd/detail/esimd_host_util.hpp
diff --git a/sycl/include/CL/sycl/intel/esimd/detail/esimd_intrin.hpp b/sycl/include/CL/sycl/INTEL/esimd/detail/esimd_intrin.hpp
similarity index 85%
rename from sycl/include/CL/sycl/intel/esimd/detail/esimd_intrin.hpp
rename to sycl/include/CL/sycl/INTEL/esimd/detail/esimd_intrin.hpp
index 23674ac3d3e91..34bbc905ceb44 100644
--- a/sycl/include/CL/sycl/intel/esimd/detail/esimd_intrin.hpp
+++ b/sycl/include/CL/sycl/INTEL/esimd/detail/esimd_intrin.hpp
@@ -11,9 +11,9 @@
 
 #pragma once
 
-#include <CL/sycl/intel/esimd/detail/esimd_types.hpp>
-#include <CL/sycl/intel/esimd/detail/esimd_util.hpp>
-#include <CL/sycl/intel/esimd/esimd_enum.hpp>
+#include <CL/sycl/INTEL/esimd/detail/esimd_types.hpp>
+#include <CL/sycl/INTEL/esimd/detail/esimd_util.hpp>
+#include <CL/sycl/INTEL/esimd/esimd_enum.hpp>
 #include <cstdint>
 
 // \brief __esimd_rdregion: region access intrinsic.
@@ -60,8 +60,8 @@
 //
 template <typename T, int N, int M, int VStride, int Width, int Stride,
           int ParentWidth = 0>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<T, M>
-__esimd_rdregion(sycl::intel::gpu::vector_type_t<T, N> Input, uint16_t Offset);
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<T, M>
+__esimd_rdregion(sycl::INTEL::gpu::vector_type_t<T, N> Input, uint16_t Offset);
 
 // __esimd_wrregion returns the updated vector with the region updated.
 //
@@ -112,14 +112,14 @@ __esimd_rdregion(sycl::intel::gpu::vector_type_t<T, N> Input, uint16_t Offset);
 //
 template <typename T, int N, int M, int VStride, int Width, int Stride,
           int ParentWidth = 0>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<T, N>
-__esimd_wrregion(sycl::intel::gpu::vector_type_t<T, N> OldVal,
-                 sycl::intel::gpu::vector_type_t<T, M> NewVal, uint16_t Offset,
-                 sycl::intel::gpu::mask_type_t<M> Mask = 1);
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<T, N>
+__esimd_wrregion(sycl::INTEL::gpu::vector_type_t<T, N> OldVal,
+                 sycl::INTEL::gpu::vector_type_t<T, M> NewVal, uint16_t Offset,
+                 sycl::INTEL::gpu::mask_type_t<M> Mask = 1);
 
 __SYCL_INLINE_NAMESPACE(cl) {
 namespace sycl {
-namespace intel {
+namespace INTEL {
 namespace gpu {
 // TODO dependencies on the std SYCL concepts like images
 // should be refactored in a separate header
@@ -208,7 +208,7 @@ readRegion(const vector_type_t<BT, BN> &Base, std::pair<T, U> Region) {
 }
 
 } // namespace gpu
-} // namespace intel
+} // namespace INTEL
 } // namespace sycl
 } // __SYCL_INLINE_NAMESPACE(cl)
 
@@ -218,37 +218,37 @@ readRegion(const vector_type_t<BT, BN> &Base, std::pair<T, U> Region) {
 // optimization on simd object
 //
 template <typename T, int N>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<T, N>
-__esimd_vload(const sycl::intel::gpu::vector_type_t<T, N> *ptr);
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<T, N>
+__esimd_vload(const sycl::INTEL::gpu::vector_type_t<T, N> *ptr);
 
 // vstore
 //
 // map to the backend vstore intrinsic, used by compiler to control
 // optimization on simd object
 template <typename T, int N>
-SYCL_EXTERNAL void __esimd_vstore(sycl::intel::gpu::vector_type_t<T, N> *ptr,
-                                  sycl::intel::gpu::vector_type_t<T, N> vals);
+SYCL_EXTERNAL void __esimd_vstore(sycl::INTEL::gpu::vector_type_t<T, N> *ptr,
+                                  sycl::INTEL::gpu::vector_type_t<T, N> vals);
 
 template <typename T, int N>
-SYCL_EXTERNAL uint16_t __esimd_any(sycl::intel::gpu::vector_type_t<T, N> src);
+SYCL_EXTERNAL uint16_t __esimd_any(sycl::INTEL::gpu::vector_type_t<T, N> src);
 
 template <typename T, int N>
-SYCL_EXTERNAL uint16_t __esimd_all(sycl::intel::gpu::vector_type_t<T, N> src);
+SYCL_EXTERNAL uint16_t __esimd_all(sycl::INTEL::gpu::vector_type_t<T, N> src);
 
 #ifndef __SYCL_DEVICE_ONLY__
 
 // Implementations of ESIMD intrinsics for the SYCL host device
 template <typename T, int N, int M, int VStride, int Width, int Stride,
           int ParentWidth>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<T, M>
-__esimd_rdregion(sycl::intel::gpu::vector_type_t<T, N> Input, uint16_t Offset) {
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<T, M>
+__esimd_rdregion(sycl::INTEL::gpu::vector_type_t<T, N> Input, uint16_t Offset) {
   uint16_t EltOffset = Offset / sizeof(T);
   assert(Offset % sizeof(T) == 0);
 
   int NumRows = M / Width;
   assert(M % Width == 0);
 
-  sycl::intel::gpu::vector_type_t<T, M> Result;
+  sycl::INTEL::gpu::vector_type_t<T, M> Result;
   int Index = 0;
   for (int i = 0; i < NumRows; ++i) {
     for (int j = 0; j < Width; ++j) {
@@ -260,17 +260,17 @@ __esimd_rdregion(sycl::intel::gpu::vector_type_t<T, N> Input, uint16_t Offset) {
 
 template <typename T, int N, int M, int VStride, int Width, int Stride,
           int ParentWidth>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<T, N>
-__esimd_wrregion(sycl::intel::gpu::vector_type_t<T, N> OldVal,
-                 sycl::intel::gpu::vector_type_t<T, M> NewVal, uint16_t Offset,
-                 sycl::intel::gpu::mask_type_t<M> Mask) {
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<T, N>
+__esimd_wrregion(sycl::INTEL::gpu::vector_type_t<T, N> OldVal,
+                 sycl::INTEL::gpu::vector_type_t<T, M> NewVal, uint16_t Offset,
+                 sycl::INTEL::gpu::mask_type_t<M> Mask) {
   uint16_t EltOffset = Offset / sizeof(T);
   assert(Offset % sizeof(T) == 0);
 
   int NumRows = M / Width;
   assert(M % Width == 0);
 
-  sycl::intel::gpu::vector_type_t<T, N> Result = OldVal;
+  sycl::INTEL::gpu::vector_type_t<T, N> Result = OldVal;
   int Index = 0;
   for (int i = 0; i < NumRows; ++i) {
     for (int j = 0; j < Width; ++j) {
diff --git a/sycl/include/CL/sycl/intel/esimd/detail/esimd_math_intrin.hpp b/sycl/include/CL/sycl/INTEL/esimd/detail/esimd_math_intrin.hpp
similarity index 91%
rename from sycl/include/CL/sycl/intel/esimd/detail/esimd_math_intrin.hpp
rename to sycl/include/CL/sycl/INTEL/esimd/detail/esimd_math_intrin.hpp
index c3f5a9d141305..dbe6f457b8c09 100644
--- a/sycl/include/CL/sycl/intel/esimd/detail/esimd_math_intrin.hpp
+++ b/sycl/include/CL/sycl/INTEL/esimd/detail/esimd_math_intrin.hpp
@@ -11,12 +11,12 @@
 
 #pragma once
 
-#include <CL/sycl/intel/esimd/detail/esimd_host_util.hpp>
-#include <CL/sycl/intel/esimd/detail/esimd_types.hpp>
-#include <CL/sycl/intel/esimd/esimd_enum.hpp>
+#include <CL/sycl/INTEL/esimd/detail/esimd_host_util.hpp>
+#include <CL/sycl/INTEL/esimd/detail/esimd_types.hpp>
+#include <CL/sycl/INTEL/esimd/esimd_enum.hpp>
 #include <cstdint>
 
-using sycl::intel::gpu::vector_type_t;
+using sycl::INTEL::gpu::vector_type_t;
 
 // saturation intrinsics
 template <typename T0, typename T1, int SZ>
@@ -210,39 +210,39 @@ SYCL_EXTERNAL vector_type_t<T1, N> __esimd_dp4a(vector_type_t<T2, N> src0,
 
 // Reduction functions
 template <typename Ty, int N>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N>
-__esimd_reduced_fmax(sycl::intel::gpu::vector_type_t<Ty, N> src1,
-                     sycl::intel::gpu::vector_type_t<Ty, N> src2);
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N>
+__esimd_reduced_fmax(sycl::INTEL::gpu::vector_type_t<Ty, N> src1,
+                     sycl::INTEL::gpu::vector_type_t<Ty, N> src2);
 
 template <typename Ty, int N>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N>
-__esimd_reduced_umax(sycl::intel::gpu::vector_type_t<Ty, N> src1,
-                     sycl::intel::gpu::vector_type_t<Ty, N> src2);
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N>
+__esimd_reduced_umax(sycl::INTEL::gpu::vector_type_t<Ty, N> src1,
+                     sycl::INTEL::gpu::vector_type_t<Ty, N> src2);
 
 template <typename Ty, int N>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N>
-__esimd_reduced_smax(sycl::intel::gpu::vector_type_t<Ty, N> src1,
-                     sycl::intel::gpu::vector_type_t<Ty, N> src2);
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N>
+__esimd_reduced_smax(sycl::INTEL::gpu::vector_type_t<Ty, N> src1,
+                     sycl::INTEL::gpu::vector_type_t<Ty, N> src2);
 
 template <typename Ty, int N>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N>
-__esimd_reduced_fmin(sycl::intel::gpu::vector_type_t<Ty, N> src1,
-                     sycl::intel::gpu::vector_type_t<Ty, N> src2);
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N>
+__esimd_reduced_fmin(sycl::INTEL::gpu::vector_type_t<Ty, N> src1,
+                     sycl::INTEL::gpu::vector_type_t<Ty, N> src2);
 
 template <typename Ty, int N>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N>
-__esimd_reduced_umin(sycl::intel::gpu::vector_type_t<Ty, N> src1,
-                     sycl::intel::gpu::vector_type_t<Ty, N> src2);
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N>
+__esimd_reduced_umin(sycl::INTEL::gpu::vector_type_t<Ty, N> src1,
+                     sycl::INTEL::gpu::vector_type_t<Ty, N> src2);
 
 template <typename Ty, int N>
-sycl::intel::gpu::vector_type_t<Ty, N> SYCL_EXTERNAL
-__esimd_reduced_smin(sycl::intel::gpu::vector_type_t<Ty, N> src1,
-                     sycl::intel::gpu::vector_type_t<Ty, N> src2);
+sycl::INTEL::gpu::vector_type_t<Ty, N> SYCL_EXTERNAL
+__esimd_reduced_smin(sycl::INTEL::gpu::vector_type_t<Ty, N> src1,
+                     sycl::INTEL::gpu::vector_type_t<Ty, N> src2);
 
 template <typename Ty, int N>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N>
-__esimd_dp4(sycl::intel::gpu::vector_type_t<Ty, N> v1,
-            sycl::intel::gpu::vector_type_t<Ty, N> v2);
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N>
+__esimd_dp4(sycl::INTEL::gpu::vector_type_t<Ty, N> v1,
+            sycl::INTEL::gpu::vector_type_t<Ty, N> v2);
 
 #ifndef __SYCL_DEVICE_ONLY__
 
@@ -1096,10 +1096,10 @@ SYCL_EXTERNAL vector_type_t<T1, N> __esimd_dp4a(vector_type_t<T2, N> src0,
 };
 
 template <typename Ty, int N>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N>
-__esimd_reduced_max(sycl::intel::gpu::vector_type_t<Ty, N> src1,
-                    sycl::intel::gpu::vector_type_t<Ty, N> src2) {
-  sycl::intel::gpu::vector_type_t<Ty, N> retv;
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N>
+__esimd_reduced_max(sycl::INTEL::gpu::vector_type_t<Ty, N> src1,
+                    sycl::INTEL::gpu::vector_type_t<Ty, N> src2) {
+  sycl::INTEL::gpu::vector_type_t<Ty, N> retv;
   for (int I = 0; I < N; I++) {
     if (src1[I] >= src2[I]) {
       retv[I] = src1[I];
@@ -1111,31 +1111,31 @@ __esimd_reduced_max(sycl::intel::gpu::vector_type_t<Ty, N> src1,
 }
 
 template <typename Ty, int N>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N>
-__esimd_reduced_fmax(sycl::intel::gpu::vector_type_t<Ty, N> src1,
-                     sycl::intel::gpu::vector_type_t<Ty, N> src2) {
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N>
+__esimd_reduced_fmax(sycl::INTEL::gpu::vector_type_t<Ty, N> src1,
+                     sycl::INTEL::gpu::vector_type_t<Ty, N> src2) {
   return __esimd_reduced_max<Ty, N>(src1, src2);
 }
 
 template <typename Ty, int N>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N>
-__esimd_reduced_umax(sycl::intel::gpu::vector_type_t<Ty, N> src1,
-                     sycl::intel::gpu::vector_type_t<Ty, N> src2) {
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N>
+__esimd_reduced_umax(sycl::INTEL::gpu::vector_type_t<Ty, N> src1,
+                     sycl::INTEL::gpu::vector_type_t<Ty, N> src2) {
   return __esimd_reduced_max<Ty, N>(src1, src2);
 }
 
 template <typename Ty, int N>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N>
-__esimd_reduced_smax(sycl::intel::gpu::vector_type_t<Ty, N> src1,
-                     sycl::intel::gpu::vector_type_t<Ty, N> src2) {
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N>
+__esimd_reduced_smax(sycl::INTEL::gpu::vector_type_t<Ty, N> src1,
+                     sycl::INTEL::gpu::vector_type_t<Ty, N> src2) {
   return __esimd_reduced_max<Ty, N>(src1, src2);
 }
 
 template <typename Ty, int N>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N>
-__esimd_reduced_min(sycl::intel::gpu::vector_type_t<Ty, N> src1,
-                    sycl::intel::gpu::vector_type_t<Ty, N> src2) {
-  sycl::intel::gpu::vector_type_t<Ty, N> retv;
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N>
+__esimd_reduced_min(sycl::INTEL::gpu::vector_type_t<Ty, N> src1,
+                    sycl::INTEL::gpu::vector_type_t<Ty, N> src2) {
+  sycl::INTEL::gpu::vector_type_t<Ty, N> retv;
   for (int I = 0; I < N; I++) {
     if (src1[I] <= src2[I]) {
       retv[I] = src1[I];
@@ -1147,23 +1147,23 @@ __esimd_reduced_min(sycl::intel::gpu::vector_type_t<Ty, N> src1,
 }
 
 template <typename Ty, int N>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N>
-__esimd_reduced_fmin(sycl::intel::gpu::vector_type_t<Ty, N> src1,
-                     sycl::intel::gpu::vector_type_t<Ty, N> src2) {
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N>
+__esimd_reduced_fmin(sycl::INTEL::gpu::vector_type_t<Ty, N> src1,
+                     sycl::INTEL::gpu::vector_type_t<Ty, N> src2) {
   return __esimd_reduced_min<Ty, N>(src1, src2);
 }
 
 template <typename Ty, int N>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N>
-__esimd_reduced_umin(sycl::intel::gpu::vector_type_t<Ty, N> src1,
-                     sycl::intel::gpu::vector_type_t<Ty, N> src2) {
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N>
+__esimd_reduced_umin(sycl::INTEL::gpu::vector_type_t<Ty, N> src1,
+                     sycl::INTEL::gpu::vector_type_t<Ty, N> src2) {
   return __esimd_reduced_min<Ty, N>(src1, src2);
 }
 
 template <typename Ty, int N>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N>
-__esimd_reduced_smin(sycl::intel::gpu::vector_type_t<Ty, N> src1,
-                     sycl::intel::gpu::vector_type_t<Ty, N> src2) {
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N>
+__esimd_reduced_smin(sycl::INTEL::gpu::vector_type_t<Ty, N> src1,
+                     sycl::INTEL::gpu::vector_type_t<Ty, N> src2) {
   return __esimd_reduced_min<Ty, N>(src1, src2);
 }
 
diff --git a/sycl/include/CL/sycl/intel/esimd/detail/esimd_memory_intrin.hpp b/sycl/include/CL/sycl/INTEL/esimd/detail/esimd_memory_intrin.hpp
similarity index 50%
rename from sycl/include/CL/sycl/intel/esimd/detail/esimd_memory_intrin.hpp
rename to sycl/include/CL/sycl/INTEL/esimd/detail/esimd_memory_intrin.hpp
index d712fccf0d956..0c53470712ee6 100644
--- a/sycl/include/CL/sycl/intel/esimd/detail/esimd_memory_intrin.hpp
+++ b/sycl/include/CL/sycl/INTEL/esimd/detail/esimd_memory_intrin.hpp
@@ -11,100 +11,100 @@
 
 #pragma once
 
-#include <CL/sycl/intel/esimd/detail/esimd_types.hpp>
-#include <CL/sycl/intel/esimd/detail/esimd_util.hpp>
-#include <CL/sycl/intel/esimd/esimd_enum.hpp>
+#include <CL/sycl/INTEL/esimd/detail/esimd_types.hpp>
+#include <CL/sycl/INTEL/esimd/detail/esimd_util.hpp>
+#include <CL/sycl/INTEL/esimd/esimd_enum.hpp>
 #include <cstdint>
 
 // flat_read does flat-address gather
 template <typename Ty, int N, int NumBlk = 0,
-          sycl::intel::gpu::CacheHint L1H = sycl::intel::gpu::CacheHint::None,
-          sycl::intel::gpu::CacheHint L3H = sycl::intel::gpu::CacheHint::None>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<
-    Ty, N * sycl::intel::gpu::ElemsPerAddrDecoding(NumBlk)>
-__esimd_flat_read(sycl::intel::gpu::vector_type_t<uint64_t, N> addrs,
+          sycl::INTEL::gpu::CacheHint L1H = sycl::INTEL::gpu::CacheHint::None,
+          sycl::INTEL::gpu::CacheHint L3H = sycl::INTEL::gpu::CacheHint::None>
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<
+    Ty, N * sycl::INTEL::gpu::ElemsPerAddrDecoding(NumBlk)>
+__esimd_flat_read(sycl::INTEL::gpu::vector_type_t<uint64_t, N> addrs,
                   int ElemsPerAddr = NumBlk,
-                  sycl::intel::gpu::vector_type_t<uint16_t, N> pred = 1);
+                  sycl::INTEL::gpu::vector_type_t<uint16_t, N> pred = 1);
 
 // flat_write does flat-address scatter
 template <typename Ty, int N, int NumBlk = 0,
-          sycl::intel::gpu::CacheHint L1H = sycl::intel::gpu::CacheHint::None,
-          sycl::intel::gpu::CacheHint L3H = sycl::intel::gpu::CacheHint::None>
+          sycl::INTEL::gpu::CacheHint L1H = sycl::INTEL::gpu::CacheHint::None,
+          sycl::INTEL::gpu::CacheHint L3H = sycl::INTEL::gpu::CacheHint::None>
 SYCL_EXTERNAL void
-__esimd_flat_write(sycl::intel::gpu::vector_type_t<uint64_t, N> addrs,
-                   sycl::intel::gpu::vector_type_t<
-                       Ty, N * sycl::intel::gpu::ElemsPerAddrDecoding(NumBlk)>
+__esimd_flat_write(sycl::INTEL::gpu::vector_type_t<uint64_t, N> addrs,
+                   sycl::INTEL::gpu::vector_type_t<
+                       Ty, N * sycl::INTEL::gpu::ElemsPerAddrDecoding(NumBlk)>
                        vals,
                    int ElemsPerAddr = NumBlk,
-                   sycl::intel::gpu::vector_type_t<uint16_t, N> pred = 1);
+                   sycl::INTEL::gpu::vector_type_t<uint16_t, N> pred = 1);
 
 // flat_block_read reads a block of data from one flat address
 template <typename Ty, int N,
-          sycl::intel::gpu::CacheHint L1H = sycl::intel::gpu::CacheHint::None,
-          sycl::intel::gpu::CacheHint L3H = sycl::intel::gpu::CacheHint::None>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N>
+          sycl::INTEL::gpu::CacheHint L1H = sycl::INTEL::gpu::CacheHint::None,
+          sycl::INTEL::gpu::CacheHint L3H = sycl::INTEL::gpu::CacheHint::None>
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N>
 __esimd_flat_block_read_unaligned(uint64_t addr);
 
 // flat_block_write writes a block of data using one flat address
 template <typename Ty, int N,
-          sycl::intel::gpu::CacheHint L1H = sycl::intel::gpu::CacheHint::None,
-          sycl::intel::gpu::CacheHint L3H = sycl::intel::gpu::CacheHint::None>
+          sycl::INTEL::gpu::CacheHint L1H = sycl::INTEL::gpu::CacheHint::None,
+          sycl::INTEL::gpu::CacheHint L3H = sycl::INTEL::gpu::CacheHint::None>
 SYCL_EXTERNAL void
 __esimd_flat_block_write(uint64_t addr,
-                         sycl::intel::gpu::vector_type_t<Ty, N> vals);
+                         sycl::INTEL::gpu::vector_type_t<Ty, N> vals);
 
 // Reads a block of data from given surface at given offset.
 template <typename Ty, int N, typename SurfIndAliasTy>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N>
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N>
 __esimd_block_read(SurfIndAliasTy surf_ind, uint32_t offset);
 
 // Writes given block of data to a surface with given index at given offset.
 template <typename Ty, int N, typename SurfIndAliasTy>
 SYCL_EXTERNAL void
 __esimd_block_write(SurfIndAliasTy surf_ind, uint32_t offset,
-                    sycl::intel::gpu::vector_type_t<Ty, N> vals);
+                    sycl::INTEL::gpu::vector_type_t<Ty, N> vals);
 
 // flat_read4 does flat-address gather4
-template <typename Ty, int N, sycl::intel::gpu::ChannelMaskType Mask,
-          sycl::intel::gpu::CacheHint L1H = sycl::intel::gpu::CacheHint::None,
-          sycl::intel::gpu::CacheHint L3H = sycl::intel::gpu::CacheHint::None>
-sycl::intel::gpu::vector_type_t<Ty, N * NumChannels(Mask)> SYCL_EXTERNAL
-__esimd_flat_read4(sycl::intel::gpu::vector_type_t<uint64_t, N> addrs,
-                   sycl::intel::gpu::vector_type_t<uint16_t, N> pred = 1);
+template <typename Ty, int N, sycl::INTEL::gpu::ChannelMaskType Mask,
+          sycl::INTEL::gpu::CacheHint L1H = sycl::INTEL::gpu::CacheHint::None,
+          sycl::INTEL::gpu::CacheHint L3H = sycl::INTEL::gpu::CacheHint::None>
+sycl::INTEL::gpu::vector_type_t<Ty, N * NumChannels(Mask)> SYCL_EXTERNAL
+__esimd_flat_read4(sycl::INTEL::gpu::vector_type_t<uint64_t, N> addrs,
+                   sycl::INTEL::gpu::vector_type_t<uint16_t, N> pred = 1);
 
 // flat_write does flat-address scatter
-template <typename Ty, int N, sycl::intel::gpu::ChannelMaskType Mask,
-          sycl::intel::gpu::CacheHint L1H = sycl::intel::gpu::CacheHint::None,
-          sycl::intel::gpu::CacheHint L3H = sycl::intel::gpu::CacheHint::None>
+template <typename Ty, int N, sycl::INTEL::gpu::ChannelMaskType Mask,
+          sycl::INTEL::gpu::CacheHint L1H = sycl::INTEL::gpu::CacheHint::None,
+          sycl::INTEL::gpu::CacheHint L3H = sycl::INTEL::gpu::CacheHint::None>
 SYCL_EXTERNAL void __esimd_flat_write4(
-    sycl::intel::gpu::vector_type_t<uint64_t, N> addrs,
-    sycl::intel::gpu::vector_type_t<Ty, N * NumChannels(Mask)> vals,
-    sycl::intel::gpu::vector_type_t<uint16_t, N> pred = 1);
+    sycl::INTEL::gpu::vector_type_t<uint64_t, N> addrs,
+    sycl::INTEL::gpu::vector_type_t<Ty, N * NumChannels(Mask)> vals,
+    sycl::INTEL::gpu::vector_type_t<uint16_t, N> pred = 1);
 
 // flat_atomic: flat-address atomic
-template <sycl::intel::gpu::EsimdAtomicOpType Op, typename Ty, int N,
-          sycl::intel::gpu::CacheHint L1H = sycl::intel::gpu::CacheHint::None,
-          sycl::intel::gpu::CacheHint L3H = sycl::intel::gpu::CacheHint::None>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N>
-__esimd_flat_atomic0(sycl::intel::gpu::vector_type_t<uint64_t, N> addrs,
-                     sycl::intel::gpu::vector_type_t<uint16_t, N> pred);
-
-template <sycl::intel::gpu::EsimdAtomicOpType Op, typename Ty, int N,
-          sycl::intel::gpu::CacheHint L1H = sycl::intel::gpu::CacheHint::None,
-          sycl::intel::gpu::CacheHint L3H = sycl::intel::gpu::CacheHint::None>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N>
-__esimd_flat_atomic1(sycl::intel::gpu::vector_type_t<uint64_t, N> addrs,
-                     sycl::intel::gpu::vector_type_t<Ty, N> src0,
-                     sycl::intel::gpu::vector_type_t<uint16_t, N> pred);
-
-template <sycl::intel::gpu::EsimdAtomicOpType Op, typename Ty, int N,
-          sycl::intel::gpu::CacheHint L1H = sycl::intel::gpu::CacheHint::None,
-          sycl::intel::gpu::CacheHint L3H = sycl::intel::gpu::CacheHint::None>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N>
-__esimd_flat_atomic2(sycl::intel::gpu::vector_type_t<uint64_t, N> addrs,
-                     sycl::intel::gpu::vector_type_t<Ty, N> src0,
-                     sycl::intel::gpu::vector_type_t<Ty, N> src1,
-                     sycl::intel::gpu::vector_type_t<uint16_t, N> pred);
+template <sycl::INTEL::gpu::EsimdAtomicOpType Op, typename Ty, int N,
+          sycl::INTEL::gpu::CacheHint L1H = sycl::INTEL::gpu::CacheHint::None,
+          sycl::INTEL::gpu::CacheHint L3H = sycl::INTEL::gpu::CacheHint::None>
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N>
+__esimd_flat_atomic0(sycl::INTEL::gpu::vector_type_t<uint64_t, N> addrs,
+                     sycl::INTEL::gpu::vector_type_t<uint16_t, N> pred);
+
+template <sycl::INTEL::gpu::EsimdAtomicOpType Op, typename Ty, int N,
+          sycl::INTEL::gpu::CacheHint L1H = sycl::INTEL::gpu::CacheHint::None,
+          sycl::INTEL::gpu::CacheHint L3H = sycl::INTEL::gpu::CacheHint::None>
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N>
+__esimd_flat_atomic1(sycl::INTEL::gpu::vector_type_t<uint64_t, N> addrs,
+                     sycl::INTEL::gpu::vector_type_t<Ty, N> src0,
+                     sycl::INTEL::gpu::vector_type_t<uint16_t, N> pred);
+
+template <sycl::INTEL::gpu::EsimdAtomicOpType Op, typename Ty, int N,
+          sycl::INTEL::gpu::CacheHint L1H = sycl::INTEL::gpu::CacheHint::None,
+          sycl::INTEL::gpu::CacheHint L3H = sycl::INTEL::gpu::CacheHint::None>
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N>
+__esimd_flat_atomic2(sycl::INTEL::gpu::vector_type_t<uint64_t, N> addrs,
+                     sycl::INTEL::gpu::vector_type_t<Ty, N> src0,
+                     sycl::INTEL::gpu::vector_type_t<Ty, N> src1,
+                     sycl::INTEL::gpu::vector_type_t<uint16_t, N> pred);
 
 // esimd_barrier, generic group barrier
 SYCL_EXTERNAL void __esimd_barrier();
@@ -114,59 +114,59 @@ SYCL_EXTERNAL void __esimd_slm_fence(uint8_t cntl);
 
 // slm_read does SLM gather
 template <typename Ty, int N>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N>
-__esimd_slm_read(sycl::intel::gpu::vector_type_t<uint32_t, N> addrs,
-                 sycl::intel::gpu::vector_type_t<uint16_t, N> pred = 1);
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N>
+__esimd_slm_read(sycl::INTEL::gpu::vector_type_t<uint32_t, N> addrs,
+                 sycl::INTEL::gpu::vector_type_t<uint16_t, N> pred = 1);
 
 // slm_write does SLM scatter
 template <typename Ty, int N>
 SYCL_EXTERNAL void
-__esimd_slm_write(sycl::intel::gpu::vector_type_t<uint32_t, N> addrs,
-                  sycl::intel::gpu::vector_type_t<Ty, N> vals,
-                  sycl::intel::gpu::vector_type_t<uint16_t, N> pred = 1);
+__esimd_slm_write(sycl::INTEL::gpu::vector_type_t<uint32_t, N> addrs,
+                  sycl::INTEL::gpu::vector_type_t<Ty, N> vals,
+                  sycl::INTEL::gpu::vector_type_t<uint16_t, N> pred = 1);
 
 // slm_block_read reads a block of data from SLM
 template <typename Ty, int N>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N>
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N>
 __esimd_slm_block_read(uint32_t addr);
 
 // slm_block_write writes a block of data to SLM
 template <typename Ty, int N>
 SYCL_EXTERNAL void
 __esimd_slm_block_write(uint32_t addr,
-                        sycl::intel::gpu::vector_type_t<Ty, N> vals);
+                        sycl::INTEL::gpu::vector_type_t<Ty, N> vals);
 
 // slm_read4 does SLM gather4
-template <typename Ty, int N, sycl::intel::gpu::ChannelMaskType Mask>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N * NumChannels(Mask)>
-__esimd_slm_read4(sycl::intel::gpu::vector_type_t<uint32_t, N> addrs,
-                  sycl::intel::gpu::vector_type_t<uint16_t, N> pred = 1);
+template <typename Ty, int N, sycl::INTEL::gpu::ChannelMaskType Mask>
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N * NumChannels(Mask)>
+__esimd_slm_read4(sycl::INTEL::gpu::vector_type_t<uint32_t, N> addrs,
+                  sycl::INTEL::gpu::vector_type_t<uint16_t, N> pred = 1);
 
 // slm_write4 does SLM scatter4
-template <typename Ty, int N, sycl::intel::gpu::ChannelMaskType Mask>
+template <typename Ty, int N, sycl::INTEL::gpu::ChannelMaskType Mask>
 SYCL_EXTERNAL void __esimd_slm_write4(
-    sycl::intel::gpu::vector_type_t<uint32_t, N> addrs,
-    sycl::intel::gpu::vector_type_t<Ty, N * NumChannels(Mask)> vals,
-    sycl::intel::gpu::vector_type_t<uint16_t, N> pred = 1);
+    sycl::INTEL::gpu::vector_type_t<uint32_t, N> addrs,
+    sycl::INTEL::gpu::vector_type_t<Ty, N * NumChannels(Mask)> vals,
+    sycl::INTEL::gpu::vector_type_t<uint16_t, N> pred = 1);
 
 // slm_atomic: SLM atomic
-template <sycl::intel::gpu::EsimdAtomicOpType Op, typename Ty, int N>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N>
-__esimd_slm_atomic0(sycl::intel::gpu::vector_type_t<uint32_t, N> addrs,
-                    sycl::intel::gpu::vector_type_t<uint16_t, N> pred);
-
-template <sycl::intel::gpu::EsimdAtomicOpType Op, typename Ty, int N>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N>
-__esimd_slm_atomic1(sycl::intel::gpu::vector_type_t<uint32_t, N> addrs,
-                    sycl::intel::gpu::vector_type_t<Ty, N> src0,
-                    sycl::intel::gpu::vector_type_t<uint16_t, N> pred);
-
-template <sycl::intel::gpu::EsimdAtomicOpType Op, typename Ty, int N>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N>
-__esimd_slm_atomic2(sycl::intel::gpu::vector_type_t<uint32_t, N> addrs,
-                    sycl::intel::gpu::vector_type_t<Ty, N> src0,
-                    sycl::intel::gpu::vector_type_t<Ty, N> src1,
-                    sycl::intel::gpu::vector_type_t<uint16_t, N> pred);
+template <sycl::INTEL::gpu::EsimdAtomicOpType Op, typename Ty, int N>
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N>
+__esimd_slm_atomic0(sycl::INTEL::gpu::vector_type_t<uint32_t, N> addrs,
+                    sycl::INTEL::gpu::vector_type_t<uint16_t, N> pred);
+
+template <sycl::INTEL::gpu::EsimdAtomicOpType Op, typename Ty, int N>
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N>
+__esimd_slm_atomic1(sycl::INTEL::gpu::vector_type_t<uint32_t, N> addrs,
+                    sycl::INTEL::gpu::vector_type_t<Ty, N> src0,
+                    sycl::INTEL::gpu::vector_type_t<uint16_t, N> pred);
+
+template <sycl::INTEL::gpu::EsimdAtomicOpType Op, typename Ty, int N>
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N>
+__esimd_slm_atomic2(sycl::INTEL::gpu::vector_type_t<uint32_t, N> addrs,
+                    sycl::INTEL::gpu::vector_type_t<Ty, N> src0,
+                    sycl::INTEL::gpu::vector_type_t<Ty, N> src1,
+                    sycl::INTEL::gpu::vector_type_t<uint16_t, N> pred);
 
 // Media block load
 //
@@ -193,7 +193,7 @@ __esimd_slm_atomic2(sycl::intel::gpu::vector_type_t<uint32_t, N> addrs,
 // @return the linearized 2D block data read from surface.
 //
 template <typename Ty, int M, int N, typename TACC>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, M * N>
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, M * N>
 __esimd_media_block_load(unsigned modififer, TACC handle, unsigned plane,
                          unsigned width, unsigned x, unsigned y);
 
@@ -225,22 +225,22 @@ template <typename Ty, int M, int N, typename TACC>
 SYCL_EXTERNAL void
 __esimd_media_block_store(unsigned modififer, TACC handle, unsigned plane,
                           unsigned width, unsigned x, unsigned y,
-                          sycl::intel::gpu::vector_type_t<Ty, M * N> vals);
+                          sycl::INTEL::gpu::vector_type_t<Ty, M * N> vals);
 
 #ifndef __SYCL_DEVICE_ONLY__
 
-template <typename Ty, int N, int NumBlk, sycl::intel::gpu::CacheHint L1H,
-          sycl::intel::gpu::CacheHint L3H>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<
-    Ty, N * sycl::intel::gpu::ElemsPerAddrDecoding(NumBlk)>
-__esimd_flat_read(sycl::intel::gpu::vector_type_t<uint64_t, N> addrs,
+template <typename Ty, int N, int NumBlk, sycl::INTEL::gpu::CacheHint L1H,
+          sycl::INTEL::gpu::CacheHint L3H>
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<
+    Ty, N * sycl::INTEL::gpu::ElemsPerAddrDecoding(NumBlk)>
+__esimd_flat_read(sycl::INTEL::gpu::vector_type_t<uint64_t, N> addrs,
                   int ElemsPerAddr,
-                  sycl::intel::gpu::vector_type_t<uint16_t, N> pred) {
-  auto NumBlkDecoded = sycl::intel::gpu::ElemsPerAddrDecoding(NumBlk);
-  sycl::intel::gpu::vector_type_t<
-      Ty, N * sycl::intel::gpu::ElemsPerAddrDecoding(NumBlk)>
+                  sycl::INTEL::gpu::vector_type_t<uint16_t, N> pred) {
+  auto NumBlkDecoded = sycl::INTEL::gpu::ElemsPerAddrDecoding(NumBlk);
+  sycl::INTEL::gpu::vector_type_t<
+      Ty, N * sycl::INTEL::gpu::ElemsPerAddrDecoding(NumBlk)>
       V;
-  ElemsPerAddr = sycl::intel::gpu::ElemsPerAddrDecoding(ElemsPerAddr);
+  ElemsPerAddr = sycl::INTEL::gpu::ElemsPerAddrDecoding(ElemsPerAddr);
 
   for (int I = 0; I < N; I++) {
     if (pred[I]) {
@@ -259,12 +259,12 @@ __esimd_flat_read(sycl::intel::gpu::vector_type_t<uint64_t, N> addrs,
   return V;
 }
 
-template <typename Ty, int N, sycl::intel::gpu::ChannelMaskType Mask,
-          sycl::intel::gpu::CacheHint L1H, sycl::intel::gpu::CacheHint L3H>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N * NumChannels(Mask)>
-__esimd_flat_read4(sycl::intel::gpu::vector_type_t<uint64_t, N> addrs,
-                   sycl::intel::gpu::vector_type_t<uint16_t, N> pred) {
-  sycl::intel::gpu::vector_type_t<Ty, N * NumChannels(Mask)> V;
+template <typename Ty, int N, sycl::INTEL::gpu::ChannelMaskType Mask,
+          sycl::INTEL::gpu::CacheHint L1H, sycl::INTEL::gpu::CacheHint L3H>
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N * NumChannels(Mask)>
+__esimd_flat_read4(sycl::INTEL::gpu::vector_type_t<uint64_t, N> addrs,
+                   sycl::INTEL::gpu::vector_type_t<uint16_t, N> pred) {
+  sycl::INTEL::gpu::vector_type_t<Ty, N * NumChannels(Mask)> V;
   unsigned int Next = 0;
 
   if constexpr (HasR(Mask)) {
@@ -307,17 +307,17 @@ __esimd_flat_read4(sycl::intel::gpu::vector_type_t<uint64_t, N> addrs,
   return V;
 }
 
-template <typename Ty, int N, int NumBlk, sycl::intel::gpu::CacheHint L1H,
-          sycl::intel::gpu::CacheHint L3H>
+template <typename Ty, int N, int NumBlk, sycl::INTEL::gpu::CacheHint L1H,
+          sycl::INTEL::gpu::CacheHint L3H>
 SYCL_EXTERNAL void
-__esimd_flat_write(sycl::intel::gpu::vector_type_t<uint64_t, N> addrs,
-                   sycl::intel::gpu::vector_type_t<
-                       Ty, N * sycl::intel::gpu::ElemsPerAddrDecoding(NumBlk)>
+__esimd_flat_write(sycl::INTEL::gpu::vector_type_t<uint64_t, N> addrs,
+                   sycl::INTEL::gpu::vector_type_t<
+                       Ty, N * sycl::INTEL::gpu::ElemsPerAddrDecoding(NumBlk)>
                        vals,
                    int ElemsPerAddr,
-                   sycl::intel::gpu::vector_type_t<uint16_t, N> pred) {
-  auto NumBlkDecoded = sycl::intel::gpu::ElemsPerAddrDecoding(NumBlk);
-  ElemsPerAddr = sycl::intel::gpu::ElemsPerAddrDecoding(ElemsPerAddr);
+                   sycl::INTEL::gpu::vector_type_t<uint16_t, N> pred) {
+  auto NumBlkDecoded = sycl::INTEL::gpu::ElemsPerAddrDecoding(NumBlk);
+  ElemsPerAddr = sycl::INTEL::gpu::ElemsPerAddrDecoding(ElemsPerAddr);
 
   for (int I = 0; I < N; I++) {
     if (pred[I]) {
@@ -335,13 +335,13 @@ __esimd_flat_write(sycl::intel::gpu::vector_type_t<uint64_t, N> addrs,
   }
 }
 
-template <typename Ty, int N, sycl::intel::gpu::ChannelMaskType Mask,
-          sycl::intel::gpu::CacheHint L1H, sycl::intel::gpu::CacheHint L3H>
+template <typename Ty, int N, sycl::INTEL::gpu::ChannelMaskType Mask,
+          sycl::INTEL::gpu::CacheHint L1H, sycl::INTEL::gpu::CacheHint L3H>
 SYCL_EXTERNAL void __esimd_flat_write4(
-    sycl::intel::gpu::vector_type_t<uint64_t, N> addrs,
-    sycl::intel::gpu::vector_type_t<Ty, N * NumChannels(Mask)> vals,
-    sycl::intel::gpu::vector_type_t<uint16_t, N> pred) {
-  sycl::intel::gpu::vector_type_t<Ty, N * NumChannels(Mask)> V;
+    sycl::INTEL::gpu::vector_type_t<uint64_t, N> addrs,
+    sycl::INTEL::gpu::vector_type_t<Ty, N * NumChannels(Mask)> vals,
+    sycl::INTEL::gpu::vector_type_t<uint16_t, N> pred) {
+  sycl::INTEL::gpu::vector_type_t<Ty, N * NumChannels(Mask)> V;
   unsigned int Next = 0;
 
   if constexpr (HasR(Mask)) {
@@ -382,11 +382,11 @@ SYCL_EXTERNAL void __esimd_flat_write4(
   }
 }
 
-template <typename Ty, int N, sycl::intel::gpu::CacheHint L1H,
-          sycl::intel::gpu::CacheHint L3H>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N>
+template <typename Ty, int N, sycl::INTEL::gpu::CacheHint L1H,
+          sycl::INTEL::gpu::CacheHint L3H>
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N>
 __esimd_flat_block_read_unaligned(uint64_t addr) {
-  sycl::intel::gpu::vector_type_t<Ty, N> V;
+  sycl::INTEL::gpu::vector_type_t<Ty, N> V;
 
   for (int I = 0; I < N; I++) {
     Ty *Addr = reinterpret_cast<Ty *>(addr + I * sizeof(Ty));
@@ -395,11 +395,11 @@ __esimd_flat_block_read_unaligned(uint64_t addr) {
   return V;
 }
 
-template <typename Ty, int N, sycl::intel::gpu::CacheHint L1H,
-          sycl::intel::gpu::CacheHint L3H>
+template <typename Ty, int N, sycl::INTEL::gpu::CacheHint L1H,
+          sycl::INTEL::gpu::CacheHint L3H>
 SYCL_EXTERNAL void
 __esimd_flat_block_write(uint64_t addr,
-                         sycl::intel::gpu::vector_type_t<Ty, N> vals) {
+                         sycl::INTEL::gpu::vector_type_t<Ty, N> vals) {
   for (int I = 0; I < N; I++) {
     Ty *Addr = reinterpret_cast<Ty *>(addr + I * sizeof(Ty));
     *Addr = vals[I];
@@ -407,14 +407,14 @@ __esimd_flat_block_write(uint64_t addr,
 }
 
 template <typename Ty, int M, int N, typename TACC>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, M * N>
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, M * N>
 __esimd_media_block_load(unsigned modififer, TACC handle, unsigned plane,
                          unsigned width, unsigned x, unsigned y) {
   // On host the input surface is modeled as sycl image 2d object,
   // and the read/write access is done through accessor,
   // which is passed in as the handle argument.
-  auto range = sycl::intel::gpu::AccessorPrivateProxy::getImageRange(handle);
-  unsigned bpp = sycl::intel::gpu::AccessorPrivateProxy::getElemSize(handle);
+  auto range = sycl::INTEL::gpu::AccessorPrivateProxy::getImageRange(handle);
+  unsigned bpp = sycl::INTEL::gpu::AccessorPrivateProxy::getElemSize(handle);
   unsigned vpp = bpp / sizeof(Ty);
   unsigned int i = x / bpp;
   unsigned int j = y;
@@ -423,7 +423,7 @@ __esimd_media_block_load(unsigned modififer, TACC handle, unsigned plane,
   unsigned int xbound = range[0] - 1;
   unsigned int ybound = range[1] - 1;
 
-  sycl::intel::gpu::vector_type_t<Ty, M * N> vals;
+  sycl::INTEL::gpu::vector_type_t<Ty, M * N> vals;
   for (int row = 0; row < M; row++) {
     for (int col = 0; col < N; col += vpp) {
       unsigned int xoff = (i > xbound) ? xbound : i;
@@ -431,14 +431,14 @@ __esimd_media_block_load(unsigned modififer, TACC handle, unsigned plane,
       auto coords = cl::sycl::cl_int2(xoff, yoff);
       cl::sycl::cl_uint4 data = handle.read(coords);
 
-      sycl::intel::gpu::vector_type_t<unsigned int, 4> res;
+      sycl::INTEL::gpu::vector_type_t<unsigned int, 4> res;
       for (int idx = 0; idx < 4; idx++) {
         res[idx] = data[idx];
       }
 
       constexpr int refN = sizeof(cl::sycl::cl_uint4) / sizeof(Ty);
       unsigned int stride = sizeof(cl::sycl::cl_uint4) / bpp;
-      using refTy = sycl::intel::gpu::vector_type_t<Ty, refN>;
+      using refTy = sycl::INTEL::gpu::vector_type_t<Ty, refN>;
       auto ref = reinterpret_cast<refTy>(res);
 
       unsigned int offset1 = col + row * N;
@@ -461,10 +461,10 @@ template <typename Ty, int M, int N, typename TACC>
 SYCL_EXTERNAL void
 __esimd_media_block_store(unsigned modififer, TACC handle, unsigned plane,
                           unsigned width, unsigned x, unsigned y,
-                          sycl::intel::gpu::vector_type_t<Ty, M * N> vals) {
-  unsigned bpp = sycl::intel::gpu::AccessorPrivateProxy::getElemSize(handle);
+                          sycl::INTEL::gpu::vector_type_t<Ty, M * N> vals) {
+  unsigned bpp = sycl::INTEL::gpu::AccessorPrivateProxy::getElemSize(handle);
   unsigned vpp = bpp / sizeof(Ty);
-  auto range = sycl::intel::gpu::AccessorPrivateProxy::getImageRange(handle);
+  auto range = sycl::INTEL::gpu::AccessorPrivateProxy::getImageRange(handle);
   unsigned int i = x / bpp;
   unsigned int j = y;
 
@@ -473,7 +473,7 @@ __esimd_media_block_store(unsigned modififer, TACC handle, unsigned plane,
   for (int row = 0; row < M; row++) {
     for (int col = 0; col < N; col += vpp) {
       constexpr int Sz = sizeof(cl::sycl::cl_uint4) / sizeof(Ty);
-      sycl::intel::gpu::vector_type_t<Ty, Sz> res = 0;
+      sycl::INTEL::gpu::vector_type_t<Ty, Sz> res = 0;
 
       unsigned int offset1 = col + row * N;
       unsigned int offset2 = 0;
@@ -484,7 +484,7 @@ __esimd_media_block_store(unsigned modififer, TACC handle, unsigned plane,
         offset2 += stride;
       }
 
-      using refTy = sycl::intel::gpu::vector_type_t<unsigned int, 4>;
+      using refTy = sycl::INTEL::gpu::vector_type_t<unsigned int, 4>;
       auto ref = reinterpret_cast<refTy>(res);
 
       cl::sycl::cl_uint4 data;
@@ -504,7 +504,7 @@ __esimd_media_block_store(unsigned modififer, TACC handle, unsigned plane,
 }
 
 template <typename Ty, int N>
-SYCL_EXTERNAL uint16_t __esimd_any(sycl::intel::gpu::vector_type_t<Ty, N> src) {
+SYCL_EXTERNAL uint16_t __esimd_any(sycl::INTEL::gpu::vector_type_t<Ty, N> src) {
   for (unsigned int i = 0; i != N; i++) {
     if (src[i] != 0)
       return 1;
@@ -513,7 +513,7 @@ SYCL_EXTERNAL uint16_t __esimd_any(sycl::intel::gpu::vector_type_t<Ty, N> src) {
 }
 
 template <typename Ty, int N>
-SYCL_EXTERNAL uint16_t __esimd_all(sycl::intel::gpu::vector_type_t<Ty, N> src) {
+SYCL_EXTERNAL uint16_t __esimd_all(sycl::INTEL::gpu::vector_type_t<Ty, N> src) {
   for (unsigned int i = 0; i != N; i++) {
     if (src[i] == 0)
       return 0;
@@ -522,10 +522,10 @@ SYCL_EXTERNAL uint16_t __esimd_all(sycl::intel::gpu::vector_type_t<Ty, N> src) {
 }
 
 template <typename Ty, int N>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N>
-__esimd_dp4(sycl::intel::gpu::vector_type_t<Ty, N> v1,
-            sycl::intel::gpu::vector_type_t<Ty, N> v2) {
-  sycl::intel::gpu::vector_type_t<Ty, N> retv;
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N>
+__esimd_dp4(sycl::INTEL::gpu::vector_type_t<Ty, N> v1,
+            sycl::INTEL::gpu::vector_type_t<Ty, N> v2) {
+  sycl::INTEL::gpu::vector_type_t<Ty, N> retv;
   for (auto i = 0; i != N; i += 4) {
     Ty dp = (v1[i] * v2[i]) + (v1[i + 1] * v2[i + 1]) +
             (v1[i + 2] * v2[i + 2]) + (v1[i + 3] * v2[i + 3]);
@@ -543,25 +543,25 @@ SYCL_EXTERNAL void __esimd_barrier() {}
 SYCL_EXTERNAL void __esimd_slm_fence(uint8_t cntl) {}
 
 template <typename Ty, int N>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N>
-__esimd_slm_read(sycl::intel::gpu::vector_type_t<uint32_t, N> addrs,
-                 sycl::intel::gpu::vector_type_t<uint16_t, N> pred) {
-  sycl::intel::gpu::vector_type_t<Ty, N> retv;
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N>
+__esimd_slm_read(sycl::INTEL::gpu::vector_type_t<uint32_t, N> addrs,
+                 sycl::INTEL::gpu::vector_type_t<uint16_t, N> pred) {
+  sycl::INTEL::gpu::vector_type_t<Ty, N> retv;
   return retv;
 }
 
 // slm_write does SLM scatter
 template <typename Ty, int N>
 SYCL_EXTERNAL void
-__esimd_slm_write(sycl::intel::gpu::vector_type_t<uint32_t, N> addrs,
-                  sycl::intel::gpu::vector_type_t<Ty, N> vals,
-                  sycl::intel::gpu::vector_type_t<uint16_t, N> pred) {}
+__esimd_slm_write(sycl::INTEL::gpu::vector_type_t<uint32_t, N> addrs,
+                  sycl::INTEL::gpu::vector_type_t<Ty, N> vals,
+                  sycl::INTEL::gpu::vector_type_t<uint16_t, N> pred) {}
 
 // slm_block_read reads a block of data from SLM
 template <typename Ty, int N>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N>
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N>
 __esimd_slm_block_read(uint32_t addr) {
-  sycl::intel::gpu::vector_type_t<Ty, N> retv;
+  sycl::INTEL::gpu::vector_type_t<Ty, N> retv;
   return retv;
 }
 
@@ -569,93 +569,93 @@ __esimd_slm_block_read(uint32_t addr) {
 template <typename Ty, int N>
 SYCL_EXTERNAL void
 __esimd_slm_block_write(uint32_t addr,
-                        sycl::intel::gpu::vector_type_t<Ty, N> vals) {}
+                        sycl::INTEL::gpu::vector_type_t<Ty, N> vals) {}
 
 // slm_read4 does SLM gather4
-template <typename Ty, int N, sycl::intel::gpu::ChannelMaskType Mask>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N * NumChannels(Mask)>
-__esimd_slm_read4(sycl::intel::gpu::vector_type_t<uint32_t, N> addrs,
-                  sycl::intel::gpu::vector_type_t<uint16_t, N> pred) {
-  sycl::intel::gpu::vector_type_t<Ty, N * NumChannels(Mask)> retv;
+template <typename Ty, int N, sycl::INTEL::gpu::ChannelMaskType Mask>
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N * NumChannels(Mask)>
+__esimd_slm_read4(sycl::INTEL::gpu::vector_type_t<uint32_t, N> addrs,
+                  sycl::INTEL::gpu::vector_type_t<uint16_t, N> pred) {
+  sycl::INTEL::gpu::vector_type_t<Ty, N * NumChannels(Mask)> retv;
   return retv;
 }
 
 // slm_write4 does SLM scatter4
-template <typename Ty, int N, sycl::intel::gpu::ChannelMaskType Mask>
+template <typename Ty, int N, sycl::INTEL::gpu::ChannelMaskType Mask>
 SYCL_EXTERNAL void __esimd_slm_write4(
-    sycl::intel::gpu::vector_type_t<uint32_t, N> addrs,
-    sycl::intel::gpu::vector_type_t<Ty, N * NumChannels(Mask)> vals,
-    sycl::intel::gpu::vector_type_t<uint16_t, N> pred) {}
+    sycl::INTEL::gpu::vector_type_t<uint32_t, N> addrs,
+    sycl::INTEL::gpu::vector_type_t<Ty, N * NumChannels(Mask)> vals,
+    sycl::INTEL::gpu::vector_type_t<uint16_t, N> pred) {}
 
 // slm_atomic: SLM atomic
-template <sycl::intel::gpu::EsimdAtomicOpType Op, typename Ty, int N>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N>
-__esimd_slm_atomic0(sycl::intel::gpu::vector_type_t<uint32_t, N> addrs,
-                    sycl::intel::gpu::vector_type_t<uint16_t, N> pred) {
-  sycl::intel::gpu::vector_type_t<Ty, N> retv;
+template <sycl::INTEL::gpu::EsimdAtomicOpType Op, typename Ty, int N>
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N>
+__esimd_slm_atomic0(sycl::INTEL::gpu::vector_type_t<uint32_t, N> addrs,
+                    sycl::INTEL::gpu::vector_type_t<uint16_t, N> pred) {
+  sycl::INTEL::gpu::vector_type_t<Ty, N> retv;
   return retv;
 }
 
-template <sycl::intel::gpu::EsimdAtomicOpType Op, typename Ty, int N>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N>
-__esimd_slm_atomic1(sycl::intel::gpu::vector_type_t<uint32_t, N> addrs,
-                    sycl::intel::gpu::vector_type_t<Ty, N> src0,
-                    sycl::intel::gpu::vector_type_t<uint16_t, N> pred) {
-  sycl::intel::gpu::vector_type_t<Ty, N> retv;
+template <sycl::INTEL::gpu::EsimdAtomicOpType Op, typename Ty, int N>
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N>
+__esimd_slm_atomic1(sycl::INTEL::gpu::vector_type_t<uint32_t, N> addrs,
+                    sycl::INTEL::gpu::vector_type_t<Ty, N> src0,
+                    sycl::INTEL::gpu::vector_type_t<uint16_t, N> pred) {
+  sycl::INTEL::gpu::vector_type_t<Ty, N> retv;
   return retv;
 }
 
-template <sycl::intel::gpu::EsimdAtomicOpType Op, typename Ty, int N>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N>
-__esimd_slm_atomic2(sycl::intel::gpu::vector_type_t<uint32_t, N> addrs,
-                    sycl::intel::gpu::vector_type_t<Ty, N> src0,
-                    sycl::intel::gpu::vector_type_t<Ty, N> src1,
-                    sycl::intel::gpu::vector_type_t<uint16_t, N> pred) {
-  sycl::intel::gpu::vector_type_t<Ty, N> retv;
+template <sycl::INTEL::gpu::EsimdAtomicOpType Op, typename Ty, int N>
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N>
+__esimd_slm_atomic2(sycl::INTEL::gpu::vector_type_t<uint32_t, N> addrs,
+                    sycl::INTEL::gpu::vector_type_t<Ty, N> src0,
+                    sycl::INTEL::gpu::vector_type_t<Ty, N> src1,
+                    sycl::INTEL::gpu::vector_type_t<uint16_t, N> pred) {
+  sycl::INTEL::gpu::vector_type_t<Ty, N> retv;
   return retv;
 }
 
-template <sycl::intel::gpu::EsimdAtomicOpType Op, typename Ty, int N,
-          sycl::intel::gpu::CacheHint L1H, sycl::intel::gpu::CacheHint L3H>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N>
-__esimd_flat_atomic0(sycl::intel::gpu::vector_type_t<uint64_t, N> addrs,
-                     sycl::intel::gpu::vector_type_t<uint16_t, N> pred) {
-  sycl::intel::gpu::vector_type_t<Ty, N> retv;
+template <sycl::INTEL::gpu::EsimdAtomicOpType Op, typename Ty, int N,
+          sycl::INTEL::gpu::CacheHint L1H, sycl::INTEL::gpu::CacheHint L3H>
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N>
+__esimd_flat_atomic0(sycl::INTEL::gpu::vector_type_t<uint64_t, N> addrs,
+                     sycl::INTEL::gpu::vector_type_t<uint16_t, N> pred) {
+  sycl::INTEL::gpu::vector_type_t<Ty, N> retv;
   return retv;
 }
 
-template <sycl::intel::gpu::EsimdAtomicOpType Op, typename Ty, int N,
-          sycl::intel::gpu::CacheHint L1H, sycl::intel::gpu::CacheHint L3H>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N>
-__esimd_flat_atomic1(sycl::intel::gpu::vector_type_t<uint64_t, N> addrs,
-                     sycl::intel::gpu::vector_type_t<Ty, N> src0,
-                     sycl::intel::gpu::vector_type_t<uint16_t, N> pred) {
-  sycl::intel::gpu::vector_type_t<Ty, N> retv;
+template <sycl::INTEL::gpu::EsimdAtomicOpType Op, typename Ty, int N,
+          sycl::INTEL::gpu::CacheHint L1H, sycl::INTEL::gpu::CacheHint L3H>
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N>
+__esimd_flat_atomic1(sycl::INTEL::gpu::vector_type_t<uint64_t, N> addrs,
+                     sycl::INTEL::gpu::vector_type_t<Ty, N> src0,
+                     sycl::INTEL::gpu::vector_type_t<uint16_t, N> pred) {
+  sycl::INTEL::gpu::vector_type_t<Ty, N> retv;
   return retv;
 }
 
-template <sycl::intel::gpu::EsimdAtomicOpType Op, typename Ty, int N,
-          sycl::intel::gpu::CacheHint L1H, sycl::intel::gpu::CacheHint L3H>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N>
-__esimd_flat_atomic2(sycl::intel::gpu::vector_type_t<uint64_t, N> addrs,
-                     sycl::intel::gpu::vector_type_t<Ty, N> src0,
-                     sycl::intel::gpu::vector_type_t<Ty, N> src1,
-                     sycl::intel::gpu::vector_type_t<uint16_t, N> pred) {
-  sycl::intel::gpu::vector_type_t<Ty, N> retv;
+template <sycl::INTEL::gpu::EsimdAtomicOpType Op, typename Ty, int N,
+          sycl::INTEL::gpu::CacheHint L1H, sycl::INTEL::gpu::CacheHint L3H>
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N>
+__esimd_flat_atomic2(sycl::INTEL::gpu::vector_type_t<uint64_t, N> addrs,
+                     sycl::INTEL::gpu::vector_type_t<Ty, N> src0,
+                     sycl::INTEL::gpu::vector_type_t<Ty, N> src1,
+                     sycl::INTEL::gpu::vector_type_t<uint16_t, N> pred) {
+  sycl::INTEL::gpu::vector_type_t<Ty, N> retv;
   return retv;
 }
 
 template <typename Ty, int N, typename SurfIndAliasTy>
-SYCL_EXTERNAL sycl::intel::gpu::vector_type_t<Ty, N>
+SYCL_EXTERNAL sycl::INTEL::gpu::vector_type_t<Ty, N>
 __esimd_block_read(SurfIndAliasTy surf_ind, uint32_t offset) {
   throw cl::sycl::feature_not_supported();
-  return sycl::intel::gpu::vector_type_t<Ty, N>();
+  return sycl::INTEL::gpu::vector_type_t<Ty, N>();
 }
 
 template <typename Ty, int N, typename SurfIndAliasTy>
 SYCL_EXTERNAL void
 __esimd_block_write(SurfIndAliasTy surf_ind, uint32_t offset,
-                    sycl::intel::gpu::vector_type_t<Ty, N> vals) {
+                    sycl::INTEL::gpu::vector_type_t<Ty, N> vals) {
 
   throw cl::sycl::feature_not_supported();
 }
diff --git a/sycl/include/CL/sycl/intel/esimd/detail/esimd_region.hpp b/sycl/include/CL/sycl/INTEL/esimd/detail/esimd_region.hpp
similarity index 99%
rename from sycl/include/CL/sycl/intel/esimd/detail/esimd_region.hpp
rename to sycl/include/CL/sycl/INTEL/esimd/detail/esimd_region.hpp
index c1576415a882b..f995eb0b5e621 100644
--- a/sycl/include/CL/sycl/intel/esimd/detail/esimd_region.hpp
+++ b/sycl/include/CL/sycl/INTEL/esimd/detail/esimd_region.hpp
@@ -17,7 +17,7 @@
 
 __SYCL_INLINE_NAMESPACE(cl) {
 namespace sycl {
-namespace intel {
+namespace INTEL {
 namespace gpu {
 
 // The common base type of region types.
@@ -114,6 +114,6 @@ template <typename T, typename U> T getBaseRegion(std::pair<T, U> Reg) {
 }
 
 } // namespace gpu
-} // namespace intel
+} // namespace INTEL
 } // namespace sycl
 } // __SYCL_INLINE_NAMESPACE(cl)
diff --git a/sycl/include/CL/sycl/intel/esimd/detail/esimd_types.hpp b/sycl/include/CL/sycl/INTEL/esimd/detail/esimd_types.hpp
similarity index 98%
rename from sycl/include/CL/sycl/intel/esimd/detail/esimd_types.hpp
rename to sycl/include/CL/sycl/INTEL/esimd/detail/esimd_types.hpp
index 7ff12e9113dda..f760d825d6a9d 100644
--- a/sycl/include/CL/sycl/intel/esimd/detail/esimd_types.hpp
+++ b/sycl/include/CL/sycl/INTEL/esimd/detail/esimd_types.hpp
@@ -10,17 +10,17 @@
 
 #pragma once
 
+#include <CL/sycl/INTEL/esimd/detail/esimd_region.hpp>
+#include <CL/sycl/INTEL/esimd/esimd_enum.hpp>
 #include <CL/sycl/detail/defines.hpp>
 #include <CL/sycl/detail/stl_type_traits.hpp> // to define C++14,17 extensions
 #include <CL/sycl/half_type.hpp>
-#include <CL/sycl/intel/esimd/detail/esimd_region.hpp>
-#include <CL/sycl/intel/esimd/esimd_enum.hpp>
 #include <cstdint>
 #include <type_traits>
 
 __SYCL_INLINE_NAMESPACE(cl) {
 namespace sycl {
-namespace intel {
+namespace INTEL {
 namespace gpu {
 
 namespace csd = cl::sycl::detail;
@@ -256,6 +256,6 @@ inline std::istream &operator>>(std::istream &I, half &rhs) {
 }
 
 } // namespace gpu
-} // namespace intel
+} // namespace INTEL
 } // namespace sycl
 } // __SYCL_INLINE_NAMESPACE(cl)
diff --git a/sycl/include/CL/sycl/intel/esimd/detail/esimd_util.hpp b/sycl/include/CL/sycl/INTEL/esimd/detail/esimd_util.hpp
similarity index 88%
rename from sycl/include/CL/sycl/intel/esimd/detail/esimd_util.hpp
rename to sycl/include/CL/sycl/INTEL/esimd/detail/esimd_util.hpp
index 4bd68905e069b..42ce828da229d 100755
--- a/sycl/include/CL/sycl/intel/esimd/detail/esimd_util.hpp
+++ b/sycl/include/CL/sycl/INTEL/esimd/detail/esimd_util.hpp
@@ -69,7 +69,7 @@ static ESIMD_INLINE constexpr bool isPowerOf2(unsigned int n,
 
 __SYCL_INLINE_NAMESPACE(cl) {
 namespace sycl {
-namespace intel {
+namespace INTEL {
 namespace gpu {
 
 constexpr unsigned int ElemsPerAddrDecoding(unsigned int ElemsPerAddrEncoded) {
@@ -84,11 +84,11 @@ template <typename T> struct is_esimd_vector {
   static const bool value = false;
 };
 template <typename T, int N>
-struct is_esimd_vector<sycl::intel::gpu::simd<T, N>> {
+struct is_esimd_vector<sycl::INTEL::gpu::simd<T, N>> {
   static const bool value = true;
 };
 template <typename T, int N>
-struct is_esimd_vector<sycl::intel::gpu::vector_type<T, N>> {
+struct is_esimd_vector<sycl::INTEL::gpu::vector_type<T, N>> {
   static const bool value = true;
 };
 
@@ -106,12 +106,12 @@ struct is_dword_type
 };
 
 template <typename T, int N>
-struct is_dword_type<sycl::intel::gpu::vector_type<T, N>> {
+struct is_dword_type<sycl::INTEL::gpu::vector_type<T, N>> {
   static const bool value = is_dword_type<T>::value;
 };
 
 template <typename T, int N>
-struct is_dword_type<sycl::intel::gpu::simd<T, N>> {
+struct is_dword_type<sycl::INTEL::gpu::simd<T, N>> {
   static const bool value = is_dword_type<T>::value;
 };
 
@@ -124,11 +124,11 @@ struct is_word_type
                            typename std::remove_const<T>::type>::value> {};
 
 template <typename T, int N>
-struct is_word_type<sycl::intel::gpu::vector_type<T, N>> {
+struct is_word_type<sycl::INTEL::gpu::vector_type<T, N>> {
   static const bool value = is_word_type<T>::value;
 };
 
-template <typename T, int N> struct is_word_type<sycl::intel::gpu::simd<T, N>> {
+template <typename T, int N> struct is_word_type<sycl::INTEL::gpu::simd<T, N>> {
   static const bool value = is_word_type<T>::value;
 };
 
@@ -141,11 +141,11 @@ struct is_byte_type
                            typename std::remove_const<T>::type>::value> {};
 
 template <typename T, int N>
-struct is_byte_type<sycl::intel::gpu::vector_type<T, N>> {
+struct is_byte_type<sycl::INTEL::gpu::vector_type<T, N>> {
   static const bool value = is_byte_type<T>::value;
 };
 
-template <typename T, int N> struct is_byte_type<sycl::intel::gpu::simd<T, N>> {
+template <typename T, int N> struct is_byte_type<sycl::INTEL::gpu::simd<T, N>> {
   static const bool value = is_byte_type<T>::value;
 };
 
@@ -179,33 +179,33 @@ struct is_qword_type
                            typename std::remove_const<T>::type>::value> {};
 
 template <typename T, int N>
-struct is_qword_type<sycl::intel::gpu::vector_type<T, N>> {
+struct is_qword_type<sycl::INTEL::gpu::vector_type<T, N>> {
   static const bool value = is_qword_type<T>::value;
 };
 
 template <typename T, int N>
-struct is_qword_type<sycl::intel::gpu::simd<T, N>> {
+struct is_qword_type<sycl::INTEL::gpu::simd<T, N>> {
   static const bool value = is_qword_type<T>::value;
 };
 
 // Extends to ESIMD vector types.
 template <typename T, int N>
-struct is_fp_or_dword_type<sycl::intel::gpu::vector_type<T, N>> {
+struct is_fp_or_dword_type<sycl::INTEL::gpu::vector_type<T, N>> {
   static const bool value = is_fp_or_dword_type<T>::value;
 };
 
 template <typename T, int N>
-struct is_fp_or_dword_type<sycl::intel::gpu::simd<T, N>> {
+struct is_fp_or_dword_type<sycl::INTEL::gpu::simd<T, N>> {
   static const bool value = is_fp_or_dword_type<T>::value;
 };
 
 /// Convert types into vector types
 template <typename T> struct simd_type {
-  using type = sycl::intel::gpu::simd<T, 1>;
+  using type = sycl::INTEL::gpu::simd<T, 1>;
 };
 template <typename T, int N>
-struct simd_type<sycl::intel::gpu::vector_type<T, N>> {
-  using type = sycl::intel::gpu::simd<T, N>;
+struct simd_type<sycl::INTEL::gpu::vector_type<T, N>> {
+  using type = sycl::INTEL::gpu::simd<T, N>;
 };
 
 template <typename T> struct simd_type<T &> {
@@ -238,6 +238,6 @@ template <> struct word_type<uint> { using type = ushort; };
 
 } // namespace details
 } // namespace gpu
-} // namespace intel
+} // namespace INTEL
 } // namespace sycl
 } // __SYCL_INLINE_NAMESPACE(cl)
diff --git a/sycl/include/CL/sycl/intel/esimd/esimd.hpp b/sycl/include/CL/sycl/INTEL/esimd/esimd.hpp
similarity index 98%
rename from sycl/include/CL/sycl/intel/esimd/esimd.hpp
rename to sycl/include/CL/sycl/INTEL/esimd/esimd.hpp
index 757055dfa00fe..25f8e339fefd6 100644
--- a/sycl/include/CL/sycl/intel/esimd/esimd.hpp
+++ b/sycl/include/CL/sycl/INTEL/esimd/esimd.hpp
@@ -10,12 +10,12 @@
 
 #pragma once
 
-#include <CL/sycl/intel/esimd/detail/esimd_intrin.hpp>
-#include <CL/sycl/intel/esimd/detail/esimd_types.hpp>
+#include <CL/sycl/INTEL/esimd/detail/esimd_intrin.hpp>
+#include <CL/sycl/INTEL/esimd/detail/esimd_types.hpp>
 
 __SYCL_INLINE_NAMESPACE(cl) {
 namespace sycl {
-namespace intel {
+namespace INTEL {
 namespace gpu {
 
 //
@@ -444,14 +444,14 @@ ESIMD_INLINE simd<U, n> convert(simd<T, n> val) {
 }
 
 } // namespace gpu
-} // namespace intel
+} // namespace INTEL
 } // namespace sycl
 } // __SYCL_INLINE_NAMESPACE(cl)
 
 #ifndef __SYCL_DEVICE_ONLY__
 template <typename Ty, int N>
 std::ostream &operator<<(std::ostream &OS,
-                         const sycl::intel::gpu::simd<Ty, N> &V) {
+                         const sycl::INTEL::gpu::simd<Ty, N> &V) {
   OS << "{";
   for (int I = 0; I < N; I++) {
     OS << V[I];
diff --git a/sycl/include/CL/sycl/intel/esimd/esimd_enum.hpp b/sycl/include/CL/sycl/INTEL/esimd/esimd_enum.hpp
similarity index 98%
rename from sycl/include/CL/sycl/intel/esimd/esimd_enum.hpp
rename to sycl/include/CL/sycl/INTEL/esimd/esimd_enum.hpp
index 4b901ea079119..78ceb5c0c4b97 100644
--- a/sycl/include/CL/sycl/intel/esimd/esimd_enum.hpp
+++ b/sycl/include/CL/sycl/INTEL/esimd/esimd_enum.hpp
@@ -15,7 +15,7 @@
 
 __SYCL_INLINE_NAMESPACE(cl) {
 namespace sycl {
-namespace intel {
+namespace INTEL {
 namespace gpu {
 
 using uchar = unsigned char;
@@ -106,6 +106,6 @@ enum class CacheHint : uint8_t {
 
 } // namespace gpu
 
-} // namespace intel
+} // namespace INTEL
 } // namespace sycl
 } // __SYCL_INLINE_NAMESPACE(cl)
diff --git a/sycl/include/CL/sycl/intel/esimd/esimd_math.hpp b/sycl/include/CL/sycl/INTEL/esimd/esimd_math.hpp
similarity index 99%
rename from sycl/include/CL/sycl/intel/esimd/esimd_math.hpp
rename to sycl/include/CL/sycl/INTEL/esimd/esimd_math.hpp
index cd5b962dd60a2..1f241c63745cb 100644
--- a/sycl/include/CL/sycl/intel/esimd/esimd_math.hpp
+++ b/sycl/include/CL/sycl/INTEL/esimd/esimd_math.hpp
@@ -10,16 +10,16 @@
 
 #pragma once
 
-#include <CL/sycl/intel/esimd/detail/esimd_math_intrin.hpp>
-#include <CL/sycl/intel/esimd/detail/esimd_types.hpp>
-#include <CL/sycl/intel/esimd/detail/esimd_util.hpp>
-#include <CL/sycl/intel/esimd/esimd.hpp>
-#include <CL/sycl/intel/esimd/esimd_enum.hpp>
+#include <CL/sycl/INTEL/esimd/detail/esimd_math_intrin.hpp>
+#include <CL/sycl/INTEL/esimd/detail/esimd_types.hpp>
+#include <CL/sycl/INTEL/esimd/detail/esimd_util.hpp>
+#include <CL/sycl/INTEL/esimd/esimd.hpp>
+#include <CL/sycl/INTEL/esimd/esimd_enum.hpp>
 #include <cstdint>
 
 __SYCL_INLINE_NAMESPACE(cl) {
 namespace sycl {
-namespace intel {
+namespace INTEL {
 namespace gpu {
 
 template <typename T0, typename T1, int SZ>
@@ -1945,6 +1945,6 @@ simd<T, N> esimd_dp4(simd<T, N> v1, simd<T, N> v2) {
 }
 
 } // namespace gpu
-} // namespace intel
+} // namespace INTEL
 } // namespace sycl
 } // __SYCL_INLINE_NAMESPACE(cl)
diff --git a/sycl/include/CL/sycl/intel/esimd/esimd_memory.hpp b/sycl/include/CL/sycl/INTEL/esimd/esimd_memory.hpp
similarity index 98%
rename from sycl/include/CL/sycl/intel/esimd/esimd_memory.hpp
rename to sycl/include/CL/sycl/INTEL/esimd/esimd_memory.hpp
index 77035cb16c9c3..8925f858b1fea 100644
--- a/sycl/include/CL/sycl/intel/esimd/esimd_memory.hpp
+++ b/sycl/include/CL/sycl/INTEL/esimd/esimd_memory.hpp
@@ -10,17 +10,17 @@
 
 #pragma once
 
+#include <CL/sycl/INTEL/esimd/detail/esimd_memory_intrin.hpp>
+#include <CL/sycl/INTEL/esimd/detail/esimd_types.hpp>
+#include <CL/sycl/INTEL/esimd/detail/esimd_util.hpp>
+#include <CL/sycl/INTEL/esimd/esimd.hpp>
+#include <CL/sycl/INTEL/esimd/esimd_enum.hpp>
 #include <CL/sycl/half_type.hpp>
-#include <CL/sycl/intel/esimd/detail/esimd_memory_intrin.hpp>
-#include <CL/sycl/intel/esimd/detail/esimd_types.hpp>
-#include <CL/sycl/intel/esimd/detail/esimd_util.hpp>
-#include <CL/sycl/intel/esimd/esimd.hpp>
-#include <CL/sycl/intel/esimd/esimd_enum.hpp>
 #include <cstdint>
 
 __SYCL_INLINE_NAMESPACE(cl) {
 namespace sycl {
-namespace intel {
+namespace INTEL {
 namespace gpu {
 
 template <int ElemsPerAddr,
@@ -69,7 +69,7 @@ constexpr unsigned int ElemsPerAddrEncoding() {
 //
 // TODO @keryell
 // {quote}
-// An approach � la https ://github.com/chriskohlhoff/propria from
+// An approach a la https ://github.com/chriskohlhoff/propria from
 // @chriskohlhoff would be to add a property to the pointer, such as
 //
 //    auto result = flat_load(p, offsets);
@@ -644,6 +644,6 @@ SYCL_EXTERNAL void slm_init(uint32_t size) {}
 
 #endif
 } // namespace gpu
-} // namespace intel
+} // namespace INTEL
 } // namespace sycl
 } // __SYCL_INLINE_NAMESPACE(cl)
diff --git a/sycl/include/CL/sycl/intel/esimd/esimd_view.hpp b/sycl/include/CL/sycl/INTEL/esimd/esimd_view.hpp
similarity index 99%
rename from sycl/include/CL/sycl/intel/esimd/esimd_view.hpp
rename to sycl/include/CL/sycl/INTEL/esimd/esimd_view.hpp
index 57338a0c51e86..aa3e29698cf99 100644
--- a/sycl/include/CL/sycl/intel/esimd/esimd_view.hpp
+++ b/sycl/include/CL/sycl/INTEL/esimd/esimd_view.hpp
@@ -10,11 +10,11 @@
 
 #pragma once
 
-#include <CL/sycl/intel/esimd/detail/esimd_types.hpp>
+#include <CL/sycl/INTEL/esimd/detail/esimd_types.hpp>
 
 __SYCL_INLINE_NAMESPACE(cl) {
 namespace sycl {
-namespace intel {
+namespace INTEL {
 namespace gpu {
 
 //
@@ -380,6 +380,6 @@ template <typename BaseTy, typename RegionTy> class simd_view {
 };
 
 } // namespace gpu
-} // namespace intel
+} // namespace INTEL
 } // namespace sycl
 } // __SYCL_INLINE_NAMESPACE(cl)
diff --git a/sycl/include/CL/sycl/intel/fpga_device_selector.hpp b/sycl/include/CL/sycl/INTEL/fpga_device_selector.hpp
similarity index 89%
rename from sycl/include/CL/sycl/intel/fpga_device_selector.hpp
rename to sycl/include/CL/sycl/INTEL/fpga_device_selector.hpp
index d5f9cab31180c..3218cf9c9e427 100644
--- a/sycl/include/CL/sycl/intel/fpga_device_selector.hpp
+++ b/sycl/include/CL/sycl/INTEL/fpga_device_selector.hpp
@@ -12,7 +12,7 @@
 
 __SYCL_INLINE_NAMESPACE(cl) {
 namespace sycl {
-namespace intel {
+namespace INTEL {
 
 class platform_selector : public device_selector {
 private:
@@ -20,7 +20,7 @@ class platform_selector : public device_selector {
 
 public:
   platform_selector(const std::string &platform_name)
-      : device_platform_name(platform_name){}
+      : device_platform_name(platform_name) {}
 
   int operator()(const device &device) const override {
     const platform &pf = device.get_platform();
@@ -39,14 +39,14 @@ static constexpr auto HARDWARE_PLATFORM_NAME =
 
 class fpga_selector : public platform_selector {
 public:
-  fpga_selector() : platform_selector(HARDWARE_PLATFORM_NAME){}
+  fpga_selector() : platform_selector(HARDWARE_PLATFORM_NAME) {}
 };
 
 class fpga_emulator_selector : public platform_selector {
 public:
-  fpga_emulator_selector() : platform_selector(EMULATION_PLATFORM_NAME){}
+  fpga_emulator_selector() : platform_selector(EMULATION_PLATFORM_NAME) {}
 };
 
-} // namespace intel
+} // namespace INTEL
 } // namespace sycl
 } // __SYCL_INLINE_NAMESPACE(cl)
diff --git a/sycl/include/CL/sycl/intel/fpga_extensions.hpp b/sycl/include/CL/sycl/INTEL/fpga_extensions.hpp
similarity index 70%
rename from sycl/include/CL/sycl/intel/fpga_extensions.hpp
rename to sycl/include/CL/sycl/INTEL/fpga_extensions.hpp
index 7140421fe5189..c2021fcfe7658 100644
--- a/sycl/include/CL/sycl/intel/fpga_extensions.hpp
+++ b/sycl/include/CL/sycl/INTEL/fpga_extensions.hpp
@@ -7,7 +7,7 @@
 //===----------------------------------------------------------------------===//
 
 #pragma once
-#include <CL/sycl/intel/fpga_device_selector.hpp>
-#include <CL/sycl/intel/fpga_lsu.hpp>
-#include <CL/sycl/intel/fpga_reg.hpp>
-#include <CL/sycl/intel/pipes.hpp>
+#include <CL/sycl/INTEL/fpga_device_selector.hpp>
+#include <CL/sycl/INTEL/fpga_lsu.hpp>
+#include <CL/sycl/INTEL/fpga_reg.hpp>
+#include <CL/sycl/INTEL/pipes.hpp>
diff --git a/sycl/include/CL/sycl/intel/fpga_lsu.hpp b/sycl/include/CL/sycl/INTEL/fpga_lsu.hpp
similarity index 99%
rename from sycl/include/CL/sycl/intel/fpga_lsu.hpp
rename to sycl/include/CL/sycl/INTEL/fpga_lsu.hpp
index 5f8d37f802e76..a52723c0c4a2e 100644
--- a/sycl/include/CL/sycl/intel/fpga_lsu.hpp
+++ b/sycl/include/CL/sycl/INTEL/fpga_lsu.hpp
@@ -13,7 +13,7 @@
 
 __SYCL_INLINE_NAMESPACE(cl) {
 namespace sycl {
-namespace intel {
+namespace INTEL {
 constexpr uint8_t BURST_COALESCE = 0x1;
 constexpr uint8_t CACHE = 0x2;
 constexpr uint8_t STATICALLY_COALESCE = 0x4;
@@ -108,6 +108,6 @@ template <class... mem_access_params> class lsu final {
                   "unable to implement a store LSU with a prefetcher.");
   }
 };
-} // namespace intel
+} // namespace INTEL
 } // namespace sycl
 } // __SYCL_INLINE_NAMESPACE(cl)
diff --git a/sycl/include/CL/sycl/intel/fpga_reg.hpp b/sycl/include/CL/sycl/INTEL/fpga_reg.hpp
similarity index 89%
rename from sycl/include/CL/sycl/intel/fpga_reg.hpp
rename to sycl/include/CL/sycl/INTEL/fpga_reg.hpp
index 0078dd66c383c..3a6e59b9ed87c 100644
--- a/sycl/include/CL/sycl/intel/fpga_reg.hpp
+++ b/sycl/include/CL/sycl/INTEL/fpga_reg.hpp
@@ -12,7 +12,7 @@
 
 __SYCL_INLINE_NAMESPACE(cl) {
 namespace sycl {
-namespace intel {
+namespace INTEL {
 
 template <typename T> T fpga_reg(const T &t) {
 #if __has_builtin(__builtin_intel_fpga_reg)
@@ -22,7 +22,7 @@ template <typename T> T fpga_reg(const T &t) {
 #endif
 }
 
-} // namespace intel
+} // namespace INTEL
 } // namespace sycl
 } // __SYCL_INLINE_NAMESPACE(cl)
 
@@ -30,6 +30,6 @@ template <typename T> T fpga_reg(const T &t) {
 // Currently clang does not support nested namespace for attributes
 namespace intelfpga {
 template <typename T> T fpga_reg(const T &t) {
-  return cl::sycl::intel::fpga_reg(t);
-}
+  return cl::sycl::INTEL::fpga_reg(t);
 }
+} // namespace intelfpga
diff --git a/sycl/include/CL/sycl/intel/fpga_utils.hpp b/sycl/include/CL/sycl/INTEL/fpga_utils.hpp
similarity index 96%
rename from sycl/include/CL/sycl/intel/fpga_utils.hpp
rename to sycl/include/CL/sycl/INTEL/fpga_utils.hpp
index be9bf1a6fc5af..7fdc64e94a246 100644
--- a/sycl/include/CL/sycl/intel/fpga_utils.hpp
+++ b/sycl/include/CL/sycl/INTEL/fpga_utils.hpp
@@ -13,7 +13,7 @@
 
 __SYCL_INLINE_NAMESPACE(cl) {
 namespace sycl {
-namespace intel {
+namespace INTEL {
 
 template <template <int32_t> class Type, class T>
 struct MatchType : std::is_same<Type<T::value>, T> {};
@@ -28,6 +28,6 @@ struct GetValue<Type, T1, T...> {
       std::conditional<MatchType<Type, T1>::value, T1,
                        GetValue<Type, T...>>::type::value;
 };
-} // namespace intel
+} // namespace INTEL
 } // namespace sycl
 } // __SYCL_INLINE_NAMESPACE(cl)
diff --git a/sycl/include/CL/sycl/intel/pipes.hpp b/sycl/include/CL/sycl/INTEL/pipes.hpp
similarity index 95%
rename from sycl/include/CL/sycl/intel/pipes.hpp
rename to sycl/include/CL/sycl/INTEL/pipes.hpp
index 8396bc1e215fc..9d74c98982d65 100644
--- a/sycl/include/CL/sycl/intel/pipes.hpp
+++ b/sycl/include/CL/sycl/INTEL/pipes.hpp
@@ -14,7 +14,7 @@
 
 __SYCL_INLINE_NAMESPACE(cl) {
 namespace sycl {
-namespace intel {
+namespace INTEL {
 
 template <class name, class dataT, int32_t min_capacity = 0> class pipe {
 public:
@@ -24,7 +24,7 @@ template <class name, class dataT, int32_t min_capacity = 0> class pipe {
   static dataT read(bool &Success) {
 #ifdef __SYCL_DEVICE_ONLY__
     RPipeTy<dataT> RPipe =
-      __spirv_CreatePipeFromPipeStorage_read<dataT>(&m_Storage);
+        __spirv_CreatePipeFromPipeStorage_read<dataT>(&m_Storage);
     dataT TempData;
     Success = !static_cast<bool>(
         __spirv_ReadPipe(RPipe, &TempData, m_Size, m_Alignment));
@@ -40,7 +40,7 @@ template <class name, class dataT, int32_t min_capacity = 0> class pipe {
   static void write(const dataT &Data, bool &Success) {
 #ifdef __SYCL_DEVICE_ONLY__
     WPipeTy<dataT> WPipe =
-      __spirv_CreatePipeFromPipeStorage_write<dataT>(&m_Storage);
+        __spirv_CreatePipeFromPipeStorage_write<dataT>(&m_Storage);
     Success = !static_cast<bool>(
         __spirv_WritePipe(WPipe, &Data, m_Size, m_Alignment));
 #else
@@ -56,7 +56,7 @@ template <class name, class dataT, int32_t min_capacity = 0> class pipe {
   static dataT read() {
 #ifdef __SYCL_DEVICE_ONLY__
     RPipeTy<dataT> RPipe =
-      __spirv_CreatePipeFromPipeStorage_read<dataT>(&m_Storage);
+        __spirv_CreatePipeFromPipeStorage_read<dataT>(&m_Storage);
     dataT TempData;
     __spirv_ReadPipeBlockingINTEL(RPipe, &TempData, m_Size, m_Alignment);
     return TempData;
@@ -70,7 +70,7 @@ template <class name, class dataT, int32_t min_capacity = 0> class pipe {
   static void write(const dataT &Data) {
 #ifdef __SYCL_DEVICE_ONLY__
     WPipeTy<dataT> WPipe =
-      __spirv_CreatePipeFromPipeStorage_write<dataT>(&m_Storage);
+        __spirv_CreatePipeFromPipeStorage_write<dataT>(&m_Storage);
     __spirv_WritePipeBlockingINTEL(WPipe, &Data, m_Size, m_Alignment);
 #else
     (void)Data;
@@ -198,6 +198,6 @@ class kernel_writeable_io_pipe {
 #endif // __SYCL_DEVICE_ONLY__
 };
 
-} // namespace intel
+} // namespace INTEL
 } // namespace sycl
 } // __SYCL_INLINE_NAMESPACE(cl)
diff --git a/sycl/include/CL/sycl/accessor.hpp b/sycl/include/CL/sycl/accessor.hpp
index 8631cee6ab640..dd4f7fc09be01 100755
--- a/sycl/include/CL/sycl/accessor.hpp
+++ b/sycl/include/CL/sycl/accessor.hpp
@@ -199,12 +199,12 @@
 
 __SYCL_INLINE_NAMESPACE(cl) {
 namespace sycl {
-namespace intel {
+namespace INTEL {
 namespace gpu {
 // Forward declare a "back-door" access class to support ESIMD.
 class AccessorPrivateProxy;
 } // namespace gpu
-} // namespace intel
+} // namespace INTEL
 } // namespace sycl
 } // __SYCL_INLINE_NAMESPACE(cl)
 
@@ -434,7 +434,7 @@ class image_accessor
 #endif
 
 private:
-  friend class sycl::intel::gpu::AccessorPrivateProxy;
+  friend class sycl::INTEL::gpu::AccessorPrivateProxy;
 
 #if defined(__SYCL_DEVICE_ONLY__) && defined(__SYCL_EXPLICIT_SIMD__)
   const OCLImageTy getNativeImageObj() const { return MImageObj; }
@@ -885,7 +885,7 @@ class accessor :
 #endif // __SYCL_DEVICE_ONLY__
 
 private:
-  friend class sycl::intel::gpu::AccessorPrivateProxy;
+  friend class sycl::INTEL::gpu::AccessorPrivateProxy;
 
 public:
   using value_type = DataT;
diff --git a/sycl/include/CL/sycl/detail/accessor_impl.hpp b/sycl/include/CL/sycl/detail/accessor_impl.hpp
index 76676014975c2..277b740e6a229 100644
--- a/sycl/include/CL/sycl/detail/accessor_impl.hpp
+++ b/sycl/include/CL/sycl/detail/accessor_impl.hpp
@@ -17,12 +17,12 @@
 
 __SYCL_INLINE_NAMESPACE(cl) {
 namespace sycl {
-namespace intel {
+namespace INTEL {
 namespace gpu {
 // Forward declare a "back-door" access class to support ESIMD.
 class AccessorPrivateProxy;
 } // namespace gpu
-} // namespace intel
+} // namespace INTEL
 } // namespace sycl
 } // __SYCL_INLINE_NAMESPACE(cl)
 
@@ -170,7 +170,7 @@ class AccessorBaseHost {
   AccessorImplPtr impl;
 
 private:
-  friend class sycl::intel::gpu::AccessorPrivateProxy;
+  friend class sycl::INTEL::gpu::AccessorPrivateProxy;
 };
 
 class __SYCL_EXPORT LocalAccessorImplHost {
diff --git a/sycl/include/CL/sycl/pipes.hpp b/sycl/include/CL/sycl/pipes.hpp
index e02fa1155592f..3701fd4352320 100644
--- a/sycl/include/CL/sycl/pipes.hpp
+++ b/sycl/include/CL/sycl/pipes.hpp
@@ -8,11 +8,11 @@
 
 #pragma once
 
-#include <CL/sycl/intel/pipes.hpp>
+#include <CL/sycl/INTEL/pipes.hpp>
 
 __SYCL_INLINE_NAMESPACE(cl) {
 namespace sycl {
 template <class name, class dataT, int32_t min_capacity = 0>
-using pipe = intel::pipe<name, dataT, min_capacity>;
+using pipe = INTEL::pipe<name, dataT, min_capacity>;
 } // namespace sycl
 } // __SYCL_INLINE_NAMESPACE(cl)
diff --git a/sycl/test/basic_tests/esimd/block_load_store.cpp b/sycl/test/basic_tests/esimd/block_load_store.cpp
index 268df2c7991c6..974e633f7d096 100644
--- a/sycl/test/basic_tests/esimd/block_load_store.cpp
+++ b/sycl/test/basic_tests/esimd/block_load_store.cpp
@@ -2,11 +2,11 @@
 // expected-no-diagnostics
 
 #include <CL/sycl.hpp>
-#include <CL/sycl/intel/esimd.hpp>
+#include <CL/sycl/INTEL/esimd.hpp>
 #include <limits>
 #include <utility>
 
-using namespace sycl::intel::gpu;
+using namespace sycl::INTEL::gpu;
 using namespace cl::sycl;
 
 void kernel(accessor<int, 1, access::mode::read_write, access::target::global_buffer> &buf) __attribute__((sycl_device)) {
diff --git a/sycl/test/basic_tests/esimd/esimd_math.cpp b/sycl/test/basic_tests/esimd/esimd_math.cpp
index bada49639b366..34385ff058d98 100644
--- a/sycl/test/basic_tests/esimd/esimd_math.cpp
+++ b/sycl/test/basic_tests/esimd/esimd_math.cpp
@@ -1,11 +1,11 @@
 // RUN: %clangxx -fsycl -fsycl-explicit-simd -fsycl-device-only -fsyntax-only -Xclang -verify %s
 // expected-no-diagnostics
 
-#include <CL/sycl/intel/esimd.hpp>
+#include <CL/sycl/INTEL/esimd.hpp>
 #include <limits>
 #include <utility>
 
-using namespace sycl::intel::gpu;
+using namespace sycl::INTEL::gpu;
 
 bool test_esimd_mask() __attribute__((sycl_device)) {
   simd<ushort, 16> a(0);
diff --git a/sycl/test/basic_tests/esimd/flat_atomic.cpp b/sycl/test/basic_tests/esimd/flat_atomic.cpp
index 03bf1742015ed..9b8fa775c21b7 100644
--- a/sycl/test/basic_tests/esimd/flat_atomic.cpp
+++ b/sycl/test/basic_tests/esimd/flat_atomic.cpp
@@ -2,11 +2,11 @@
 // expected-no-diagnostics
 
 #include <CL/sycl.hpp>
-#include <CL/sycl/intel/esimd.hpp>
+#include <CL/sycl/INTEL/esimd.hpp>
 #include <limits>
 #include <utility>
 
-using namespace sycl::intel::gpu;
+using namespace sycl::INTEL::gpu;
 using namespace cl::sycl;
 
 void kernel0(accessor<uint32_t, 1, access::mode::read_write, access::target::global_buffer> &buf) __attribute__((sycl_device)) {
diff --git a/sycl/test/basic_tests/esimd/gather4_scatter4.cpp b/sycl/test/basic_tests/esimd/gather4_scatter4.cpp
index 0e912f393afd3..b8b92305b14f3 100644
--- a/sycl/test/basic_tests/esimd/gather4_scatter4.cpp
+++ b/sycl/test/basic_tests/esimd/gather4_scatter4.cpp
@@ -2,11 +2,11 @@
 // expected-no-diagnostics
 
 #include <CL/sycl.hpp>
-#include <CL/sycl/intel/esimd.hpp>
+#include <CL/sycl/INTEL/esimd.hpp>
 #include <limits>
 #include <utility>
 
-using namespace sycl::intel::gpu;
+using namespace sycl::INTEL::gpu;
 using namespace cl::sycl;
 
 void kernel(accessor<int, 1, access::mode::read_write,
diff --git a/sycl/test/basic_tests/esimd/gather_scatter.cpp b/sycl/test/basic_tests/esimd/gather_scatter.cpp
index d0c83ef7606e9..80c0400a94d41 100644
--- a/sycl/test/basic_tests/esimd/gather_scatter.cpp
+++ b/sycl/test/basic_tests/esimd/gather_scatter.cpp
@@ -2,11 +2,11 @@
 // expected-no-diagnostics
 
 #include <CL/sycl.hpp>
-#include <CL/sycl/intel/esimd.hpp>
+#include <CL/sycl/INTEL/esimd.hpp>
 #include <limits>
 #include <utility>
 
-using namespace sycl::intel::gpu;
+using namespace sycl::INTEL::gpu;
 using namespace cl::sycl;
 
 void kernel(accessor<int, 1, access::mode::read_write, access::target::global_buffer> &buf) __attribute__((sycl_device)) {
diff --git a/sycl/test/basic_tests/esimd/global_var.cpp b/sycl/test/basic_tests/esimd/global_var.cpp
index e2b52fc51241a..e4ea7c150260b 100644
--- a/sycl/test/basic_tests/esimd/global_var.cpp
+++ b/sycl/test/basic_tests/esimd/global_var.cpp
@@ -1,7 +1,7 @@
 // RUN: %clangxx -fsycl -fsycl-explicit-simd -fsycl-device-only -fsyntax-only -Xclang -verify %s
 // expected-no-diagnostics
 
-#include <CL/sycl/intel/esimd.hpp>
+#include <CL/sycl/INTEL/esimd.hpp>
 
 // This test checks that DPC++ compiler in ESIMD mode understands
 // the ESIMD_PRIVATE and ESIMD_REGISTER macros
diff --git a/sycl/test/basic_tests/esimd/simd.cpp b/sycl/test/basic_tests/esimd/simd.cpp
index 5eb82677e0691..9ce57014f83f5 100644
--- a/sycl/test/basic_tests/esimd/simd.cpp
+++ b/sycl/test/basic_tests/esimd/simd.cpp
@@ -1,11 +1,11 @@
 // RUN: %clangxx -fsycl -fsycl-explicit-simd -fsycl-device-only -fsyntax-only -Xclang -verify %s
 // expected-no-diagnostics
 
-#include <CL/sycl/intel/esimd.hpp>
+#include <CL/sycl/INTEL/esimd.hpp>
 #include <limits>
 #include <utility>
 
-using namespace sycl::intel::gpu;
+using namespace sycl::INTEL::gpu;
 
 bool test_simd_ctors() __attribute__((sycl_device)) {
   simd<int, 16> v0 = 1;
diff --git a/sycl/test/basic_tests/esimd/simd_merge.cpp b/sycl/test/basic_tests/esimd/simd_merge.cpp
index 20c357188be79..394922a1e3773 100644
--- a/sycl/test/basic_tests/esimd/simd_merge.cpp
+++ b/sycl/test/basic_tests/esimd/simd_merge.cpp
@@ -1,11 +1,11 @@
 // RUN: %clangxx -fsycl -fsycl-explicit-simd -fsycl-device-only -fsyntax-only -Xclang -verify %s
 // expected-no-diagnostics
 
-#include <CL/sycl/intel/esimd.hpp>
+#include <CL/sycl/INTEL/esimd.hpp>
 #include <limits>
 #include <utility>
 
-using namespace sycl::intel::gpu;
+using namespace sycl::INTEL::gpu;
 
 bool test_simd_merge1() __attribute__((sycl_device)) {
   simd<int, 16> v0 = 1;
diff --git a/sycl/test/basic_tests/esimd/simd_view.cpp b/sycl/test/basic_tests/esimd/simd_view.cpp
index 0910dace1c98a..81375eb1ff01a 100644
--- a/sycl/test/basic_tests/esimd/simd_view.cpp
+++ b/sycl/test/basic_tests/esimd/simd_view.cpp
@@ -1,11 +1,11 @@
 // RUN: %clangxx -fsycl -fsycl-explicit-simd -fsycl-device-only -fsyntax-only -Xclang -verify %s
 // expected-no-diagnostics
 
-#include <CL/sycl/intel/esimd.hpp>
+#include <CL/sycl/INTEL/esimd.hpp>
 #include <limits>
 #include <utility>
 
-using namespace sycl::intel::gpu;
+using namespace sycl::INTEL::gpu;
 
 bool test_simd_view_ctors() __attribute__((sycl_device)) {
   simd<int, 16> v0(0, 1);
diff --git a/sycl/test/basic_tests/esimd/slm_atomic.cpp b/sycl/test/basic_tests/esimd/slm_atomic.cpp
index b7f094075e147..c0dda1dade4fd 100644
--- a/sycl/test/basic_tests/esimd/slm_atomic.cpp
+++ b/sycl/test/basic_tests/esimd/slm_atomic.cpp
@@ -2,11 +2,11 @@
 // expected-no-diagnostics
 
 #include <CL/sycl.hpp>
-#include <CL/sycl/intel/esimd.hpp>
+#include <CL/sycl/INTEL/esimd.hpp>
 #include <limits>
 #include <utility>
 
-using namespace sycl::intel::gpu;
+using namespace sycl::INTEL::gpu;
 using namespace cl::sycl;
 
 void kernel0() __attribute__((sycl_device)) {
diff --git a/sycl/test/basic_tests/esimd/slm_block.cpp b/sycl/test/basic_tests/esimd/slm_block.cpp
index a49083f5c6524..d8d2937a9f67a 100644
--- a/sycl/test/basic_tests/esimd/slm_block.cpp
+++ b/sycl/test/basic_tests/esimd/slm_block.cpp
@@ -2,11 +2,11 @@
 // expected-no-diagnostics
 
 #include <CL/sycl.hpp>
-#include <CL/sycl/intel/esimd.hpp>
+#include <CL/sycl/INTEL/esimd.hpp>
 #include <limits>
 #include <utility>
 
-using namespace sycl::intel::gpu;
+using namespace sycl::INTEL::gpu;
 using namespace cl::sycl;
 
 void kernel() __attribute__((sycl_device)) {
diff --git a/sycl/test/basic_tests/esimd/slm_load.cpp b/sycl/test/basic_tests/esimd/slm_load.cpp
index a84dce7b25f7c..cf890cfe9184e 100644
--- a/sycl/test/basic_tests/esimd/slm_load.cpp
+++ b/sycl/test/basic_tests/esimd/slm_load.cpp
@@ -2,11 +2,11 @@
 // expected-no-diagnostics
 
 #include <CL/sycl.hpp>
-#include <CL/sycl/intel/esimd.hpp>
+#include <CL/sycl/INTEL/esimd.hpp>
 #include <limits>
 #include <utility>
 
-using namespace sycl::intel::gpu;
+using namespace sycl::INTEL::gpu;
 using namespace cl::sycl;
 
 void kernel() __attribute__((sycl_device)) {
diff --git a/sycl/test/basic_tests/esimd/slm_load4.cpp b/sycl/test/basic_tests/esimd/slm_load4.cpp
index f1f483e72c214..a544a5c781f61 100644
--- a/sycl/test/basic_tests/esimd/slm_load4.cpp
+++ b/sycl/test/basic_tests/esimd/slm_load4.cpp
@@ -2,11 +2,11 @@
 // expected-no-diagnostics
 
 #include <CL/sycl.hpp>
-#include <CL/sycl/intel/esimd.hpp>
+#include <CL/sycl/INTEL/esimd.hpp>
 #include <limits>
 #include <utility>
 
-using namespace sycl::intel::gpu;
+using namespace sycl::INTEL::gpu;
 using namespace cl::sycl;
 
 void kernel() __attribute__((sycl_device)) {
diff --git a/sycl/test/basic_tests/esimd/vadd.cpp b/sycl/test/basic_tests/esimd/vadd.cpp
index 481c22a2718d9..8de695c445254 100644
--- a/sycl/test/basic_tests/esimd/vadd.cpp
+++ b/sycl/test/basic_tests/esimd/vadd.cpp
@@ -3,7 +3,7 @@
 // RUN: env SYCL_DEVICE_TYPE=HOST %t.out
 
 #include <CL/sycl.hpp>
-#include <CL/sycl/intel/esimd.hpp>
+#include <CL/sycl/INTEL/esimd.hpp>
 #include <iostream>
 
 using namespace cl::sycl;
@@ -74,7 +74,7 @@ int main(void) {
 
       cgh.parallel_for<class Test>(
           Range, [=](nd_item<1> ndi) SYCL_ESIMD_KERNEL {
-            using namespace sycl::intel::gpu;
+            using namespace sycl::INTEL::gpu;
             auto pA = accA.get_pointer().get();
             auto pB = accB.get_pointer().get();
             auto pC = accC.get_pointer().get();
diff --git a/sycl/test/enqueue_barrier/enqueue_barrier.cpp b/sycl/test/enqueue_barrier/enqueue_barrier.cpp
index b84660d58b467..a417f230f601c 100644
--- a/sycl/test/enqueue_barrier/enqueue_barrier.cpp
+++ b/sycl/test/enqueue_barrier/enqueue_barrier.cpp
@@ -6,7 +6,7 @@
 // UNSUPPORTED: cuda
 
 #include <CL/sycl.hpp>
-#include <CL/sycl/intel/fpga_device_selector.hpp>
+#include <CL/sycl/INTEL/fpga_device_selector.hpp>
 
 int main() {
   sycl::context Context;
diff --git a/sycl/test/esimd/glob.cpp b/sycl/test/esimd/glob.cpp
index ae752ad5801ea..841aa6a3eba87 100644
--- a/sycl/test/esimd/glob.cpp
+++ b/sycl/test/esimd/glob.cpp
@@ -6,11 +6,11 @@
 // (including translation of the register attribute)
 
 #include <CL/sycl.hpp>
-#include <CL/sycl/intel/esimd.hpp>
+#include <CL/sycl/INTEL/esimd.hpp>
 #include <iostream>
 
 using namespace cl::sycl;
-using namespace sycl::intel::gpu;
+using namespace sycl::INTEL::gpu;
 
 constexpr unsigned VL = 16;
 
diff --git a/sycl/test/esimd/hw_compile.cpp b/sycl/test/esimd/hw_compile.cpp
index 96ffe30fda89c..c10fc33e277d1 100644
--- a/sycl/test/esimd/hw_compile.cpp
+++ b/sycl/test/esimd/hw_compile.cpp
@@ -2,7 +2,7 @@
 // RUN: %clangxx -fsycl -fsycl-explicit-simd -fsycl-device-only -c %s -o %t.bc
 
 #include <CL/sycl.hpp>
-#include <CL/sycl/intel/esimd.hpp>
+#include <CL/sycl/INTEL/esimd.hpp>
 #include <iostream>
 
 int main(void) {
diff --git a/sycl/test/esimd/intrins_trans.cpp b/sycl/test/esimd/intrins_trans.cpp
index 8bdd4981b78e9..5497da31ddf86 100644
--- a/sycl/test/esimd/intrins_trans.cpp
+++ b/sycl/test/esimd/intrins_trans.cpp
@@ -5,10 +5,10 @@
 // NOTE: must be run in -O0, as optimizer optimizes away some of the code
 
 #include <CL/sycl.hpp>
+#include <CL/sycl/INTEL/esimd.hpp>
 #include <CL/sycl/detail/image_ocl_types.hpp>
-#include <CL/sycl/intel/esimd.hpp>
 
-using namespace sycl::intel::gpu;
+using namespace sycl::INTEL::gpu;
 
 ESIMD_PRIVATE vector_type_t<int, 32> vc;
 ESIMD_PRIVATE ESIMD_REGISTER(192) simd<int, 16> vg;
diff --git a/sycl/test/esimd/on-device/BitonicSortK.cpp b/sycl/test/esimd/on-device/BitonicSortK.cpp
index a08b1c9b97be0..d5929fae9e12a 100755
--- a/sycl/test/esimd/on-device/BitonicSortK.cpp
+++ b/sycl/test/esimd/on-device/BitonicSortK.cpp
@@ -14,12 +14,12 @@
 #include "esimd_test_utils.hpp"
 
 #include <CL/sycl.hpp>
-#include <CL/sycl/intel/esimd.hpp>
+#include <CL/sycl/INTEL/esimd.hpp>
 #include <algorithm>
 #include <iostream>
 
 using namespace cl::sycl;
-using namespace sycl::intel::gpu;
+using namespace sycl::INTEL::gpu;
 using namespace std;
 
 #define LOG2_ELEMENTS 16 // 24
@@ -611,7 +611,7 @@ int BitonicSort::Solve(uint32_t *pInputs, uint32_t *pOutputs, uint32_t size) {
       auto acco = bufo.get_access<access::mode::write>(cgh);
       cgh.parallel_for<class Sort256>(SortGlobalRange * SortLocalRange,
                                       [=](id<1> i) SYCL_ESIMD_KERNEL {
-                                        using namespace sycl::intel::gpu;
+                                        using namespace sycl::INTEL::gpu;
                                         cmk_bitonic_sort_256(acci, acco, i);
                                       });
     });
@@ -647,7 +647,7 @@ int BitonicSort::Solve(uint32_t *pInputs, uint32_t *pOutputs, uint32_t size) {
         auto acc = buf.get_access<access::mode::read_write>(cgh);
         cgh.parallel_for<class Merge>(MergeGlobalRange * MergeLocalRange,
                                       [=](id<1> tid) SYCL_ESIMD_KERNEL {
-                                        using namespace sycl::intel::gpu;
+                                        using namespace sycl::INTEL::gpu;
                                         cmk_bitonic_merge(acc, j, i, tid);
                                       });
       });
diff --git a/sycl/test/esimd/on-device/BitonicSortKv2.cpp b/sycl/test/esimd/on-device/BitonicSortKv2.cpp
index 59b897b829524..5f08cec74bda5 100755
--- a/sycl/test/esimd/on-device/BitonicSortKv2.cpp
+++ b/sycl/test/esimd/on-device/BitonicSortKv2.cpp
@@ -15,12 +15,12 @@
 #include "esimd_test_utils.hpp"
 
 #include <CL/sycl.hpp>
-#include <CL/sycl/intel/esimd.hpp>
+#include <CL/sycl/INTEL/esimd.hpp>
 #include <algorithm>
 #include <iostream>
 
 using namespace cl::sycl;
-using namespace sycl::intel::gpu;
+using namespace sycl::INTEL::gpu;
 using namespace std;
 
 #define LOG2_ELEMENTS 16 // 24
@@ -527,7 +527,7 @@ int BitonicSort::Solve(uint32_t *pInputs, uint32_t *pOutputs, uint32_t size) {
   auto e = pQueue_->submit([&](handler &cgh) {
     cgh.parallel_for<class Sort256>(
         SortGlobalRange * SortLocalRange, [=](id<1> i) SYCL_ESIMD_KERNEL {
-          using namespace sycl::intel::gpu;
+          using namespace sycl::INTEL::gpu;
           cmk_bitonic_sort_256(pInputs, pOutputs, i);
         });
   });
@@ -560,7 +560,7 @@ int BitonicSort::Solve(uint32_t *pInputs, uint32_t *pOutputs, uint32_t size) {
       mergeEvent[k] = pQueue_->submit([&](handler &cgh) {
         cgh.parallel_for<class Merge>(MergeGlobalRange * MergeLocalRange,
                                       [=](id<1> tid) SYCL_ESIMD_KERNEL {
-                                        using namespace sycl::intel::gpu;
+                                        using namespace sycl::INTEL::gpu;
                                         cmk_bitonic_merge(pOutputs, j, i, tid);
                                       });
       });
diff --git a/sycl/test/esimd/on-device/accessor.cpp b/sycl/test/esimd/on-device/accessor.cpp
index e1ba618d92951..e0cbbe7dcc6c5 100644
--- a/sycl/test/esimd/on-device/accessor.cpp
+++ b/sycl/test/esimd/on-device/accessor.cpp
@@ -16,7 +16,7 @@
 #include "esimd_test_utils.hpp"
 
 #include <CL/sycl.hpp>
-#include <CL/sycl/intel/esimd.hpp>
+#include <CL/sycl/INTEL/esimd.hpp>
 
 #include <iostream>
 
@@ -51,7 +51,7 @@ int main() {
 
       cgh.parallel_for<class Test>(
           range<1>(1), [=](sycl::id<1> i) SYCL_ESIMD_KERNEL {
-            using namespace sycl::intel::gpu;
+            using namespace sycl::INTEL::gpu;
             unsigned int offset = 0;
             for (int k = 0; k < VL / 16; k++) {
               simd<Ty, 16> var = block_load<Ty, 16>(acc0, offset);
diff --git a/sycl/test/esimd/on-device/histogram.cpp b/sycl/test/esimd/on-device/histogram.cpp
index 880754cf61ac1..aa044deb010ec 100644
--- a/sycl/test/esimd/on-device/histogram.cpp
+++ b/sycl/test/esimd/on-device/histogram.cpp
@@ -15,7 +15,7 @@
 #include "esimd_test_utils.hpp"
 
 #include <CL/sycl.hpp>
-#include <CL/sycl/intel/esimd.hpp>
+#include <CL/sycl/INTEL/esimd.hpp>
 #include <array>
 #include <iostream>
 
@@ -149,7 +149,7 @@ int main(int argc, char *argv[]) {
 
       cgh.parallel_for<class Hist>(
           Range, [=](nd_item<1> ndi) SYCL_ESIMD_KERNEL {
-            using namespace sycl::intel::gpu;
+            using namespace sycl::INTEL::gpu;
 
             // Get thread origin offsets
             uint tid = ndi.get_group(0);
diff --git a/sycl/test/esimd/on-device/histogram_2d.cpp b/sycl/test/esimd/on-device/histogram_2d.cpp
index 115aa6b4f8851..826e0d209edc4 100644
--- a/sycl/test/esimd/on-device/histogram_2d.cpp
+++ b/sycl/test/esimd/on-device/histogram_2d.cpp
@@ -15,7 +15,7 @@
 #include "esimd_test_utils.hpp"
 
 #include <CL/sycl.hpp>
-#include <CL/sycl/intel/esimd.hpp>
+#include <CL/sycl/INTEL/esimd.hpp>
 #include <array>
 #include <iostream>
 
@@ -149,7 +149,7 @@ int main(int argc, char *argv[]) {
 
       cgh.parallel_for<class Hist>(
           Range, [=](nd_item<2> ndi) SYCL_ESIMD_KERNEL {
-            using namespace sycl::intel::gpu;
+            using namespace sycl::INTEL::gpu;
 
             // Get thread origin offsets
             uint h_pos = ndi.get_group(0) * BLOCK_WIDTH;
diff --git a/sycl/test/esimd/on-device/kmeans/kmeans.cpp b/sycl/test/esimd/on-device/kmeans/kmeans.cpp
index 917e3bfd4495d..f6b0be0a4f994 100644
--- a/sycl/test/esimd/on-device/kmeans/kmeans.cpp
+++ b/sycl/test/esimd/on-device/kmeans/kmeans.cpp
@@ -18,14 +18,14 @@
 #include "point.h"
 
 #include <CL/sycl.hpp>
-#include <CL/sycl/intel/esimd.hpp>
+#include <CL/sycl/INTEL/esimd.hpp>
 #include <fstream>
 #include <iostream>
 #include <string.h>
 #include <vector>
 
 using namespace cl::sycl;
-using namespace sycl::intel::gpu;
+using namespace sycl::INTEL::gpu;
 using namespace std;
 
 // Each HW thread process POINTS_PER_THREAD points. If the total number of
@@ -639,7 +639,7 @@ int main(int argc, char *argv[]) {
     auto e = q.submit([&](cl::sycl::handler &cgh) {
       cgh.parallel_for<class kMeans>(
           GlobalRange * LocalRange, [=](id<1> i) SYCL_ESIMD_KERNEL {
-            using namespace sycl::intel::gpu;
+            using namespace sycl::INTEL::gpu;
             cmk_kmeans((uint *)points, (uint *)centroids, (uint *)accum,
                        NUM_POINTS, finalIter, i, dbgBuf);
           });
@@ -658,7 +658,7 @@ int main(int argc, char *argv[]) {
     auto e1 = q.submit([&](cl::sycl::handler &cgh) {
       cgh.parallel_for<class kAccumRed>(GlobalRange * LocalRange,
                                         [=](id<1> i) SYCL_ESIMD_KERNEL {
-                                          using namespace sycl::intel::gpu;
+                                          using namespace sycl::INTEL::gpu;
                                           cmk_accum_reduction((uint *)accum, i);
                                         });
     });
@@ -670,7 +670,7 @@ int main(int argc, char *argv[]) {
     auto e2 = q.submit([&](cl::sycl::handler &cgh) {
       cgh.parallel_for<class kCompCentroidPos>(
           GlobalRange1 * LocalRange1, [=](id<1> i) SYCL_ESIMD_KERNEL {
-            using namespace sycl::intel::gpu;
+            using namespace sycl::INTEL::gpu;
             cmk_compute_centroid_position((uint *)centroids, (uint *)accum, i,
                                           dbgBuf);
           });
diff --git a/sycl/test/esimd/on-device/linear/linear.cpp b/sycl/test/esimd/on-device/linear/linear.cpp
index be9ebf58b631a..8d67a6d38459a 100644
--- a/sycl/test/esimd/on-device/linear/linear.cpp
+++ b/sycl/test/esimd/on-device/linear/linear.cpp
@@ -16,7 +16,7 @@
 #include "esimd_test_utils.hpp"
 
 #include <CL/sycl.hpp>
-#include <CL/sycl/intel/esimd.hpp>
+#include <CL/sycl/INTEL/esimd.hpp>
 #include <array>
 #include <iostream>
 
@@ -88,7 +88,7 @@ int main(int argc, char *argv[]) {
 
       cgh.parallel_for<class Test>(
           GlobalRange * LocalRange, [=](item<2> it) SYCL_ESIMD_KERNEL {
-            using namespace sycl::intel::gpu;
+            using namespace sycl::INTEL::gpu;
 
             simd<unsigned char, 8 * 32> vin;
             auto in = vin.format<unsigned char, 8, 32>();
diff --git a/sycl/test/esimd/on-device/mandelbrot/mandelbrot.cpp b/sycl/test/esimd/on-device/mandelbrot/mandelbrot.cpp
index 53078457bf3e5..4549150b5c672 100755
--- a/sycl/test/esimd/on-device/mandelbrot/mandelbrot.cpp
+++ b/sycl/test/esimd/on-device/mandelbrot/mandelbrot.cpp
@@ -13,13 +13,13 @@
 
 #include "esimd_test_utils.hpp"
 #include <CL/sycl.hpp>
-#include <CL/sycl/intel/esimd.hpp>
+#include <CL/sycl/INTEL/esimd.hpp>
 #include <array>
 #include <iostream>
 #include <memory>
 
 using namespace cl::sycl;
-using namespace sycl::intel::gpu;
+using namespace sycl::INTEL::gpu;
 
 #ifdef _SIM_MODE_
 #define CRUNCH 32
diff --git a/sycl/test/esimd/on-device/matrix_transpose.cpp b/sycl/test/esimd/on-device/matrix_transpose.cpp
index 5b40b5af4fc60..27757414ac77a 100755
--- a/sycl/test/esimd/on-device/matrix_transpose.cpp
+++ b/sycl/test/esimd/on-device/matrix_transpose.cpp
@@ -14,7 +14,7 @@
 #include "esimd_test_utils.hpp"
 
 #include <CL/sycl.hpp>
-#include <CL/sycl/intel/esimd.hpp>
+#include <CL/sycl/INTEL/esimd.hpp>
 #include <iostream>
 
 #ifdef __linux__
@@ -59,7 +59,7 @@ double getTimeStamp() {
 
 using namespace cl::sycl;
 using namespace std;
-using namespace sycl::intel::gpu;
+using namespace sycl::INTEL::gpu;
 
 void initMatrix(int *M, unsigned N) {
   assert(N >= 8 && (((N - 1) & N) == 0) &&
diff --git a/sycl/test/esimd/on-device/matrix_transpose_glb.cpp b/sycl/test/esimd/on-device/matrix_transpose_glb.cpp
index 6591b9fcebc15..24f2bb1942a8b 100644
--- a/sycl/test/esimd/on-device/matrix_transpose_glb.cpp
+++ b/sycl/test/esimd/on-device/matrix_transpose_glb.cpp
@@ -14,7 +14,7 @@
 #include "esimd_test_utils.hpp"
 
 #include <CL/sycl.hpp>
-#include <CL/sycl/intel/esimd.hpp>
+#include <CL/sycl/INTEL/esimd.hpp>
 #include <iostream>
 
 #ifdef __linux__
@@ -59,7 +59,7 @@ double getTimeStamp() {
 
 using namespace cl::sycl;
 using namespace std;
-using namespace sycl::intel::gpu;
+using namespace sycl::INTEL::gpu;
 
 void initMatrix(int *M, unsigned N) {
   assert(N >= 8 && (((N - 1) & N) == 0) &&
diff --git a/sycl/test/esimd/on-device/matrix_transpose_usm.cpp b/sycl/test/esimd/on-device/matrix_transpose_usm.cpp
index 247e45ec70b25..14bd0cc4aa581 100644
--- a/sycl/test/esimd/on-device/matrix_transpose_usm.cpp
+++ b/sycl/test/esimd/on-device/matrix_transpose_usm.cpp
@@ -15,7 +15,7 @@
 #include "esimd_test_utils.hpp"
 
 #include <CL/sycl.hpp>
-#include <CL/sycl/intel/esimd.hpp>
+#include <CL/sycl/INTEL/esimd.hpp>
 #include <iostream>
 
 #ifdef __linux__
@@ -60,7 +60,7 @@ double getTimeStamp() {
 
 using namespace cl::sycl;
 using namespace std;
-using namespace sycl::intel::gpu;
+using namespace sycl::INTEL::gpu;
 
 void initMatrix(int *M, unsigned N) {
   assert(N >= 8 && (((N - 1) & N) == 0) &&
diff --git a/sycl/test/esimd/on-device/slm_barrier.cpp b/sycl/test/esimd/on-device/slm_barrier.cpp
index 39b9c7bd6752e..a564623331c74 100755
--- a/sycl/test/esimd/on-device/slm_barrier.cpp
+++ b/sycl/test/esimd/on-device/slm_barrier.cpp
@@ -14,11 +14,11 @@
 #include "esimd_test_utils.hpp"
 
 #include <CL/sycl.hpp>
-#include <CL/sycl/intel/esimd.hpp>
+#include <CL/sycl/INTEL/esimd.hpp>
 #include <iostream>
 
 using namespace cl::sycl;
-using namespace sycl::intel::gpu;
+using namespace sycl::INTEL::gpu;
 
 #define LOCAL_SIZE 4
 #define GLOBAL_SIZE 6
diff --git a/sycl/test/esimd/on-device/test_id_3d.cpp b/sycl/test/esimd/on-device/test_id_3d.cpp
index 0be7c76515d00..83d6844d12191 100755
--- a/sycl/test/esimd/on-device/test_id_3d.cpp
+++ b/sycl/test/esimd/on-device/test_id_3d.cpp
@@ -18,7 +18,7 @@
 #include "esimd_test_utils.hpp"
 
 #include <CL/sycl.hpp>
-#include <CL/sycl/intel/esimd.hpp>
+#include <CL/sycl/INTEL/esimd.hpp>
 #include <iostream>
 
 using namespace cl::sycl;
@@ -44,7 +44,7 @@ int main(void) {
   auto e = q.submit([&](handler &cgh) {
     cgh.parallel_for<class Test>(
         GlobalRange, [=](item<3> it) SYCL_ESIMD_KERNEL {
-          using namespace sycl::intel::gpu;
+          using namespace sycl::INTEL::gpu;
           auto id = it.get_id();
           // calculate linear ID:
           size_t lin_id = id[0] * Y * X + id[1] * X + id[2];
diff --git a/sycl/test/esimd/on-device/vadd_1d.cpp b/sycl/test/esimd/on-device/vadd_1d.cpp
index ed8c6a8da2635..9e37d3dd785fd 100644
--- a/sycl/test/esimd/on-device/vadd_1d.cpp
+++ b/sycl/test/esimd/on-device/vadd_1d.cpp
@@ -14,7 +14,7 @@
 #include "esimd_test_utils.hpp"
 
 #include <CL/sycl.hpp>
-#include <CL/sycl/intel/esimd.hpp>
+#include <CL/sycl/INTEL/esimd.hpp>
 #include <iostream>
 
 using namespace cl::sycl;
@@ -54,7 +54,7 @@ int main(void) {
       auto PC = bufc.get_access<access::mode::write>(cgh);
       cgh.parallel_for<class Test>(
           GlobalRange * LocalRange, [=](id<1> i) SYCL_ESIMD_KERNEL {
-            using namespace sycl::intel::gpu;
+            using namespace sycl::INTEL::gpu;
             unsigned int offset = i * VL * sizeof(float);
             simd<float, VL> va = block_load<float, VL>(PA, offset);
             simd<float, VL> vb = block_load<float, VL>(PB, offset);
diff --git a/sycl/test/esimd/on-device/vadd_2d.cpp b/sycl/test/esimd/on-device/vadd_2d.cpp
index d1c886efe1b1a..3b6f3cb172f0a 100644
--- a/sycl/test/esimd/on-device/vadd_2d.cpp
+++ b/sycl/test/esimd/on-device/vadd_2d.cpp
@@ -15,7 +15,7 @@
 #include "esimd_test_utils.hpp"
 
 #include <CL/sycl.hpp>
-#include <CL/sycl/intel/esimd.hpp>
+#include <CL/sycl/INTEL/esimd.hpp>
 #include <iostream>
 
 using namespace cl::sycl;
@@ -62,7 +62,7 @@ int main(void) {
 
       cgh.parallel_for<class Test>(
           GlobalRange * LocalRange, [=](id<1> i) SYCL_ESIMD_KERNEL {
-            using namespace sycl::intel::gpu;
+            using namespace sycl::INTEL::gpu;
 
             constexpr int ESIZE = sizeof(int);
             int x = i * ESIZE * VL;
diff --git a/sycl/test/esimd/on-device/vadd_usm.cpp b/sycl/test/esimd/on-device/vadd_usm.cpp
index 073743b16864c..9b7f26cdc35da 100755
--- a/sycl/test/esimd/on-device/vadd_usm.cpp
+++ b/sycl/test/esimd/on-device/vadd_usm.cpp
@@ -15,7 +15,7 @@
 #include "esimd_test_utils.hpp"
 
 #include <CL/sycl.hpp>
-#include <CL/sycl/intel/esimd.hpp>
+#include <CL/sycl/INTEL/esimd.hpp>
 #include <iostream>
 
 using namespace cl::sycl;
@@ -50,7 +50,7 @@ int main(void) {
 
   auto e = q.submit([&](handler &cgh) {
     cgh.parallel_for<class Test>(Range, [=](nd_item<1> ndi) SYCL_ESIMD_KERNEL {
-      using namespace sycl::intel::gpu;
+      using namespace sycl::INTEL::gpu;
 
       int i = ndi.get_global_id(0);
       simd<float, VL> va = block_load<float, VL>(A + i * VL);
diff --git a/sycl/test/esimd/spirv_intrins_trans.cpp b/sycl/test/esimd/spirv_intrins_trans.cpp
index 3327b0c13e117..0f8eee3972a35 100644
--- a/sycl/test/esimd/spirv_intrins_trans.cpp
+++ b/sycl/test/esimd/spirv_intrins_trans.cpp
@@ -3,7 +3,7 @@
 // translated into GenX counterparts (implemented in LowerCM.cpp)
 
 #include <CL/sycl.hpp>
-#include <CL/sycl/intel/esimd.hpp>
+#include <CL/sycl/INTEL/esimd.hpp>
 
 SYCL_EXTERNAL size_t __spirv_GlobalInvocationId_x();
 SYCL_EXTERNAL size_t __spirv_GlobalInvocationId_y();
diff --git a/sycl/test/fpga_tests/fpga_io_pipes.cpp b/sycl/test/fpga_tests/fpga_io_pipes.cpp
index 989e390389418..d1d62cdbc72cc 100644
--- a/sycl/test/fpga_tests/fpga_io_pipes.cpp
+++ b/sycl/test/fpga_tests/fpga_io_pipes.cpp
@@ -8,7 +8,7 @@
 //
 //===----------------------------------------------------------------------===//
 #include <CL/sycl.hpp>
-#include <CL/sycl/intel/fpga_extensions.hpp>
+#include <CL/sycl/INTEL/fpga_extensions.hpp>
 #include <fstream>
 #include <iostream>
 
@@ -113,7 +113,7 @@ int test_io_bl_pipe(cl::sycl::queue Queue) {
 }
 
 int main() {
-  cl::sycl::queue Queue{cl::sycl::intel::fpga_emulator_selector{}};
+  cl::sycl::queue Queue{cl::sycl::INTEL::fpga_emulator_selector{}};
 
   if (!Queue.get_device()
            .get_info<cl::sycl::info::device::kernel_kernel_pipe_support>()) {
diff --git a/sycl/test/fpga_tests/fpga_lsu.cpp b/sycl/test/fpga_tests/fpga_lsu.cpp
index ea85dbff49c90..ffdc1d92bf954 100644
--- a/sycl/test/fpga_tests/fpga_lsu.cpp
+++ b/sycl/test/fpga_tests/fpga_lsu.cpp
@@ -11,7 +11,7 @@
 //
 //===----------------------------------------------------------------------===//
 #include <CL/sycl.hpp>
-#include <CL/sycl/intel/fpga_extensions.hpp>
+#include <CL/sycl/INTEL/fpga_extensions.hpp>
 
 // TODO: run is disabled, since no support added in FPGA backend yet. Check
 // implementation correctness from CXX and SYCL languages perspective.
@@ -42,19 +42,19 @@ int test_lsu(cl::sycl::queue Queue) {
         auto output_ptr = output_accessor.get_pointer();
 
         using PrefetchingLSU =
-            cl::sycl::intel::lsu<cl::sycl::intel::prefetch<true>,
-                                 cl::sycl::intel::statically_coalesce<false>>;
+            cl::sycl::INTEL::lsu<cl::sycl::INTEL::prefetch<true>,
+                                 cl::sycl::INTEL::statically_coalesce<false>>;
 
         using BurstCoalescedLSU =
-            cl::sycl::intel::lsu<cl::sycl::intel::burst_coalesce<true>,
-                                 cl::sycl::intel::statically_coalesce<false>>;
+            cl::sycl::INTEL::lsu<cl::sycl::INTEL::burst_coalesce<true>,
+                                 cl::sycl::INTEL::statically_coalesce<false>>;
 
         using CachingLSU =
-            cl::sycl::intel::lsu<cl::sycl::intel::burst_coalesce<true>,
-                                 cl::sycl::intel::cache<1024>,
-                                 cl::sycl::intel::statically_coalesce<false>>;
+            cl::sycl::INTEL::lsu<cl::sycl::INTEL::burst_coalesce<true>,
+                                 cl::sycl::INTEL::cache<1024>,
+                                 cl::sycl::INTEL::statically_coalesce<false>>;
 
-        using PipelinedLSU = cl::sycl::intel::lsu<>;
+        using PipelinedLSU = cl::sycl::INTEL::lsu<>;
 
         int X = PrefetchingLSU::load(input_ptr); // int X = input_ptr[0]
         int Y = CachingLSU::load(input_ptr + 1); // int Y = input_ptr[1]
@@ -77,7 +77,7 @@ int test_lsu(cl::sycl::queue Queue) {
 }
 
 int main() {
-  cl::sycl::queue Queue{cl::sycl::intel::fpga_emulator_selector{}};
+  cl::sycl::queue Queue{cl::sycl::INTEL::fpga_emulator_selector{}};
 
   return test_lsu(Queue);
 }
diff --git a/sycl/test/fpga_tests/fpga_pipes.cpp b/sycl/test/fpga_tests/fpga_pipes.cpp
index 1eba903d9972e..d5e61b9a6ce28 100644
--- a/sycl/test/fpga_tests/fpga_pipes.cpp
+++ b/sycl/test/fpga_tests/fpga_pipes.cpp
@@ -12,7 +12,7 @@
 //
 //===----------------------------------------------------------------------===//
 #include <CL/sycl.hpp>
-#include <CL/sycl/intel/fpga_extensions.hpp>
+#include <CL/sycl/INTEL/fpga_extensions.hpp>
 #include <iostream>
 
 // Size of an array passing through a pipe
@@ -27,12 +27,11 @@ class nb_pipe;
 }
 
 // For non-blocking template pipes
-template<int N>
-class templ_nb_pipe;
+template <int N> class templ_nb_pipe;
 
 // For non-blocking multiple pipes
-template<int N>
-using PipeMulNb = cl::sycl::intel::pipe<class templ_nb_pipe<N>, int>;
+template <int N>
+using PipeMulNb = cl::sycl::INTEL::pipe<class templ_nb_pipe<N>, int>;
 
 // For simple blocking pipes with explicit type
 class some_bl_pipe;
@@ -43,25 +42,22 @@ class bl_pipe;
 }
 
 // For blocking template pipes
-template<int N>
-class templ_bl_pipe;
+template <int N> class templ_bl_pipe;
 
 // For blocking multiple pipes
-template<int N>
-using PipeMulBl = cl::sycl::intel::pipe<class templ_bl_pipe<N>, int>;
+template <int N>
+using PipeMulBl = cl::sycl::INTEL::pipe<class templ_bl_pipe<N>, int>;
 
 // Kernel names
-template <int TestNumber, int KernelNumber = 0>
-class writer;
-template <int TestNumber, int KernelNumber = 0>
-class reader;
+template <int TestNumber, int KernelNumber = 0> class writer;
+template <int TestNumber, int KernelNumber = 0> class reader;
 
 // Test for simple non-blocking pipes
-template<typename PipeName, int TestNumber>
+template <typename PipeName, int TestNumber>
 int test_simple_nb_pipe(cl::sycl::queue Queue) {
   int data[] = {0};
 
-  using Pipe = cl::sycl::intel::pipe<PipeName, int>;
+  using Pipe = cl::sycl::INTEL::pipe<PipeName, int>;
 
   cl::sycl::buffer<int, 1> readBuf(data, 1);
   Queue.submit([&](cl::sycl::handler &cgh) {
@@ -97,8 +93,7 @@ int test_simple_nb_pipe(cl::sycl::queue Queue) {
 }
 
 // Test for multiple non-blocking pipes
-template<int TestNumber>
-int test_multiple_nb_pipe(cl::sycl::queue Queue) {
+template <int TestNumber> int test_multiple_nb_pipe(cl::sycl::queue Queue) {
   int data[] = {0};
 
   Queue.submit([&](cl::sycl::handler &cgh) {
@@ -149,10 +144,9 @@ int test_multiple_nb_pipe(cl::sycl::queue Queue) {
 }
 
 // Test for array passing through a non-blocking pipe
-template<int TestNumber>
-int test_array_th_nb_pipe(cl::sycl::queue Queue) {
+template <int TestNumber> int test_array_th_nb_pipe(cl::sycl::queue Queue) {
   int data[N] = {0};
-  using AnotherNbPipe = cl::sycl::intel::pipe<class another_nb_pipe, int>;
+  using AnotherNbPipe = cl::sycl::INTEL::pipe<class another_nb_pipe, int>;
 
   Queue.submit([&](cl::sycl::handler &cgh) {
     cgh.single_task<class writer<TestNumber>>([=]() {
@@ -190,11 +184,11 @@ int test_array_th_nb_pipe(cl::sycl::queue Queue) {
 }
 
 // Test for simple blocking pipes
-template<typename PipeName, int TestNumber>
+template <typename PipeName, int TestNumber>
 int test_simple_bl_pipe(cl::sycl::queue Queue) {
   int data[] = {0};
 
-  using Pipe = cl::sycl::intel::pipe<PipeName, int>;
+  using Pipe = cl::sycl::INTEL::pipe<PipeName, int>;
 
   cl::sycl::buffer<int, 1> readBuf(data, 1);
   Queue.submit([&](cl::sycl::handler &cgh) {
@@ -224,8 +218,7 @@ int test_simple_bl_pipe(cl::sycl::queue Queue) {
 }
 
 // Test for multiple blocking pipes
-template<int TestNumber>
-int test_multiple_bl_pipe(cl::sycl::queue Queue) {
+template <int TestNumber> int test_multiple_bl_pipe(cl::sycl::queue Queue) {
   int data[] = {0};
 
   Queue.submit([&](cl::sycl::handler &cgh) {
@@ -261,10 +254,9 @@ int test_multiple_bl_pipe(cl::sycl::queue Queue) {
 }
 
 // Test for array passing through a blocking pipe
-template<int TestNumber>
-int test_array_th_bl_pipe(cl::sycl::queue Queue) {
+template <int TestNumber> int test_array_th_bl_pipe(cl::sycl::queue Queue) {
   int data[N] = {0};
-  using AnotherBlPipe = cl::sycl::intel::pipe<class another_bl_pipe, int>;
+  using AnotherBlPipe = cl::sycl::INTEL::pipe<class another_bl_pipe, int>;
 
   Queue.submit([&](cl::sycl::handler &cgh) {
     cgh.single_task<class writer<TestNumber>>([=]() {
diff --git a/sycl/test/fpga_tests/global_fpga_device_selector.cpp b/sycl/test/fpga_tests/global_fpga_device_selector.cpp
index edd2007cd9bf1..8b3f0c586c5b7 100644
--- a/sycl/test/fpga_tests/global_fpga_device_selector.cpp
+++ b/sycl/test/fpga_tests/global_fpga_device_selector.cpp
@@ -4,14 +4,12 @@
 // RUN: %ACC_RUN_PLACEHOLDER %t.out
 
 #include <CL/sycl.hpp>
-#include <CL/sycl/intel/fpga_extensions.hpp>
+#include <CL/sycl/INTEL/fpga_extensions.hpp>
 
-// Check that FPGA emulator device is found if we try to initialize inline global
-// variable using fpga_emulator_selector parameter.
+// Check that FPGA emulator device is found if we try to initialize inline
+// global variable using fpga_emulator_selector parameter.
 
 inline cl::sycl::queue fpga_emu_queue_inlined{
-    cl::sycl::intel::fpga_emulator_selector{}};
+    cl::sycl::INTEL::fpga_emulator_selector{}};
 
-int main() {
-  return 0;
-}
+int main() { return 0; }
diff --git a/sycl/test/fpga_tests/io_pipe_def.h b/sycl/test/fpga_tests/io_pipe_def.h
index bbfa2f3a0a49d..935170c907cf5 100644
--- a/sycl/test/fpga_tests/io_pipe_def.h
+++ b/sycl/test/fpga_tests/io_pipe_def.h
@@ -1,4 +1,4 @@
-#include <CL/sycl/intel/fpga_extensions.hpp>
+#include <CL/sycl/INTEL/fpga_extensions.hpp>
 
 namespace intelfpga {
 template <unsigned ID> struct ethernet_pipe_id {
@@ -6,7 +6,7 @@ template <unsigned ID> struct ethernet_pipe_id {
 };
 
 using ethernet_read_pipe =
-    sycl::intel::kernel_readable_io_pipe<ethernet_pipe_id<0>, int, 0>;
+    sycl::INTEL::kernel_readable_io_pipe<ethernet_pipe_id<0>, int, 0>;
 using ethernet_write_pipe =
-    sycl::intel::kernel_writeable_io_pipe<ethernet_pipe_id<1>, int, 0>;
+    sycl::INTEL::kernel_writeable_io_pipe<ethernet_pipe_id<1>, int, 0>;
 } // namespace intelfpga
diff --git a/sycl/test/regression/esimd-util-compiler-eval.cpp b/sycl/test/regression/esimd-util-compiler-eval.cpp
index 4d494f1b5e78e..15aead6ce8b17 100644
--- a/sycl/test/regression/esimd-util-compiler-eval.cpp
+++ b/sycl/test/regression/esimd-util-compiler-eval.cpp
@@ -2,7 +2,7 @@
 // This test checks compile-time evaluation of functions from esimd_util.hpp
 
 #include "CL/sycl.hpp"
-#include "CL/sycl/intel/esimd/esimd.hpp"
+#include "CL/sycl/INTEL/esimd/esimd.hpp"
 
 static_assert(__esimd::getNextPowerOf2<0>() == 0, "");
 static_assert(__esimd::getNextPowerOf2<1>() == 1, "");