diff --git a/libclc/generic/include/spirv/math/asinh.h b/libclc/generic/include/spirv/math/asinh.h deleted file mode 100644 index cb9c9bc9c4f38..0000000000000 --- a/libclc/generic/include/spirv/math/asinh.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_asinh - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/asinpi.h b/libclc/generic/include/spirv/math/asinpi.h deleted file mode 100644 index b9fdf7e4ab7f0..0000000000000 --- a/libclc/generic/include/spirv/math/asinpi.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_asinpi - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/atan.h b/libclc/generic/include/spirv/math/atan.h deleted file mode 100644 index 98ac9f2877641..0000000000000 --- a/libclc/generic/include/spirv/math/atan.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_atan - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/atan2.h b/libclc/generic/include/spirv/math/atan2.h deleted file mode 100644 index 24ffda6276a0b..0000000000000 --- a/libclc/generic/include/spirv/math/atan2.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_FUNCTION __spirv_ocl_atan2 -#define __SPIRV_BODY - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/atan2pi.h b/libclc/generic/include/spirv/math/atan2pi.h deleted file mode 100644 index 3c81d3f0b453e..0000000000000 --- a/libclc/generic/include/spirv/math/atan2pi.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_FUNCTION __spirv_ocl_atan2pi -#define __SPIRV_BODY - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/atanh.h b/libclc/generic/include/spirv/math/atanh.h deleted file mode 100644 index bee320f6a457b..0000000000000 --- a/libclc/generic/include/spirv/math/atanh.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_atanh - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/atanpi.h b/libclc/generic/include/spirv/math/atanpi.h deleted file mode 100644 index 68acf4d50d74d..0000000000000 --- a/libclc/generic/include/spirv/math/atanpi.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_atanpi - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/binary_decl.inc b/libclc/generic/include/spirv/math/binary_decl.inc deleted file mode 100644 index 54032de288033..0000000000000 --- a/libclc/generic/include/spirv/math/binary_decl.inc +++ /dev/null @@ -1,10 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -_CLC_OVERLOAD _CLC_DECL __SPIRV_GENTYPE __SPIRV_FUNCTION(__SPIRV_GENTYPE a, __SPIRV_GENTYPE b); -_CLC_OVERLOAD _CLC_DECL __SPIRV_GENTYPE __SPIRV_FUNCTION(__SPIRV_GENTYPE a, __SPIRV_SCALAR_GENTYPE b); diff --git a/libclc/generic/include/spirv/math/cbrt.h b/libclc/generic/include/spirv/math/cbrt.h deleted file mode 100644 index faf431556642f..0000000000000 --- a/libclc/generic/include/spirv/math/cbrt.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_cbrt - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/ceil.h b/libclc/generic/include/spirv/math/ceil.h deleted file mode 100644 index 3bc0489d12bcb..0000000000000 --- a/libclc/generic/include/spirv/math/ceil.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_ceil - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/cos.h b/libclc/generic/include/spirv/math/cos.h deleted file mode 100644 index a9ffe6d1deda4..0000000000000 --- a/libclc/generic/include/spirv/math/cos.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_cos - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/cosh.h b/libclc/generic/include/spirv/math/cosh.h deleted file mode 100644 index 5da156575f155..0000000000000 --- a/libclc/generic/include/spirv/math/cosh.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_cosh - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/cospi.h b/libclc/generic/include/spirv/math/cospi.h deleted file mode 100644 index 867e6cbe364cf..0000000000000 --- a/libclc/generic/include/spirv/math/cospi.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_cospi - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/erf.h b/libclc/generic/include/spirv/math/erf.h deleted file mode 100644 index bb3b22f0ea53b..0000000000000 --- a/libclc/generic/include/spirv/math/erf.h +++ /dev/null @@ -1,17 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#undef __spirv_ocl_erfc - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_erf - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/erfc.h b/libclc/generic/include/spirv/math/erfc.h deleted file mode 100644 index 2ac001cbb957b..0000000000000 --- a/libclc/generic/include/spirv/math/erfc.h +++ /dev/null @@ -1,17 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#undef __spirv_ocl_erfc - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_erfc - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/exp.h b/libclc/generic/include/spirv/math/exp.h deleted file mode 100644 index e6503d1e469f8..0000000000000 --- a/libclc/generic/include/spirv/math/exp.h +++ /dev/null @@ -1,17 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#undef __spirv_ocl_exp - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_exp - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/exp10.h b/libclc/generic/include/spirv/math/exp10.h deleted file mode 100644 index e9e710a19583e..0000000000000 --- a/libclc/generic/include/spirv/math/exp10.h +++ /dev/null @@ -1,17 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#undef __spirv_ocl_exp10 - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_exp10 - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/exp2.h b/libclc/generic/include/spirv/math/exp2.h deleted file mode 100644 index ddbd3d362e75c..0000000000000 --- a/libclc/generic/include/spirv/math/exp2.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_exp2 - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/expm1.h b/libclc/generic/include/spirv/math/expm1.h deleted file mode 100644 index f7623274bf742..0000000000000 --- a/libclc/generic/include/spirv/math/expm1.h +++ /dev/null @@ -1,17 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#undef __spirv_ocl_exp - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_expm1 - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/fabs.h b/libclc/generic/include/spirv/math/fabs.h deleted file mode 100644 index 252516fbd5671..0000000000000 --- a/libclc/generic/include/spirv/math/fabs.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_fabs - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/fdim.h b/libclc/generic/include/spirv/math/fdim.h deleted file mode 100644 index 695995e0f6830..0000000000000 --- a/libclc/generic/include/spirv/math/fdim.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_FUNCTION __spirv_ocl_fdim -#define __SPIRV_BODY - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/floor.h b/libclc/generic/include/spirv/math/floor.h deleted file mode 100644 index b55b62711086c..0000000000000 --- a/libclc/generic/include/spirv/math/floor.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_floor - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/fma.h b/libclc/generic/include/spirv/math/fma.h deleted file mode 100644 index 3986e2d7cef8f..0000000000000 --- a/libclc/generic/include/spirv/math/fma.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_fma - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/fmax.h b/libclc/generic/include/spirv/math/fmax.h deleted file mode 100644 index 1880981ad6544..0000000000000 --- a/libclc/generic/include/spirv/math/fmax.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_fmax - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/fmin.h b/libclc/generic/include/spirv/math/fmin.h deleted file mode 100644 index 4e5d37290ddfa..0000000000000 --- a/libclc/generic/include/spirv/math/fmin.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_fmin - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/fract.inc b/libclc/generic/include/spirv/math/fract.inc deleted file mode 100644 index 78586f8622265..0000000000000 --- a/libclc/generic/include/spirv/math/fract.inc +++ /dev/null @@ -1,11 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -_CLC_OVERLOAD _CLC_DECL __SPIRV_GENTYPE __spirv_ocl_fract(__SPIRV_GENTYPE x, global __SPIRV_GENTYPE *iptr); -_CLC_OVERLOAD _CLC_DECL __SPIRV_GENTYPE __spirv_ocl_fract(__SPIRV_GENTYPE x, local __SPIRV_GENTYPE *iptr); -_CLC_OVERLOAD _CLC_DECL __SPIRV_GENTYPE __spirv_ocl_fract(__SPIRV_GENTYPE x, private __SPIRV_GENTYPE *iptr); diff --git a/libclc/generic/include/spirv/math/frexp.inc b/libclc/generic/include/spirv/math/frexp.inc deleted file mode 100644 index a930eb19b91b7..0000000000000 --- a/libclc/generic/include/spirv/math/frexp.inc +++ /dev/null @@ -1,11 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -_CLC_OVERLOAD _CLC_DECL __SPIRV_GENTYPE __spirv_ocl_frexp(__SPIRV_GENTYPE x, global __SPIRV_INTN *iptr); -_CLC_OVERLOAD _CLC_DECL __SPIRV_GENTYPE __spirv_ocl_frexp(__SPIRV_GENTYPE x, local __SPIRV_INTN *iptr); -_CLC_OVERLOAD _CLC_DECL __SPIRV_GENTYPE __spirv_ocl_frexp(__SPIRV_GENTYPE x, private __SPIRV_INTN *iptr); diff --git a/libclc/generic/include/spirv/math/gentype.inc b/libclc/generic/include/spirv/math/gentype.inc deleted file mode 100644 index dad5c699f9f1b..0000000000000 --- a/libclc/generic/include/spirv/math/gentype.inc +++ /dev/null @@ -1,183 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_SCALAR_GENTYPE float -#define __SPIRV_FPSIZE 32 - -#define __SPIRV_GENTYPE float -#define __SPIRV_INTN int -#define __SPIRV_SCALAR -#include __SPIRV_BODY -#undef __SPIRV_GENTYPE -#undef __SPIRV_INTN -#undef __SPIRV_SCALAR - -#define __SPIRV_GENTYPE float2 -#define __SPIRV_INTN int2 -#define __SPIRV_VECSIZE 2 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_INTN - -#define __SPIRV_GENTYPE float3 -#define __SPIRV_INTN int3 -#define __SPIRV_VECSIZE 3 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_INTN - -#define __SPIRV_GENTYPE float4 -#define __SPIRV_INTN int4 -#define __SPIRV_VECSIZE 4 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_INTN - -#define __SPIRV_GENTYPE float8 -#define __SPIRV_INTN int8 -#define __SPIRV_VECSIZE 8 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_INTN - -#define __SPIRV_GENTYPE float16 -#define __SPIRV_INTN int16 -#define __SPIRV_VECSIZE 16 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_INTN - -#undef __SPIRV_FPSIZE -#undef __SPIRV_SCALAR_GENTYPE - -#ifndef __FLOAT_ONLY -#ifdef cl_khr_fp64 -#pragma OPENCL EXTENSION cl_khr_fp64 : enable - -#define __SPIRV_SCALAR_GENTYPE double -#define __SPIRV_FPSIZE 64 - -#define __SPIRV_SCALAR -#define __SPIRV_GENTYPE double -#define __SPIRV_INTN int -#include __SPIRV_BODY -#undef __SPIRV_GENTYPE -#undef __SPIRV_INTN -#undef __SPIRV_SCALAR - -#define __SPIRV_GENTYPE double2 -#define __SPIRV_INTN int2 -#define __SPIRV_VECSIZE 2 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_INTN - -#define __SPIRV_GENTYPE double3 -#define __SPIRV_INTN int3 -#define __SPIRV_VECSIZE 3 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_INTN - -#define __SPIRV_GENTYPE double4 -#define __SPIRV_INTN int4 -#define __SPIRV_VECSIZE 4 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_INTN - -#define __SPIRV_GENTYPE double8 -#define __SPIRV_INTN int8 -#define __SPIRV_VECSIZE 8 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_INTN - -#define __SPIRV_GENTYPE double16 -#define __SPIRV_INTN int16 -#define __SPIRV_VECSIZE 16 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_INTN - -#undef __SPIRV_FPSIZE -#undef __SPIRV_SCALAR_GENTYPE -#endif -#endif - -#ifndef __FLOAT_ONLY -#ifdef cl_khr_fp16 -#pragma OPENCL EXTENSION cl_khr_fp16 : enable - -#define __SPIRV_SCALAR_GENTYPE half -#define __SPIRV_FPSIZE 16 - -#define __SPIRV_SCALAR -#define __SPIRV_GENTYPE half -#define __SPIRV_INTN int -#include __SPIRV_BODY -#undef __SPIRV_GENTYPE -#undef __SPIRV_INTN -#undef __SPIRV_SCALAR - -#define __SPIRV_GENTYPE half2 -#define __SPIRV_INTN int2 -#define __SPIRV_VECSIZE 2 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_INTN - -#define __SPIRV_GENTYPE half3 -#define __SPIRV_INTN int3 -#define __SPIRV_VECSIZE 3 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_INTN - -#define __SPIRV_GENTYPE half4 -#define __SPIRV_INTN int4 -#define __SPIRV_VECSIZE 4 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_INTN - -#define __SPIRV_GENTYPE half8 -#define __SPIRV_INTN int8 -#define __SPIRV_VECSIZE 8 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_INTN - -#define __SPIRV_GENTYPE half16 -#define __SPIRV_INTN int16 -#define __SPIRV_VECSIZE 16 -#include __SPIRV_BODY -#undef __SPIRV_VECSIZE -#undef __SPIRV_GENTYPE -#undef __SPIRV_INTN - -#undef __SPIRV_FPSIZE -#undef __SPIRV_SCALAR_GENTYPE -#endif -#endif - -#undef __SPIRV_BODY diff --git a/libclc/generic/include/spirv/math/half_cos.h b/libclc/generic/include/spirv/math/half_cos.h deleted file mode 100644 index 04e49fd9d8782..0000000000000 --- a/libclc/generic/include/spirv/math/half_cos.h +++ /dev/null @@ -1,17 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_half_cos -#define __FLOAT_ONLY - -#include - -#undef __FLOAT_ONLY -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/half_divide.h b/libclc/generic/include/spirv/math/half_divide.h deleted file mode 100644 index 3844d9936693d..0000000000000 --- a/libclc/generic/include/spirv/math/half_divide.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_half_divide - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/half_exp.h b/libclc/generic/include/spirv/math/half_exp.h deleted file mode 100644 index 03ec8024c1196..0000000000000 --- a/libclc/generic/include/spirv/math/half_exp.h +++ /dev/null @@ -1,17 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_half_exp -#define __FLOAT_ONLY - -#include - -#undef __FLOAT_ONLY -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/half_exp10.h b/libclc/generic/include/spirv/math/half_exp10.h deleted file mode 100644 index b13a3e366c60d..0000000000000 --- a/libclc/generic/include/spirv/math/half_exp10.h +++ /dev/null @@ -1,17 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_half_exp10 -#define __FLOAT_ONLY - -#include - -#undef __FLOAT_ONLY -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/half_exp2.h b/libclc/generic/include/spirv/math/half_exp2.h deleted file mode 100644 index e4baed8c53ebd..0000000000000 --- a/libclc/generic/include/spirv/math/half_exp2.h +++ /dev/null @@ -1,17 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_half_exp2 -#define __FLOAT_ONLY - -#include - -#undef __FLOAT_ONLY -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/half_log.h b/libclc/generic/include/spirv/math/half_log.h deleted file mode 100644 index bb0201aa5c875..0000000000000 --- a/libclc/generic/include/spirv/math/half_log.h +++ /dev/null @@ -1,17 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_half_log -#define __FLOAT_ONLY - -#include - -#undef __FLOAT_ONLY -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/half_log10.h b/libclc/generic/include/spirv/math/half_log10.h deleted file mode 100644 index bcd97facef300..0000000000000 --- a/libclc/generic/include/spirv/math/half_log10.h +++ /dev/null @@ -1,17 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_half_log10 -#define __FLOAT_ONLY - -#include - -#undef __FLOAT_ONLY -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/half_log2.h b/libclc/generic/include/spirv/math/half_log2.h deleted file mode 100644 index 3666454d06fd8..0000000000000 --- a/libclc/generic/include/spirv/math/half_log2.h +++ /dev/null @@ -1,17 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_half_log2 -#define __FLOAT_ONLY - -#include - -#undef __FLOAT_ONLY -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/half_powr.h b/libclc/generic/include/spirv/math/half_powr.h deleted file mode 100644 index 5c2a8fdea73e9..0000000000000 --- a/libclc/generic/include/spirv/math/half_powr.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_half_powr - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/half_recip.h b/libclc/generic/include/spirv/math/half_recip.h deleted file mode 100644 index 20521f9b7d61a..0000000000000 --- a/libclc/generic/include/spirv/math/half_recip.h +++ /dev/null @@ -1,17 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_half_recip -#define __FLOAT_ONLY - -#include - -#undef __FLOAT_ONLY -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/half_sin.h b/libclc/generic/include/spirv/math/half_sin.h deleted file mode 100644 index 68b60a67eca9e..0000000000000 --- a/libclc/generic/include/spirv/math/half_sin.h +++ /dev/null @@ -1,17 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_half_sin -#define __FLOAT_ONLY - -#include - -#undef __FLOAT_ONLY -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/half_tan.h b/libclc/generic/include/spirv/math/half_tan.h deleted file mode 100644 index cd3bb0e0f1f54..0000000000000 --- a/libclc/generic/include/spirv/math/half_tan.h +++ /dev/null @@ -1,17 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_half_tan -#define __FLOAT_ONLY - -#include - -#undef __FLOAT_ONLY -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/hypot.h b/libclc/generic/include/spirv/math/hypot.h deleted file mode 100644 index 6885693f51290..0000000000000 --- a/libclc/generic/include/spirv/math/hypot.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_FUNCTION __spirv_ocl_hypot -#define __SPIRV_BODY - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/ldexp.h b/libclc/generic/include/spirv/math/ldexp.h deleted file mode 100644 index ffac5cd9f801e..0000000000000 --- a/libclc/generic/include/spirv/math/ldexp.h +++ /dev/null @@ -1,10 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#include diff --git a/libclc/generic/include/spirv/math/lgamma.h b/libclc/generic/include/spirv/math/lgamma.h deleted file mode 100644 index 3c39e30e9292d..0000000000000 --- a/libclc/generic/include/spirv/math/lgamma.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_lgamma - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/lgamma_r.h b/libclc/generic/include/spirv/math/lgamma_r.h deleted file mode 100644 index 073ae713912c7..0000000000000 --- a/libclc/generic/include/spirv/math/lgamma_r.h +++ /dev/null @@ -1,10 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#include diff --git a/libclc/generic/include/spirv/math/lgamma_r.inc b/libclc/generic/include/spirv/math/lgamma_r.inc deleted file mode 100644 index d4b9aa722f87b..0000000000000 --- a/libclc/generic/include/spirv/math/lgamma_r.inc +++ /dev/null @@ -1,11 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -_CLC_OVERLOAD _CLC_DECL __SPIRV_GENTYPE __spirv_ocl_lgamma_r(__SPIRV_GENTYPE x, global __SPIRV_INTN *iptr); -_CLC_OVERLOAD _CLC_DECL __SPIRV_GENTYPE __spirv_ocl_lgamma_r(__SPIRV_GENTYPE x, local __SPIRV_INTN *iptr); -_CLC_OVERLOAD _CLC_DECL __SPIRV_GENTYPE __spirv_ocl_lgamma_r(__SPIRV_GENTYPE x, private __SPIRV_INTN *iptr); diff --git a/libclc/generic/include/spirv/math/log.h b/libclc/generic/include/spirv/math/log.h deleted file mode 100644 index db71dd302de69..0000000000000 --- a/libclc/generic/include/spirv/math/log.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_log - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/log10.h b/libclc/generic/include/spirv/math/log10.h deleted file mode 100644 index 0ee9b53b67c01..0000000000000 --- a/libclc/generic/include/spirv/math/log10.h +++ /dev/null @@ -1,17 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#undef __spirv_ocl_log10 - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_log10 - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/log1p.h b/libclc/generic/include/spirv/math/log1p.h deleted file mode 100644 index 2708ce420713d..0000000000000 --- a/libclc/generic/include/spirv/math/log1p.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_log1p - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/log2.h b/libclc/generic/include/spirv/math/log2.h deleted file mode 100644 index 3dc16b3e2b83f..0000000000000 --- a/libclc/generic/include/spirv/math/log2.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_log2 - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/logb.h b/libclc/generic/include/spirv/math/logb.h deleted file mode 100644 index 976bc9daafafc..0000000000000 --- a/libclc/generic/include/spirv/math/logb.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_logb - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/mad.h b/libclc/generic/include/spirv/math/mad.h deleted file mode 100644 index d64ab1e0c7cf9..0000000000000 --- a/libclc/generic/include/spirv/math/mad.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_mad - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/maxmag.h b/libclc/generic/include/spirv/math/maxmag.h deleted file mode 100644 index 8eda45c4252e6..0000000000000 --- a/libclc/generic/include/spirv/math/maxmag.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_maxmag - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/minmag.h b/libclc/generic/include/spirv/math/minmag.h deleted file mode 100644 index 4ab3a6bd96470..0000000000000 --- a/libclc/generic/include/spirv/math/minmag.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_minmag - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/modf.h b/libclc/generic/include/spirv/math/modf.h deleted file mode 100644 index c28aa77174d8b..0000000000000 --- a/libclc/generic/include/spirv/math/modf.h +++ /dev/null @@ -1,10 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#include diff --git a/libclc/generic/include/spirv/math/modf.inc b/libclc/generic/include/spirv/math/modf.inc deleted file mode 100644 index d6e1d4a651574..0000000000000 --- a/libclc/generic/include/spirv/math/modf.inc +++ /dev/null @@ -1,11 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -_CLC_OVERLOAD _CLC_DECL __SPIRV_GENTYPE __spirv_ocl_modf(__SPIRV_GENTYPE x, global __SPIRV_GENTYPE *iptr); -_CLC_OVERLOAD _CLC_DECL __SPIRV_GENTYPE __spirv_ocl_modf(__SPIRV_GENTYPE x, local __SPIRV_GENTYPE *iptr); -_CLC_OVERLOAD _CLC_DECL __SPIRV_GENTYPE __spirv_ocl_modf(__SPIRV_GENTYPE x, private __SPIRV_GENTYPE *iptr); diff --git a/libclc/generic/include/spirv/math/nan.h b/libclc/generic/include/spirv/math/nan.h deleted file mode 100644 index 1f50b5f58aa86..0000000000000 --- a/libclc/generic/include/spirv/math/nan.h +++ /dev/null @@ -1,16 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_CONCAT(x, y) x ## y -#define __SPIRV_XCONCAT(x, y) __SPIRV_CONCAT(x, y) - -#define __SPIRV_BODY -#include - -#undef __SPIRV_XCONCAT -#undef __SPIRV_CONCAT diff --git a/libclc/generic/include/spirv/math/nan.inc b/libclc/generic/include/spirv/math/nan.inc deleted file mode 100644 index 24b11e9c62aac..0000000000000 --- a/libclc/generic/include/spirv/math/nan.inc +++ /dev/null @@ -1,26 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#ifdef __SPIRV_SCALAR -#define __SPIRV_VECSIZE -#endif - -#if __SPIRV_FPSIZE == 64 -#define __SPIRV_NATN __SPIRV_XCONCAT(ulong, __SPIRV_VECSIZE) -#elif __SPIRV_FPSIZE == 32 -#define __SPIRV_NATN __SPIRV_XCONCAT(uint, __SPIRV_VECSIZE) -#elif __SPIRV_FPSIZE == 16 -#define __SPIRV_NATN __SPIRV_XCONCAT(ushort, __SPIRV_VECSIZE) -#endif - -_CLC_OVERLOAD _CLC_DECL __SPIRV_GENTYPE __spirv_ocl_nan(__SPIRV_NATN code); - -#undef __SPIRV_NATN -#ifdef __SPIRV_SCALAR -#undef __SPIRV_VECSIZE -#endif diff --git a/libclc/generic/include/spirv/math/native_cos.h b/libclc/generic/include/spirv/math/native_cos.h deleted file mode 100644 index 701e4d931901a..0000000000000 --- a/libclc/generic/include/spirv/math/native_cos.h +++ /dev/null @@ -1,17 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_native_cos -#define __FLOAT_ONLY - -#include - -#undef __FLOAT_ONLY -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/native_divide.h b/libclc/generic/include/spirv/math/native_divide.h deleted file mode 100644 index 5c69db9ac254b..0000000000000 --- a/libclc/generic/include/spirv/math/native_divide.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_native_divide - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/native_exp.h b/libclc/generic/include/spirv/math/native_exp.h deleted file mode 100644 index 30f07fcfe120e..0000000000000 --- a/libclc/generic/include/spirv/math/native_exp.h +++ /dev/null @@ -1,17 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_native_exp -#define __FLOAT_ONLY - -#include - -#undef __FLOAT_ONLY -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/native_exp10.h b/libclc/generic/include/spirv/math/native_exp10.h deleted file mode 100644 index 826cb92de1fe1..0000000000000 --- a/libclc/generic/include/spirv/math/native_exp10.h +++ /dev/null @@ -1,17 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_native_exp10 -#define __FLOAT_ONLY - -#include - -#undef __FLOAT_ONLY -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/native_exp2.h b/libclc/generic/include/spirv/math/native_exp2.h deleted file mode 100644 index 7c80edfc62b88..0000000000000 --- a/libclc/generic/include/spirv/math/native_exp2.h +++ /dev/null @@ -1,17 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_native_exp2 -#define __FLOAT_ONLY - -#include - -#undef __FLOAT_ONLY -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/native_log.h b/libclc/generic/include/spirv/math/native_log.h deleted file mode 100644 index 69b35dfa77d9b..0000000000000 --- a/libclc/generic/include/spirv/math/native_log.h +++ /dev/null @@ -1,17 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_native_log -#define __FLOAT_ONLY - -#include - -#undef __FLOAT_ONLY -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/native_log10.h b/libclc/generic/include/spirv/math/native_log10.h deleted file mode 100644 index c3886143542f8..0000000000000 --- a/libclc/generic/include/spirv/math/native_log10.h +++ /dev/null @@ -1,17 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_native_log10 -#define __FLOAT_ONLY - -#include - -#undef __FLOAT_ONLY -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/native_log2.h b/libclc/generic/include/spirv/math/native_log2.h deleted file mode 100644 index 3731010e6db77..0000000000000 --- a/libclc/generic/include/spirv/math/native_log2.h +++ /dev/null @@ -1,17 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_native_log2 -#define __FLOAT_ONLY - -#include - -#undef __FLOAT_ONLY -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/native_powr.h b/libclc/generic/include/spirv/math/native_powr.h deleted file mode 100644 index 0d557a374d3b5..0000000000000 --- a/libclc/generic/include/spirv/math/native_powr.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_native_powr - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/native_recip.h b/libclc/generic/include/spirv/math/native_recip.h deleted file mode 100644 index 8679c8a98057e..0000000000000 --- a/libclc/generic/include/spirv/math/native_recip.h +++ /dev/null @@ -1,17 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_native_recip -#define __FLOAT_ONLY - -#include - -#undef __FLOAT_ONLY -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/native_sin.h b/libclc/generic/include/spirv/math/native_sin.h deleted file mode 100644 index 04e9d2b58cb5a..0000000000000 --- a/libclc/generic/include/spirv/math/native_sin.h +++ /dev/null @@ -1,17 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_native_sin -#define __FLOAT_ONLY - -#include - -#undef __FLOAT_ONLY -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/native_tan.h b/libclc/generic/include/spirv/math/native_tan.h deleted file mode 100644 index 44f5ed132554a..0000000000000 --- a/libclc/generic/include/spirv/math/native_tan.h +++ /dev/null @@ -1,17 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_native_tan -#define __FLOAT_ONLY - -#include - -#undef __FLOAT_ONLY -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/nextafter.h b/libclc/generic/include/spirv/math/nextafter.h deleted file mode 100644 index 47a398c1a3b28..0000000000000 --- a/libclc/generic/include/spirv/math/nextafter.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_FUNCTION __spirv_ocl_nextafter -#define __SPIRV_BODY - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/pow.h b/libclc/generic/include/spirv/math/pow.h deleted file mode 100644 index c987463e86a59..0000000000000 --- a/libclc/generic/include/spirv/math/pow.h +++ /dev/null @@ -1,13 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_FUNCTION __spirv_ocl_pow -#define __SPIRV_BODY -#include -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/pown.h b/libclc/generic/include/spirv/math/pown.h deleted file mode 100644 index b87cd439f9afd..0000000000000 --- a/libclc/generic/include/spirv/math/pown.h +++ /dev/null @@ -1,11 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#include -#undef __SPIRV_BODY diff --git a/libclc/generic/include/spirv/math/powr.h b/libclc/generic/include/spirv/math/powr.h deleted file mode 100644 index 585ec9ff03310..0000000000000 --- a/libclc/generic/include/spirv/math/powr.h +++ /dev/null @@ -1,13 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_FUNCTION __spirv_ocl_powr -#define __SPIRV_BODY -#include -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/remainder.h b/libclc/generic/include/spirv/math/remainder.h deleted file mode 100644 index d557f1fb2c762..0000000000000 --- a/libclc/generic/include/spirv/math/remainder.h +++ /dev/null @@ -1,12 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_FUNCTION __spirv_ocl_remainder -#define __SPIRV_BODY -#include -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/remquo.h b/libclc/generic/include/spirv/math/remquo.h deleted file mode 100644 index 6f9bcacf90684..0000000000000 --- a/libclc/generic/include/spirv/math/remquo.h +++ /dev/null @@ -1,26 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_FUNCTION __spirv_ocl_remquo - -#define __SPIRV_BODY -#define __SPIRV_ADDRESS_SPACE global -#include -#undef __SPIRV_ADDRESS_SPACE - -#define __SPIRV_BODY -#define __SPIRV_ADDRESS_SPACE local -#include -#undef __SPIRV_ADDRESS_SPACE - -#define __SPIRV_BODY -#define __SPIRV_ADDRESS_SPACE private -#include -#undef __SPIRV_ADDRESS_SPACE - -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/rint.h b/libclc/generic/include/spirv/math/rint.h deleted file mode 100644 index 567fce79cc237..0000000000000 --- a/libclc/generic/include/spirv/math/rint.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_rint - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/rootn.h b/libclc/generic/include/spirv/math/rootn.h deleted file mode 100644 index e1677158c1b13..0000000000000 --- a/libclc/generic/include/spirv/math/rootn.h +++ /dev/null @@ -1,11 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#include -#undef __SPIRV_BODY diff --git a/libclc/generic/include/spirv/math/round.h b/libclc/generic/include/spirv/math/round.h deleted file mode 100644 index f27c2431f53ab..0000000000000 --- a/libclc/generic/include/spirv/math/round.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_round - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/sin.h b/libclc/generic/include/spirv/math/sin.h deleted file mode 100644 index abb22b6a51795..0000000000000 --- a/libclc/generic/include/spirv/math/sin.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_sin - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/sincos.h b/libclc/generic/include/spirv/math/sincos.h deleted file mode 100644 index d85c5be453248..0000000000000 --- a/libclc/generic/include/spirv/math/sincos.h +++ /dev/null @@ -1,10 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#include diff --git a/libclc/generic/include/spirv/math/sincos.inc b/libclc/generic/include/spirv/math/sincos.inc deleted file mode 100644 index 9e814fb55bfb4..0000000000000 --- a/libclc/generic/include/spirv/math/sincos.inc +++ /dev/null @@ -1,11 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - - _CLC_OVERLOAD _CLC_DECL __SPIRV_GENTYPE __spirv_ocl_sincos (__SPIRV_GENTYPE x, global __SPIRV_GENTYPE * cosval); - _CLC_OVERLOAD _CLC_DECL __SPIRV_GENTYPE __spirv_ocl_sincos (__SPIRV_GENTYPE x, local __SPIRV_GENTYPE * cosval); - _CLC_OVERLOAD _CLC_DECL __SPIRV_GENTYPE __spirv_ocl_sincos (__SPIRV_GENTYPE x, private __SPIRV_GENTYPE * cosval); diff --git a/libclc/generic/include/spirv/math/sinh.h b/libclc/generic/include/spirv/math/sinh.h deleted file mode 100644 index 968e3f5f64bd6..0000000000000 --- a/libclc/generic/include/spirv/math/sinh.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_sinh - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/sinpi.h b/libclc/generic/include/spirv/math/sinpi.h deleted file mode 100644 index cc786d36ebbb4..0000000000000 --- a/libclc/generic/include/spirv/math/sinpi.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_sinpi - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/tan.h b/libclc/generic/include/spirv/math/tan.h deleted file mode 100644 index f2bbed82c1ff6..0000000000000 --- a/libclc/generic/include/spirv/math/tan.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_tan - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/tanh.h b/libclc/generic/include/spirv/math/tanh.h deleted file mode 100644 index 53966e39148d6..0000000000000 --- a/libclc/generic/include/spirv/math/tanh.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_tanh - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/tanpi.h b/libclc/generic/include/spirv/math/tanpi.h deleted file mode 100644 index 8bca460c8b23c..0000000000000 --- a/libclc/generic/include/spirv/math/tanpi.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_tanpi - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/ternary_decl.inc b/libclc/generic/include/spirv/math/ternary_decl.inc deleted file mode 100644 index 1cada09fc3c75..0000000000000 --- a/libclc/generic/include/spirv/math/ternary_decl.inc +++ /dev/null @@ -1,9 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -_CLC_OVERLOAD _CLC_DECL __SPIRV_GENTYPE __SPIRV_FUNCTION(__SPIRV_GENTYPE a, __SPIRV_GENTYPE b, __SPIRV_GENTYPE c); diff --git a/libclc/generic/include/spirv/math/tgamma.h b/libclc/generic/include/spirv/math/tgamma.h deleted file mode 100644 index aba422bc84b35..0000000000000 --- a/libclc/generic/include/spirv/math/tgamma.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_tgamma - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/trunc.h b/libclc/generic/include/spirv/math/trunc.h deleted file mode 100644 index 9dc553646a37f..0000000000000 --- a/libclc/generic/include/spirv/math/trunc.h +++ /dev/null @@ -1,15 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_trunc - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION diff --git a/libclc/generic/include/spirv/math/unary_decl.inc b/libclc/generic/include/spirv/math/unary_decl.inc deleted file mode 100644 index ed40a507bb317..0000000000000 --- a/libclc/generic/include/spirv/math/unary_decl.inc +++ /dev/null @@ -1,9 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -_CLC_OVERLOAD _CLC_DECL __SPIRV_GENTYPE __SPIRV_FUNCTION(__SPIRV_GENTYPE x); diff --git a/libclc/generic/include/spirv/spirv.h b/libclc/generic/include/spirv/spirv.h index 4f110280be140..7083667856b96 100644 --- a/libclc/generic/include/spirv/spirv.h +++ b/libclc/generic/include/spirv/spirv.h @@ -46,96 +46,6 @@ #include #include -/* 6.11.2 Math Functions */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - /* 6.11.2.1 Floating-point macros */ #include diff --git a/libclc/generic/include/spirv/spirv_builtins.h b/libclc/generic/include/spirv/spirv_builtins.h index 7700ee4f05132..e59c1850446d3 100644 --- a/libclc/generic/include/spirv/spirv_builtins.h +++ b/libclc/generic/include/spirv/spirv_builtins.h @@ -12426,6 +12426,479 @@ _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t __spirv_Unordered(__clc_vec16_fp16_t, __clc_vec16_fp16_t); #endif +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_acos(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_acos(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_acos(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_acos(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_acos(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_acos(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_acos(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_acos(__clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_acos(__clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_acos(__clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_acos(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_acos(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_acos(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_acos(__clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_acos(__clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_acos(__clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_acos(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_acos(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_acosh(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_acosh(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_acosh(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_acosh(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_acosh(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_acosh(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_acosh(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_acosh(__clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_acosh(__clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_acosh(__clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_acosh(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_acosh(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_acosh(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_acosh(__clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_acosh(__clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_acosh(__clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_acosh(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_acosh(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_acospi(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_acospi(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_acospi(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_acospi(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_acospi(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_acospi(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_acospi(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_acospi(__clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_acospi(__clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_acospi(__clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_acospi(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_acospi(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_acospi(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_acospi(__clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_acospi(__clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_acospi(__clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_acospi(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_acospi(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_asin(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_asin(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_asin(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_asin(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_asin(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_asin(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_asin(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_asin(__clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_asin(__clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_asin(__clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_asin(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_asin(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_asin(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_asin(__clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_asin(__clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_asin(__clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_asin(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_asin(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_asinh(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_asinh(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_asinh(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_asinh(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_asinh(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_asinh(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_asinh(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_asinh(__clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_asinh(__clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_asinh(__clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_asinh(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_asinh(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_asinh(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_asinh(__clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_asinh(__clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_asinh(__clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_asinh(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_asinh(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_asinpi(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_asinpi(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_asinpi(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_asinpi(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_asinpi(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_asinpi(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_asinpi(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_asinpi(__clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_asinpi(__clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_asinpi(__clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_asinpi(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_asinpi(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_asinpi(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_asinpi(__clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_asinpi(__clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_asinpi(__clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_asinpi(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_asinpi(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_atan(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_atan(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_atan(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_atan(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_atan(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_atan(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_atan(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_atan(__clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_atan(__clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_atan(__clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_atan(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_atan(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_atan(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_atan(__clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_atan(__clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_atan(__clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_atan(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_atan(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_atan2(__clc_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_atan2(__clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_atan2(__clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_atan2(__clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_atan2(__clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_atan2(__clc_vec16_fp32_t, __clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t + __spirv_ocl_atan2(__clc_fp64_t, __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_atan2(__clc_vec2_fp64_t, __clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_atan2(__clc_vec3_fp64_t, __clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_atan2(__clc_vec4_fp64_t, __clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_atan2(__clc_vec8_fp64_t, __clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_atan2(__clc_vec16_fp64_t, __clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t + __spirv_ocl_atan2(__clc_fp16_t, __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_atan2(__clc_vec2_fp16_t, __clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_atan2(__clc_vec3_fp16_t, __clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_atan2(__clc_vec4_fp16_t, __clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_atan2(__clc_vec8_fp16_t, __clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_atan2(__clc_vec16_fp16_t, __clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_atan2pi(__clc_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_atan2pi(__clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_atan2pi(__clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_atan2pi(__clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_atan2pi(__clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_atan2pi(__clc_vec16_fp32_t, __clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t + __spirv_ocl_atan2pi(__clc_fp64_t, __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_atan2pi(__clc_vec2_fp64_t, __clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_atan2pi(__clc_vec3_fp64_t, __clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_atan2pi(__clc_vec4_fp64_t, __clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_atan2pi(__clc_vec8_fp64_t, __clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_atan2pi(__clc_vec16_fp64_t, __clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t + __spirv_ocl_atan2pi(__clc_fp16_t, __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_atan2pi(__clc_vec2_fp16_t, __clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_atan2pi(__clc_vec3_fp16_t, __clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_atan2pi(__clc_vec4_fp16_t, __clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_atan2pi(__clc_vec8_fp16_t, __clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_atan2pi(__clc_vec16_fp16_t, __clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_atanh(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_atanh(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_atanh(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_atanh(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_atanh(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_atanh(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_atanh(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_atanh(__clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_atanh(__clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_atanh(__clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_atanh(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_atanh(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_atanh(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_atanh(__clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_atanh(__clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_atanh(__clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_atanh(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_atanh(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_atanpi(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_atanpi(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_atanpi(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_atanpi(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_atanpi(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_atanpi(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_atanpi(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_atanpi(__clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_atanpi(__clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_atanpi(__clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_atanpi(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_atanpi(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_atanpi(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_atanpi(__clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_atanpi(__clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_atanpi(__clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_atanpi(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_atanpi(__clc_vec16_fp16_t); +#endif + _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_char_t __spirv_ocl_bitselect(__clc_char_t, __clc_char_t, __clc_char_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_char_t __spirv_ocl_bitselect( @@ -12535,570 +13008,2801 @@ _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint64_t __spirv_ocl_bitselect( _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint64_t __spirv_ocl_bitselect( __clc_vec16_uint64_t, __clc_vec16_uint64_t, __clc_vec16_uint64_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t - __spirv_ocl_bitselect(__clc_fp32_t, __clc_fp32_t, __clc_fp32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t __spirv_ocl_bitselect( - __clc_vec2_fp32_t, __clc_vec2_fp32_t, __clc_vec2_fp32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t __spirv_ocl_bitselect( - __clc_vec3_fp32_t, __clc_vec3_fp32_t, __clc_vec3_fp32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t __spirv_ocl_bitselect( - __clc_vec4_fp32_t, __clc_vec4_fp32_t, __clc_vec4_fp32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t __spirv_ocl_bitselect( - __clc_vec8_fp32_t, __clc_vec8_fp32_t, __clc_vec8_fp32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t __spirv_ocl_bitselect( - __clc_vec16_fp32_t, __clc_vec16_fp32_t, __clc_vec16_fp32_t); + __spirv_ocl_bitselect(__clc_fp32_t, __clc_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t __spirv_ocl_bitselect( + __clc_vec2_fp32_t, __clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t __spirv_ocl_bitselect( + __clc_vec3_fp32_t, __clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t __spirv_ocl_bitselect( + __clc_vec4_fp32_t, __clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t __spirv_ocl_bitselect( + __clc_vec8_fp32_t, __clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t __spirv_ocl_bitselect( + __clc_vec16_fp32_t, __clc_vec16_fp32_t, __clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t + __spirv_ocl_bitselect(__clc_fp64_t, __clc_fp64_t, __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t __spirv_ocl_bitselect( + __clc_vec2_fp64_t, __clc_vec2_fp64_t, __clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t __spirv_ocl_bitselect( + __clc_vec3_fp64_t, __clc_vec3_fp64_t, __clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t __spirv_ocl_bitselect( + __clc_vec4_fp64_t, __clc_vec4_fp64_t, __clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t __spirv_ocl_bitselect( + __clc_vec8_fp64_t, __clc_vec8_fp64_t, __clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t __spirv_ocl_bitselect( + __clc_vec16_fp64_t, __clc_vec16_fp64_t, __clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t + __spirv_ocl_bitselect(__clc_fp16_t, __clc_fp16_t, __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t __spirv_ocl_bitselect( + __clc_vec2_fp16_t, __clc_vec2_fp16_t, __clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t __spirv_ocl_bitselect( + __clc_vec3_fp16_t, __clc_vec3_fp16_t, __clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t __spirv_ocl_bitselect( + __clc_vec4_fp16_t, __clc_vec4_fp16_t, __clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t __spirv_ocl_bitselect( + __clc_vec8_fp16_t, __clc_vec8_fp16_t, __clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t __spirv_ocl_bitselect( + __clc_vec16_fp16_t, __clc_vec16_fp16_t, __clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_cbrt(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_cbrt(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_cbrt(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_cbrt(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_cbrt(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_cbrt(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_cbrt(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_cbrt(__clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_cbrt(__clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_cbrt(__clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_cbrt(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_cbrt(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_cbrt(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_cbrt(__clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_cbrt(__clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_cbrt(__clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_cbrt(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_cbrt(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_ceil(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_ceil(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_ceil(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_ceil(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_ceil(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_ceil(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_ceil(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_ceil(__clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_ceil(__clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_ceil(__clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_ceil(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_ceil(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_ceil(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_ceil(__clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_ceil(__clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_ceil(__clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_ceil(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_ceil(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_char_t __spirv_ocl_clz(__clc_char_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec2_char_t __spirv_ocl_clz(__clc_vec2_char_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec3_char_t __spirv_ocl_clz(__clc_vec3_char_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec4_char_t __spirv_ocl_clz(__clc_vec4_char_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec8_char_t __spirv_ocl_clz(__clc_vec8_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_char_t + __spirv_ocl_clz(__clc_vec16_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_int8_t __spirv_ocl_clz(__clc_int8_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t __spirv_ocl_clz(__clc_vec2_int8_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t __spirv_ocl_clz(__clc_vec3_int8_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t __spirv_ocl_clz(__clc_vec4_int8_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t __spirv_ocl_clz(__clc_vec8_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_ocl_clz(__clc_vec16_int8_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_int16_t __spirv_ocl_clz(__clc_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int16_t + __spirv_ocl_clz(__clc_vec2_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int16_t + __spirv_ocl_clz(__clc_vec3_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int16_t + __spirv_ocl_clz(__clc_vec4_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int16_t + __spirv_ocl_clz(__clc_vec8_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int16_t + __spirv_ocl_clz(__clc_vec16_int16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_int32_t __spirv_ocl_clz(__clc_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int32_t + __spirv_ocl_clz(__clc_vec2_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int32_t + __spirv_ocl_clz(__clc_vec3_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int32_t + __spirv_ocl_clz(__clc_vec4_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int32_t + __spirv_ocl_clz(__clc_vec8_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int32_t + __spirv_ocl_clz(__clc_vec16_int32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_int64_t __spirv_ocl_clz(__clc_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int64_t + __spirv_ocl_clz(__clc_vec2_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int64_t + __spirv_ocl_clz(__clc_vec3_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int64_t + __spirv_ocl_clz(__clc_vec4_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int64_t + __spirv_ocl_clz(__clc_vec8_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int64_t + __spirv_ocl_clz(__clc_vec16_int64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_uint8_t __spirv_ocl_clz(__clc_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint8_t + __spirv_ocl_clz(__clc_vec2_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint8_t + __spirv_ocl_clz(__clc_vec3_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint8_t + __spirv_ocl_clz(__clc_vec4_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint8_t + __spirv_ocl_clz(__clc_vec8_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint8_t + __spirv_ocl_clz(__clc_vec16_uint8_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_uint16_t __spirv_ocl_clz(__clc_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint16_t + __spirv_ocl_clz(__clc_vec2_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint16_t + __spirv_ocl_clz(__clc_vec3_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint16_t + __spirv_ocl_clz(__clc_vec4_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint16_t + __spirv_ocl_clz(__clc_vec8_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint16_t + __spirv_ocl_clz(__clc_vec16_uint16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_uint32_t __spirv_ocl_clz(__clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint32_t + __spirv_ocl_clz(__clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint32_t + __spirv_ocl_clz(__clc_vec3_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint32_t + __spirv_ocl_clz(__clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint32_t + __spirv_ocl_clz(__clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint32_t + __spirv_ocl_clz(__clc_vec16_uint32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_uint64_t __spirv_ocl_clz(__clc_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint64_t + __spirv_ocl_clz(__clc_vec2_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint64_t + __spirv_ocl_clz(__clc_vec3_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint64_t + __spirv_ocl_clz(__clc_vec4_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint64_t + __spirv_ocl_clz(__clc_vec8_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint64_t + __spirv_ocl_clz(__clc_vec16_uint64_t); + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_copysign(__clc_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_copysign(__clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_copysign(__clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_copysign(__clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_copysign(__clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_copysign(__clc_vec16_fp32_t, __clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t + __spirv_ocl_copysign(__clc_fp64_t, __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_copysign(__clc_vec2_fp64_t, __clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_copysign(__clc_vec3_fp64_t, __clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_copysign(__clc_vec4_fp64_t, __clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_copysign(__clc_vec8_fp64_t, __clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_copysign(__clc_vec16_fp64_t, __clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t + __spirv_ocl_copysign(__clc_fp16_t, __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_copysign(__clc_vec2_fp16_t, __clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_copysign(__clc_vec3_fp16_t, __clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_copysign(__clc_vec4_fp16_t, __clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_copysign(__clc_vec8_fp16_t, __clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_copysign(__clc_vec16_fp16_t, __clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_cos(__clc_fp32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t __spirv_ocl_cos(__clc_vec2_fp32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t __spirv_ocl_cos(__clc_vec3_fp32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t __spirv_ocl_cos(__clc_vec4_fp32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t __spirv_ocl_cos(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_cos(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_cos(__clc_fp64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t __spirv_ocl_cos(__clc_vec2_fp64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t __spirv_ocl_cos(__clc_vec3_fp64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t __spirv_ocl_cos(__clc_vec4_fp64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t __spirv_ocl_cos(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_cos(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_cos(__clc_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t __spirv_ocl_cos(__clc_vec2_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t __spirv_ocl_cos(__clc_vec3_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t __spirv_ocl_cos(__clc_vec4_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t __spirv_ocl_cos(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_cos(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_cosh(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_cosh(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_cosh(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_cosh(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_cosh(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_cosh(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_cosh(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_cosh(__clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_cosh(__clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_cosh(__clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_cosh(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_cosh(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_cosh(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_cosh(__clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_cosh(__clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_cosh(__clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_cosh(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_cosh(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_cospi(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_cospi(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_cospi(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_cospi(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_cospi(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_cospi(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_cospi(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_cospi(__clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_cospi(__clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_cospi(__clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_cospi(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_cospi(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_cospi(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_cospi(__clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_cospi(__clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_cospi(__clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_cospi(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_cospi(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_cross(__clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_cross(__clc_vec4_fp32_t, __clc_vec4_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_cross(__clc_vec3_fp64_t, __clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_cross(__clc_vec4_fp64_t, __clc_vec4_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_cross(__clc_vec3_fp16_t, __clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_cross(__clc_vec4_fp16_t, __clc_vec4_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_char_t __spirv_ocl_ctz(__clc_char_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec2_char_t __spirv_ocl_ctz(__clc_vec2_char_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec3_char_t __spirv_ocl_ctz(__clc_vec3_char_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec4_char_t __spirv_ocl_ctz(__clc_vec4_char_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec8_char_t __spirv_ocl_ctz(__clc_vec8_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_char_t + __spirv_ocl_ctz(__clc_vec16_char_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_int8_t __spirv_ocl_ctz(__clc_int8_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t __spirv_ocl_ctz(__clc_vec2_int8_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t __spirv_ocl_ctz(__clc_vec3_int8_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t __spirv_ocl_ctz(__clc_vec4_int8_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t __spirv_ocl_ctz(__clc_vec8_int8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t + __spirv_ocl_ctz(__clc_vec16_int8_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_int16_t __spirv_ocl_ctz(__clc_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int16_t + __spirv_ocl_ctz(__clc_vec2_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int16_t + __spirv_ocl_ctz(__clc_vec3_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int16_t + __spirv_ocl_ctz(__clc_vec4_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int16_t + __spirv_ocl_ctz(__clc_vec8_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int16_t + __spirv_ocl_ctz(__clc_vec16_int16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_int32_t __spirv_ocl_ctz(__clc_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int32_t + __spirv_ocl_ctz(__clc_vec2_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int32_t + __spirv_ocl_ctz(__clc_vec3_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int32_t + __spirv_ocl_ctz(__clc_vec4_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int32_t + __spirv_ocl_ctz(__clc_vec8_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int32_t + __spirv_ocl_ctz(__clc_vec16_int32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_int64_t __spirv_ocl_ctz(__clc_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int64_t + __spirv_ocl_ctz(__clc_vec2_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int64_t + __spirv_ocl_ctz(__clc_vec3_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int64_t + __spirv_ocl_ctz(__clc_vec4_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int64_t + __spirv_ocl_ctz(__clc_vec8_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int64_t + __spirv_ocl_ctz(__clc_vec16_int64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_uint8_t __spirv_ocl_ctz(__clc_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint8_t + __spirv_ocl_ctz(__clc_vec2_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint8_t + __spirv_ocl_ctz(__clc_vec3_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint8_t + __spirv_ocl_ctz(__clc_vec4_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint8_t + __spirv_ocl_ctz(__clc_vec8_uint8_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint8_t + __spirv_ocl_ctz(__clc_vec16_uint8_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_uint16_t __spirv_ocl_ctz(__clc_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint16_t + __spirv_ocl_ctz(__clc_vec2_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint16_t + __spirv_ocl_ctz(__clc_vec3_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint16_t + __spirv_ocl_ctz(__clc_vec4_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint16_t + __spirv_ocl_ctz(__clc_vec8_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint16_t + __spirv_ocl_ctz(__clc_vec16_uint16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_uint32_t __spirv_ocl_ctz(__clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint32_t + __spirv_ocl_ctz(__clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint32_t + __spirv_ocl_ctz(__clc_vec3_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint32_t + __spirv_ocl_ctz(__clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint32_t + __spirv_ocl_ctz(__clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint32_t + __spirv_ocl_ctz(__clc_vec16_uint32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_uint64_t __spirv_ocl_ctz(__clc_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint64_t + __spirv_ocl_ctz(__clc_vec2_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint64_t + __spirv_ocl_ctz(__clc_vec3_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint64_t + __spirv_ocl_ctz(__clc_vec4_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint64_t + __spirv_ocl_ctz(__clc_vec8_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint64_t + __spirv_ocl_ctz(__clc_vec16_uint64_t); + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_degrees(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_degrees(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_degrees(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_degrees(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_degrees(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_degrees(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_degrees(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_degrees(__clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_degrees(__clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_degrees(__clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_degrees(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_degrees(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_degrees(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_degrees(__clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_degrees(__clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_degrees(__clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_degrees(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_degrees(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_distance(__clc_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_distance(__clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_distance(__clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_distance(__clc_vec4_fp32_t, __clc_vec4_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t + __spirv_ocl_distance(__clc_fp64_t, __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t + __spirv_ocl_distance(__clc_vec2_fp64_t, __clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t + __spirv_ocl_distance(__clc_vec3_fp64_t, __clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t + __spirv_ocl_distance(__clc_vec4_fp64_t, __clc_vec4_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t + __spirv_ocl_distance(__clc_fp16_t, __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t + __spirv_ocl_distance(__clc_vec2_fp16_t, __clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t + __spirv_ocl_distance(__clc_vec3_fp16_t, __clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t + __spirv_ocl_distance(__clc_vec4_fp16_t, __clc_vec4_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_erf(__clc_fp32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t __spirv_ocl_erf(__clc_vec2_fp32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t __spirv_ocl_erf(__clc_vec3_fp32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t __spirv_ocl_erf(__clc_vec4_fp32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t __spirv_ocl_erf(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_erf(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_erf(__clc_fp64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t __spirv_ocl_erf(__clc_vec2_fp64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t __spirv_ocl_erf(__clc_vec3_fp64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t __spirv_ocl_erf(__clc_vec4_fp64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t __spirv_ocl_erf(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_erf(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_erf(__clc_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t __spirv_ocl_erf(__clc_vec2_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t __spirv_ocl_erf(__clc_vec3_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t __spirv_ocl_erf(__clc_vec4_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t __spirv_ocl_erf(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_erf(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_erfc(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_erfc(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_erfc(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_erfc(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_erfc(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_erfc(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_erfc(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_erfc(__clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_erfc(__clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_erfc(__clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_erfc(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_erfc(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_erfc(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_erfc(__clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_erfc(__clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_erfc(__clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_erfc(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_erfc(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_exp(__clc_fp32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t __spirv_ocl_exp(__clc_vec2_fp32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t __spirv_ocl_exp(__clc_vec3_fp32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t __spirv_ocl_exp(__clc_vec4_fp32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t __spirv_ocl_exp(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_exp(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_exp(__clc_fp64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t __spirv_ocl_exp(__clc_vec2_fp64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t __spirv_ocl_exp(__clc_vec3_fp64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t __spirv_ocl_exp(__clc_vec4_fp64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t __spirv_ocl_exp(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_exp(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_exp(__clc_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t __spirv_ocl_exp(__clc_vec2_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t __spirv_ocl_exp(__clc_vec3_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t __spirv_ocl_exp(__clc_vec4_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t __spirv_ocl_exp(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_exp(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_exp10(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_exp10(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_exp10(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_exp10(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_exp10(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_exp10(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_exp10(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_exp10(__clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_exp10(__clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_exp10(__clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_exp10(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_exp10(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_exp10(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_exp10(__clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_exp10(__clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_exp10(__clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_exp10(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_exp10(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_exp2(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_exp2(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_exp2(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_exp2(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_exp2(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_exp2(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_exp2(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_exp2(__clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_exp2(__clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_exp2(__clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_exp2(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_exp2(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_exp2(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_exp2(__clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_exp2(__clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_exp2(__clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_exp2(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_exp2(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_expm1(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_expm1(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_expm1(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_expm1(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_expm1(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_expm1(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_expm1(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_expm1(__clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_expm1(__clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_expm1(__clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_expm1(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_expm1(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_expm1(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_expm1(__clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_expm1(__clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_expm1(__clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_expm1(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_expm1(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_fabs(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_fabs(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_fabs(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_fabs(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_fabs(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_fabs(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_fabs(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_fabs(__clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_fabs(__clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_fabs(__clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_fabs(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_fabs(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_fabs(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_fabs(__clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_fabs(__clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_fabs(__clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_fabs(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_fabs(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_fast_distance(__clc_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_fast_distance(__clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_fast_distance(__clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_fast_distance(__clc_vec4_fp32_t, __clc_vec4_fp32_t); + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_fast_length(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_fast_length(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_fast_length(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_fast_length(__clc_vec4_fp32_t); + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_fast_normalize(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_fast_normalize(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_fast_normalize(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_fast_normalize(__clc_vec4_fp32_t); + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_fclamp(__clc_fp32_t, __clc_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_fclamp(__clc_vec2_fp32_t, __clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_fclamp(__clc_vec3_fp32_t, __clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_fclamp(__clc_vec4_fp32_t, __clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_fclamp(__clc_vec8_fp32_t, __clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t __spirv_ocl_fclamp( + __clc_vec16_fp32_t, __clc_vec16_fp32_t, __clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t + __spirv_ocl_fclamp(__clc_fp64_t, __clc_fp64_t, __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_fclamp(__clc_vec2_fp64_t, __clc_vec2_fp64_t, __clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_fclamp(__clc_vec3_fp64_t, __clc_vec3_fp64_t, __clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_fclamp(__clc_vec4_fp64_t, __clc_vec4_fp64_t, __clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_fclamp(__clc_vec8_fp64_t, __clc_vec8_fp64_t, __clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t __spirv_ocl_fclamp( + __clc_vec16_fp64_t, __clc_vec16_fp64_t, __clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t + __spirv_ocl_fclamp(__clc_fp16_t, __clc_fp16_t, __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_fclamp(__clc_vec2_fp16_t, __clc_vec2_fp16_t, __clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_fclamp(__clc_vec3_fp16_t, __clc_vec3_fp16_t, __clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_fclamp(__clc_vec4_fp16_t, __clc_vec4_fp16_t, __clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_fclamp(__clc_vec8_fp16_t, __clc_vec8_fp16_t, __clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t __spirv_ocl_fclamp( + __clc_vec16_fp16_t, __clc_vec16_fp16_t, __clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_fdim(__clc_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_fdim(__clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_fdim(__clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_fdim(__clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_fdim(__clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_fdim(__clc_vec16_fp32_t, __clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t + __spirv_ocl_fdim(__clc_fp64_t, __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_fdim(__clc_vec2_fp64_t, __clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_fdim(__clc_vec3_fp64_t, __clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_fdim(__clc_vec4_fp64_t, __clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_fdim(__clc_vec8_fp64_t, __clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_fdim(__clc_vec16_fp64_t, __clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t + __spirv_ocl_fdim(__clc_fp16_t, __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_fdim(__clc_vec2_fp16_t, __clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_fdim(__clc_vec3_fp16_t, __clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_fdim(__clc_vec4_fp16_t, __clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_fdim(__clc_vec8_fp16_t, __clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_fdim(__clc_vec16_fp16_t, __clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_floor(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_floor(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_floor(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_floor(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_floor(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_floor(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_floor(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_floor(__clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_floor(__clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_floor(__clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_floor(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_floor(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_floor(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_floor(__clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_floor(__clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_floor(__clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_floor(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_floor(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_fma(__clc_fp32_t, + __clc_fp32_t, + __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_fma(__clc_vec2_fp32_t, __clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_fma(__clc_vec3_fp32_t, __clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_fma(__clc_vec4_fp32_t, __clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_fma(__clc_vec8_fp32_t, __clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_fma(__clc_vec16_fp32_t, __clc_vec16_fp32_t, __clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_fma(__clc_fp64_t, + __clc_fp64_t, + __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_fma(__clc_vec2_fp64_t, __clc_vec2_fp64_t, __clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_fma(__clc_vec3_fp64_t, __clc_vec3_fp64_t, __clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_fma(__clc_vec4_fp64_t, __clc_vec4_fp64_t, __clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_fma(__clc_vec8_fp64_t, __clc_vec8_fp64_t, __clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_fma(__clc_vec16_fp64_t, __clc_vec16_fp64_t, __clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_fma(__clc_fp16_t, + __clc_fp16_t, + __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_fma(__clc_vec2_fp16_t, __clc_vec2_fp16_t, __clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_fma(__clc_vec3_fp16_t, __clc_vec3_fp16_t, __clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_fma(__clc_vec4_fp16_t, __clc_vec4_fp16_t, __clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_fma(__clc_vec8_fp16_t, __clc_vec8_fp16_t, __clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_fma(__clc_vec16_fp16_t, __clc_vec16_fp16_t, __clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_fmax(__clc_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_fmax(__clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_fmax(__clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_fmax(__clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_fmax(__clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_fmax(__clc_vec16_fp32_t, __clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t + __spirv_ocl_fmax(__clc_fp64_t, __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_fmax(__clc_vec2_fp64_t, __clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_fmax(__clc_vec3_fp64_t, __clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_fmax(__clc_vec4_fp64_t, __clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_fmax(__clc_vec8_fp64_t, __clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_fmax(__clc_vec16_fp64_t, __clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t + __spirv_ocl_fmax(__clc_fp16_t, __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_fmax(__clc_vec2_fp16_t, __clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_fmax(__clc_vec3_fp16_t, __clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_fmax(__clc_vec4_fp16_t, __clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_fmax(__clc_vec8_fp16_t, __clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_fmax(__clc_vec16_fp16_t, __clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_fmax_common(__clc_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_fmax_common(__clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_fmax_common(__clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_fmax_common(__clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_fmax_common(__clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_fmax_common(__clc_vec16_fp32_t, __clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t + __spirv_ocl_fmax_common(__clc_fp64_t, __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_fmax_common(__clc_vec2_fp64_t, __clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_fmax_common(__clc_vec3_fp64_t, __clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_fmax_common(__clc_vec4_fp64_t, __clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_fmax_common(__clc_vec8_fp64_t, __clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_fmax_common(__clc_vec16_fp64_t, __clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t + __spirv_ocl_fmax_common(__clc_fp16_t, __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_fmax_common(__clc_vec2_fp16_t, __clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_fmax_common(__clc_vec3_fp16_t, __clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_fmax_common(__clc_vec4_fp16_t, __clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_fmax_common(__clc_vec8_fp16_t, __clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_fmax_common(__clc_vec16_fp16_t, __clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_fmin(__clc_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_fmin(__clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_fmin(__clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_fmin(__clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_fmin(__clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_fmin(__clc_vec16_fp32_t, __clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t + __spirv_ocl_fmin(__clc_fp64_t, __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_fmin(__clc_vec2_fp64_t, __clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_fmin(__clc_vec3_fp64_t, __clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_fmin(__clc_vec4_fp64_t, __clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_fmin(__clc_vec8_fp64_t, __clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_fmin(__clc_vec16_fp64_t, __clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t + __spirv_ocl_fmin(__clc_fp16_t, __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_fmin(__clc_vec2_fp16_t, __clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_fmin(__clc_vec3_fp16_t, __clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_fmin(__clc_vec4_fp16_t, __clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_fmin(__clc_vec8_fp16_t, __clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_fmin(__clc_vec16_fp16_t, __clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_fmin_common(__clc_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_fmin_common(__clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_fmin_common(__clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_fmin_common(__clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_fmin_common(__clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_fmin_common(__clc_vec16_fp32_t, __clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t + __spirv_ocl_fmin_common(__clc_fp64_t, __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_fmin_common(__clc_vec2_fp64_t, __clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_fmin_common(__clc_vec3_fp64_t, __clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_fmin_common(__clc_vec4_fp64_t, __clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_fmin_common(__clc_vec8_fp64_t, __clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_fmin_common(__clc_vec16_fp64_t, __clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t + __spirv_ocl_fmin_common(__clc_fp16_t, __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_fmin_common(__clc_vec2_fp16_t, __clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_fmin_common(__clc_vec3_fp16_t, __clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_fmin_common(__clc_vec4_fp16_t, __clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_fmin_common(__clc_vec8_fp16_t, __clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_fmin_common(__clc_vec16_fp16_t, __clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_fmod(__clc_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_fmod(__clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_fmod(__clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_fmod(__clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_fmod(__clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_fmod(__clc_vec16_fp32_t, __clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t + __spirv_ocl_fmod(__clc_fp64_t, __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_fmod(__clc_vec2_fp64_t, __clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_fmod(__clc_vec3_fp64_t, __clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_fmod(__clc_vec4_fp64_t, __clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_fmod(__clc_vec8_fp64_t, __clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_fmod(__clc_vec16_fp64_t, __clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t + __spirv_ocl_fmod(__clc_fp16_t, __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_fmod(__clc_vec2_fp16_t, __clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_fmod(__clc_vec3_fp16_t, __clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_fmod(__clc_vec4_fp16_t, __clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_fmod(__clc_vec8_fp16_t, __clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_fmod(__clc_vec16_fp16_t, __clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL __clc_fp32_t __spirv_ocl_fract(__clc_fp32_t, + __clc_fp32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_fp32_t __spirv_ocl_fract(__clc_fp32_t, + __clc_fp32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_fp32_t __spirv_ocl_fract(__clc_fp32_t, + __clc_fp32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp32_t +__spirv_ocl_fract(__clc_vec2_fp32_t, __clc_vec2_fp32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp32_t +__spirv_ocl_fract(__clc_vec2_fp32_t, __clc_vec2_fp32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp32_t +__spirv_ocl_fract(__clc_vec2_fp32_t, __clc_vec2_fp32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp32_t +__spirv_ocl_fract(__clc_vec3_fp32_t, __clc_vec3_fp32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp32_t +__spirv_ocl_fract(__clc_vec3_fp32_t, __clc_vec3_fp32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp32_t +__spirv_ocl_fract(__clc_vec3_fp32_t, __clc_vec3_fp32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp32_t +__spirv_ocl_fract(__clc_vec4_fp32_t, __clc_vec4_fp32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp32_t +__spirv_ocl_fract(__clc_vec4_fp32_t, __clc_vec4_fp32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp32_t +__spirv_ocl_fract(__clc_vec4_fp32_t, __clc_vec4_fp32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp32_t +__spirv_ocl_fract(__clc_vec8_fp32_t, __clc_vec8_fp32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp32_t +__spirv_ocl_fract(__clc_vec8_fp32_t, __clc_vec8_fp32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp32_t +__spirv_ocl_fract(__clc_vec8_fp32_t, __clc_vec8_fp32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp32_t +__spirv_ocl_fract(__clc_vec16_fp32_t, __clc_vec16_fp32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp32_t +__spirv_ocl_fract(__clc_vec16_fp32_t, __clc_vec16_fp32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp32_t +__spirv_ocl_fract(__clc_vec16_fp32_t, __clc_vec16_fp32_t __global *); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL __clc_fp64_t __spirv_ocl_fract(__clc_fp64_t, + __clc_fp64_t *); +_CLC_OVERLOAD _CLC_DECL __clc_fp64_t __spirv_ocl_fract(__clc_fp64_t, + __clc_fp64_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_fp64_t __spirv_ocl_fract(__clc_fp64_t, + __clc_fp64_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp64_t +__spirv_ocl_fract(__clc_vec2_fp64_t, __clc_vec2_fp64_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp64_t +__spirv_ocl_fract(__clc_vec2_fp64_t, __clc_vec2_fp64_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp64_t +__spirv_ocl_fract(__clc_vec2_fp64_t, __clc_vec2_fp64_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp64_t +__spirv_ocl_fract(__clc_vec3_fp64_t, __clc_vec3_fp64_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp64_t +__spirv_ocl_fract(__clc_vec3_fp64_t, __clc_vec3_fp64_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp64_t +__spirv_ocl_fract(__clc_vec3_fp64_t, __clc_vec3_fp64_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp64_t +__spirv_ocl_fract(__clc_vec4_fp64_t, __clc_vec4_fp64_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp64_t +__spirv_ocl_fract(__clc_vec4_fp64_t, __clc_vec4_fp64_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp64_t +__spirv_ocl_fract(__clc_vec4_fp64_t, __clc_vec4_fp64_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp64_t +__spirv_ocl_fract(__clc_vec8_fp64_t, __clc_vec8_fp64_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp64_t +__spirv_ocl_fract(__clc_vec8_fp64_t, __clc_vec8_fp64_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp64_t +__spirv_ocl_fract(__clc_vec8_fp64_t, __clc_vec8_fp64_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp64_t +__spirv_ocl_fract(__clc_vec16_fp64_t, __clc_vec16_fp64_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp64_t +__spirv_ocl_fract(__clc_vec16_fp64_t, __clc_vec16_fp64_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp64_t +__spirv_ocl_fract(__clc_vec16_fp64_t, __clc_vec16_fp64_t __global *); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL __clc_fp16_t __spirv_ocl_fract(__clc_fp16_t, + __clc_fp16_t *); +_CLC_OVERLOAD _CLC_DECL __clc_fp16_t __spirv_ocl_fract(__clc_fp16_t, + __clc_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_fp16_t __spirv_ocl_fract(__clc_fp16_t, + __clc_fp16_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp16_t +__spirv_ocl_fract(__clc_vec2_fp16_t, __clc_vec2_fp16_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp16_t +__spirv_ocl_fract(__clc_vec2_fp16_t, __clc_vec2_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp16_t +__spirv_ocl_fract(__clc_vec2_fp16_t, __clc_vec2_fp16_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp16_t +__spirv_ocl_fract(__clc_vec3_fp16_t, __clc_vec3_fp16_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp16_t +__spirv_ocl_fract(__clc_vec3_fp16_t, __clc_vec3_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp16_t +__spirv_ocl_fract(__clc_vec3_fp16_t, __clc_vec3_fp16_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp16_t +__spirv_ocl_fract(__clc_vec4_fp16_t, __clc_vec4_fp16_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp16_t +__spirv_ocl_fract(__clc_vec4_fp16_t, __clc_vec4_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp16_t +__spirv_ocl_fract(__clc_vec4_fp16_t, __clc_vec4_fp16_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp16_t +__spirv_ocl_fract(__clc_vec8_fp16_t, __clc_vec8_fp16_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp16_t +__spirv_ocl_fract(__clc_vec8_fp16_t, __clc_vec8_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp16_t +__spirv_ocl_fract(__clc_vec8_fp16_t, __clc_vec8_fp16_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp16_t +__spirv_ocl_fract(__clc_vec16_fp16_t, __clc_vec16_fp16_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp16_t +__spirv_ocl_fract(__clc_vec16_fp16_t, __clc_vec16_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp16_t +__spirv_ocl_fract(__clc_vec16_fp16_t, __clc_vec16_fp16_t __global *); +#endif + +_CLC_OVERLOAD _CLC_DECL __clc_fp32_t __spirv_ocl_frexp(__clc_fp32_t, + __clc_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_fp32_t __spirv_ocl_frexp(__clc_fp32_t, + __clc_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_fp32_t +__spirv_ocl_frexp(__clc_fp32_t, __clc_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp32_t +__spirv_ocl_frexp(__clc_vec2_fp32_t, __clc_vec2_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp32_t +__spirv_ocl_frexp(__clc_vec2_fp32_t, __clc_vec2_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp32_t +__spirv_ocl_frexp(__clc_vec2_fp32_t, __clc_vec2_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp32_t +__spirv_ocl_frexp(__clc_vec3_fp32_t, __clc_vec3_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp32_t +__spirv_ocl_frexp(__clc_vec3_fp32_t, __clc_vec3_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp32_t +__spirv_ocl_frexp(__clc_vec3_fp32_t, __clc_vec3_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp32_t +__spirv_ocl_frexp(__clc_vec4_fp32_t, __clc_vec4_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp32_t +__spirv_ocl_frexp(__clc_vec4_fp32_t, __clc_vec4_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp32_t +__spirv_ocl_frexp(__clc_vec4_fp32_t, __clc_vec4_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp32_t +__spirv_ocl_frexp(__clc_vec8_fp32_t, __clc_vec8_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp32_t +__spirv_ocl_frexp(__clc_vec8_fp32_t, __clc_vec8_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp32_t +__spirv_ocl_frexp(__clc_vec8_fp32_t, __clc_vec8_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp32_t +__spirv_ocl_frexp(__clc_vec16_fp32_t, __clc_vec16_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp32_t +__spirv_ocl_frexp(__clc_vec16_fp32_t, __clc_vec16_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp32_t +__spirv_ocl_frexp(__clc_vec16_fp32_t, __clc_vec16_int32_t __global *); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL __clc_fp64_t __spirv_ocl_frexp(__clc_fp64_t, + __clc_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_fp64_t __spirv_ocl_frexp(__clc_fp64_t, + __clc_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_fp64_t +__spirv_ocl_frexp(__clc_fp64_t, __clc_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp64_t +__spirv_ocl_frexp(__clc_vec2_fp64_t, __clc_vec2_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp64_t +__spirv_ocl_frexp(__clc_vec2_fp64_t, __clc_vec2_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp64_t +__spirv_ocl_frexp(__clc_vec2_fp64_t, __clc_vec2_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp64_t +__spirv_ocl_frexp(__clc_vec3_fp64_t, __clc_vec3_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp64_t +__spirv_ocl_frexp(__clc_vec3_fp64_t, __clc_vec3_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp64_t +__spirv_ocl_frexp(__clc_vec3_fp64_t, __clc_vec3_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp64_t +__spirv_ocl_frexp(__clc_vec4_fp64_t, __clc_vec4_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp64_t +__spirv_ocl_frexp(__clc_vec4_fp64_t, __clc_vec4_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp64_t +__spirv_ocl_frexp(__clc_vec4_fp64_t, __clc_vec4_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp64_t +__spirv_ocl_frexp(__clc_vec8_fp64_t, __clc_vec8_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp64_t +__spirv_ocl_frexp(__clc_vec8_fp64_t, __clc_vec8_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp64_t +__spirv_ocl_frexp(__clc_vec8_fp64_t, __clc_vec8_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp64_t +__spirv_ocl_frexp(__clc_vec16_fp64_t, __clc_vec16_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp64_t +__spirv_ocl_frexp(__clc_vec16_fp64_t, __clc_vec16_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp64_t +__spirv_ocl_frexp(__clc_vec16_fp64_t, __clc_vec16_int32_t __global *); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL __clc_fp16_t __spirv_ocl_frexp(__clc_fp16_t, + __clc_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_fp16_t __spirv_ocl_frexp(__clc_fp16_t, + __clc_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_fp16_t +__spirv_ocl_frexp(__clc_fp16_t, __clc_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp16_t +__spirv_ocl_frexp(__clc_vec2_fp16_t, __clc_vec2_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp16_t +__spirv_ocl_frexp(__clc_vec2_fp16_t, __clc_vec2_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp16_t +__spirv_ocl_frexp(__clc_vec2_fp16_t, __clc_vec2_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp16_t +__spirv_ocl_frexp(__clc_vec3_fp16_t, __clc_vec3_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp16_t +__spirv_ocl_frexp(__clc_vec3_fp16_t, __clc_vec3_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp16_t +__spirv_ocl_frexp(__clc_vec3_fp16_t, __clc_vec3_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp16_t +__spirv_ocl_frexp(__clc_vec4_fp16_t, __clc_vec4_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp16_t +__spirv_ocl_frexp(__clc_vec4_fp16_t, __clc_vec4_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp16_t +__spirv_ocl_frexp(__clc_vec4_fp16_t, __clc_vec4_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp16_t +__spirv_ocl_frexp(__clc_vec8_fp16_t, __clc_vec8_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp16_t +__spirv_ocl_frexp(__clc_vec8_fp16_t, __clc_vec8_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp16_t +__spirv_ocl_frexp(__clc_vec8_fp16_t, __clc_vec8_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp16_t +__spirv_ocl_frexp(__clc_vec16_fp16_t, __clc_vec16_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp16_t +__spirv_ocl_frexp(__clc_vec16_fp16_t, __clc_vec16_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp16_t +__spirv_ocl_frexp(__clc_vec16_fp16_t, __clc_vec16_int32_t __global *); +#endif + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_half_cos(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_half_cos(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_half_cos(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_half_cos(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_half_cos(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_half_cos(__clc_vec16_fp32_t); + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_half_divide(__clc_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_half_divide(__clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_half_divide(__clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_half_divide(__clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_half_divide(__clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_half_divide(__clc_vec16_fp32_t, __clc_vec16_fp32_t); + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_half_exp(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_half_exp(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_half_exp(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_half_exp(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_half_exp(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_half_exp(__clc_vec16_fp32_t); + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_half_exp10(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_half_exp10(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_half_exp10(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_half_exp10(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_half_exp10(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_half_exp10(__clc_vec16_fp32_t); + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_half_exp2(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_half_exp2(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_half_exp2(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_half_exp2(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_half_exp2(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_half_exp2(__clc_vec16_fp32_t); + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_half_log(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_half_log(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_half_log(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_half_log(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_half_log(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_half_log(__clc_vec16_fp32_t); + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_half_log10(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_half_log10(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_half_log10(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_half_log10(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_half_log10(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_half_log10(__clc_vec16_fp32_t); + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_half_log2(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_half_log2(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_half_log2(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_half_log2(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_half_log2(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_half_log2(__clc_vec16_fp32_t); + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_half_powr(__clc_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_half_powr(__clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_half_powr(__clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_half_powr(__clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_half_powr(__clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_half_powr(__clc_vec16_fp32_t, __clc_vec16_fp32_t); + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_half_recip(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_half_recip(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_half_recip(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_half_recip(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_half_recip(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_half_recip(__clc_vec16_fp32_t); + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_half_rsqrt(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_half_rsqrt(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_half_rsqrt(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_half_rsqrt(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_half_rsqrt(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_half_rsqrt(__clc_vec16_fp32_t); + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_half_sin(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_half_sin(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_half_sin(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_half_sin(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_half_sin(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_half_sin(__clc_vec16_fp32_t); + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_half_sqrt(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_half_sqrt(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_half_sqrt(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_half_sqrt(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_half_sqrt(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_half_sqrt(__clc_vec16_fp32_t); + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_half_tan(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_half_tan(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_half_tan(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_half_tan(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_half_tan(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_half_tan(__clc_vec16_fp32_t); + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_hypot(__clc_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_hypot(__clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_hypot(__clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_hypot(__clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_hypot(__clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_hypot(__clc_vec16_fp32_t, __clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t + __spirv_ocl_hypot(__clc_fp64_t, __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_hypot(__clc_vec2_fp64_t, __clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_hypot(__clc_vec3_fp64_t, __clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_hypot(__clc_vec4_fp64_t, __clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_hypot(__clc_vec8_fp64_t, __clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_hypot(__clc_vec16_fp64_t, __clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t + __spirv_ocl_hypot(__clc_fp16_t, __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_hypot(__clc_vec2_fp16_t, __clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_hypot(__clc_vec3_fp16_t, __clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_hypot(__clc_vec4_fp16_t, __clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_hypot(__clc_vec8_fp16_t, __clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_hypot(__clc_vec16_fp16_t, __clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_int32_t __spirv_ocl_ilogb(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int32_t + __spirv_ocl_ilogb(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int32_t + __spirv_ocl_ilogb(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int32_t + __spirv_ocl_ilogb(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int32_t + __spirv_ocl_ilogb(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int32_t + __spirv_ocl_ilogb(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_int32_t __spirv_ocl_ilogb(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int32_t + __spirv_ocl_ilogb(__clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int32_t + __spirv_ocl_ilogb(__clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int32_t + __spirv_ocl_ilogb(__clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int32_t + __spirv_ocl_ilogb(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int32_t + __spirv_ocl_ilogb(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_int32_t __spirv_ocl_ilogb(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int32_t + __spirv_ocl_ilogb(__clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int32_t + __spirv_ocl_ilogb(__clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int32_t + __spirv_ocl_ilogb(__clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int32_t + __spirv_ocl_ilogb(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int32_t + __spirv_ocl_ilogb(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_ldexp(__clc_fp32_t, __clc_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_ldexp(__clc_fp32_t, __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_ldexp(__clc_vec2_fp32_t, __clc_vec2_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_ldexp(__clc_vec2_fp32_t, __clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_ldexp(__clc_vec3_fp32_t, __clc_vec3_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_ldexp(__clc_vec3_fp32_t, __clc_vec3_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_ldexp(__clc_vec4_fp32_t, __clc_vec4_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_ldexp(__clc_vec4_fp32_t, __clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_ldexp(__clc_vec8_fp32_t, __clc_vec8_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_ldexp(__clc_vec8_fp32_t, __clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_ldexp(__clc_vec16_fp32_t, __clc_vec16_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_ldexp(__clc_vec16_fp32_t, __clc_vec16_uint32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t + __spirv_ocl_ldexp(__clc_fp64_t, __clc_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t + __spirv_ocl_ldexp(__clc_fp64_t, __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_ldexp(__clc_vec2_fp64_t, __clc_vec2_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_ldexp(__clc_vec2_fp64_t, __clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_ldexp(__clc_vec3_fp64_t, __clc_vec3_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_ldexp(__clc_vec3_fp64_t, __clc_vec3_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_ldexp(__clc_vec4_fp64_t, __clc_vec4_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_ldexp(__clc_vec4_fp64_t, __clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_ldexp(__clc_vec8_fp64_t, __clc_vec8_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_ldexp(__clc_vec8_fp64_t, __clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_ldexp(__clc_vec16_fp64_t, __clc_vec16_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_ldexp(__clc_vec16_fp64_t, __clc_vec16_uint32_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t + __spirv_ocl_ldexp(__clc_fp16_t, __clc_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t + __spirv_ocl_ldexp(__clc_fp16_t, __clc_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_ldexp(__clc_vec2_fp16_t, __clc_vec2_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_ldexp(__clc_vec2_fp16_t, __clc_vec2_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_ldexp(__clc_vec3_fp16_t, __clc_vec3_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_ldexp(__clc_vec3_fp16_t, __clc_vec3_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_ldexp(__clc_vec4_fp16_t, __clc_vec4_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_ldexp(__clc_vec4_fp16_t, __clc_vec4_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_ldexp(__clc_vec8_fp16_t, __clc_vec8_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_ldexp(__clc_vec8_fp16_t, __clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_ldexp(__clc_vec16_fp16_t, __clc_vec16_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_ldexp(__clc_vec16_fp16_t, __clc_vec16_uint32_t); +#endif + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_length(__clc_fp32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_length(__clc_vec2_fp32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_length(__clc_vec3_fp32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_length(__clc_vec4_fp32_t); #ifdef cl_khr_fp64 -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t - __spirv_ocl_bitselect(__clc_fp64_t, __clc_fp64_t, __clc_fp64_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t __spirv_ocl_bitselect( - __clc_vec2_fp64_t, __clc_vec2_fp64_t, __clc_vec2_fp64_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t __spirv_ocl_bitselect( - __clc_vec3_fp64_t, __clc_vec3_fp64_t, __clc_vec3_fp64_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t __spirv_ocl_bitselect( - __clc_vec4_fp64_t, __clc_vec4_fp64_t, __clc_vec4_fp64_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t __spirv_ocl_bitselect( - __clc_vec8_fp64_t, __clc_vec8_fp64_t, __clc_vec8_fp64_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t __spirv_ocl_bitselect( - __clc_vec16_fp64_t, __clc_vec16_fp64_t, __clc_vec16_fp64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_length(__clc_fp64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_length(__clc_vec2_fp64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_length(__clc_vec3_fp64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_length(__clc_vec4_fp64_t); #endif #ifdef cl_khr_fp16 -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t - __spirv_ocl_bitselect(__clc_fp16_t, __clc_fp16_t, __clc_fp16_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t __spirv_ocl_bitselect( - __clc_vec2_fp16_t, __clc_vec2_fp16_t, __clc_vec2_fp16_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t __spirv_ocl_bitselect( - __clc_vec3_fp16_t, __clc_vec3_fp16_t, __clc_vec3_fp16_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t __spirv_ocl_bitselect( - __clc_vec4_fp16_t, __clc_vec4_fp16_t, __clc_vec4_fp16_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t __spirv_ocl_bitselect( - __clc_vec8_fp16_t, __clc_vec8_fp16_t, __clc_vec8_fp16_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t __spirv_ocl_bitselect( - __clc_vec16_fp16_t, __clc_vec16_fp16_t, __clc_vec16_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_length(__clc_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_length(__clc_vec2_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_length(__clc_vec3_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_length(__clc_vec4_fp16_t); #endif -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_char_t __spirv_ocl_clz(__clc_char_t); _CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_vec2_char_t __spirv_ocl_clz(__clc_vec2_char_t); +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_lgamma(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_lgamma(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_lgamma(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_lgamma(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_lgamma(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_lgamma(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 _CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_vec3_char_t __spirv_ocl_clz(__clc_vec3_char_t); +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_lgamma(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_lgamma(__clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_lgamma(__clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_lgamma(__clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_lgamma(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_lgamma(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 _CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_vec4_char_t __spirv_ocl_clz(__clc_vec4_char_t); +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_lgamma(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_lgamma(__clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_lgamma(__clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_lgamma(__clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_lgamma(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_lgamma(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL __clc_fp32_t __spirv_ocl_lgamma_r(__clc_fp32_t, + __clc_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_fp32_t +__spirv_ocl_lgamma_r(__clc_fp32_t, __clc_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_fp32_t +__spirv_ocl_lgamma_r(__clc_fp32_t, __clc_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp32_t +__spirv_ocl_lgamma_r(__clc_vec2_fp32_t, __clc_vec2_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp32_t +__spirv_ocl_lgamma_r(__clc_vec2_fp32_t, __clc_vec2_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp32_t +__spirv_ocl_lgamma_r(__clc_vec2_fp32_t, __clc_vec2_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp32_t +__spirv_ocl_lgamma_r(__clc_vec3_fp32_t, __clc_vec3_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp32_t +__spirv_ocl_lgamma_r(__clc_vec3_fp32_t, __clc_vec3_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp32_t +__spirv_ocl_lgamma_r(__clc_vec3_fp32_t, __clc_vec3_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp32_t +__spirv_ocl_lgamma_r(__clc_vec4_fp32_t, __clc_vec4_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp32_t +__spirv_ocl_lgamma_r(__clc_vec4_fp32_t, __clc_vec4_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp32_t +__spirv_ocl_lgamma_r(__clc_vec4_fp32_t, __clc_vec4_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp32_t +__spirv_ocl_lgamma_r(__clc_vec8_fp32_t, __clc_vec8_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp32_t +__spirv_ocl_lgamma_r(__clc_vec8_fp32_t, __clc_vec8_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp32_t +__spirv_ocl_lgamma_r(__clc_vec8_fp32_t, __clc_vec8_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp32_t +__spirv_ocl_lgamma_r(__clc_vec16_fp32_t, __clc_vec16_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp32_t +__spirv_ocl_lgamma_r(__clc_vec16_fp32_t, __clc_vec16_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp32_t +__spirv_ocl_lgamma_r(__clc_vec16_fp32_t, __clc_vec16_int32_t __global *); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL __clc_fp64_t __spirv_ocl_lgamma_r(__clc_fp64_t, + __clc_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_fp64_t +__spirv_ocl_lgamma_r(__clc_fp64_t, __clc_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_fp64_t +__spirv_ocl_lgamma_r(__clc_fp64_t, __clc_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp64_t +__spirv_ocl_lgamma_r(__clc_vec2_fp64_t, __clc_vec2_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp64_t +__spirv_ocl_lgamma_r(__clc_vec2_fp64_t, __clc_vec2_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp64_t +__spirv_ocl_lgamma_r(__clc_vec2_fp64_t, __clc_vec2_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp64_t +__spirv_ocl_lgamma_r(__clc_vec3_fp64_t, __clc_vec3_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp64_t +__spirv_ocl_lgamma_r(__clc_vec3_fp64_t, __clc_vec3_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp64_t +__spirv_ocl_lgamma_r(__clc_vec3_fp64_t, __clc_vec3_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp64_t +__spirv_ocl_lgamma_r(__clc_vec4_fp64_t, __clc_vec4_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp64_t +__spirv_ocl_lgamma_r(__clc_vec4_fp64_t, __clc_vec4_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp64_t +__spirv_ocl_lgamma_r(__clc_vec4_fp64_t, __clc_vec4_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp64_t +__spirv_ocl_lgamma_r(__clc_vec8_fp64_t, __clc_vec8_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp64_t +__spirv_ocl_lgamma_r(__clc_vec8_fp64_t, __clc_vec8_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp64_t +__spirv_ocl_lgamma_r(__clc_vec8_fp64_t, __clc_vec8_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp64_t +__spirv_ocl_lgamma_r(__clc_vec16_fp64_t, __clc_vec16_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp64_t +__spirv_ocl_lgamma_r(__clc_vec16_fp64_t, __clc_vec16_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp64_t +__spirv_ocl_lgamma_r(__clc_vec16_fp64_t, __clc_vec16_int32_t __global *); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL __clc_fp16_t __spirv_ocl_lgamma_r(__clc_fp16_t, + __clc_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_fp16_t +__spirv_ocl_lgamma_r(__clc_fp16_t, __clc_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_fp16_t +__spirv_ocl_lgamma_r(__clc_fp16_t, __clc_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp16_t +__spirv_ocl_lgamma_r(__clc_vec2_fp16_t, __clc_vec2_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp16_t +__spirv_ocl_lgamma_r(__clc_vec2_fp16_t, __clc_vec2_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp16_t +__spirv_ocl_lgamma_r(__clc_vec2_fp16_t, __clc_vec2_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp16_t +__spirv_ocl_lgamma_r(__clc_vec3_fp16_t, __clc_vec3_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp16_t +__spirv_ocl_lgamma_r(__clc_vec3_fp16_t, __clc_vec3_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp16_t +__spirv_ocl_lgamma_r(__clc_vec3_fp16_t, __clc_vec3_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp16_t +__spirv_ocl_lgamma_r(__clc_vec4_fp16_t, __clc_vec4_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp16_t +__spirv_ocl_lgamma_r(__clc_vec4_fp16_t, __clc_vec4_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp16_t +__spirv_ocl_lgamma_r(__clc_vec4_fp16_t, __clc_vec4_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp16_t +__spirv_ocl_lgamma_r(__clc_vec8_fp16_t, __clc_vec8_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp16_t +__spirv_ocl_lgamma_r(__clc_vec8_fp16_t, __clc_vec8_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp16_t +__spirv_ocl_lgamma_r(__clc_vec8_fp16_t, __clc_vec8_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp16_t +__spirv_ocl_lgamma_r(__clc_vec16_fp16_t, __clc_vec16_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp16_t +__spirv_ocl_lgamma_r(__clc_vec16_fp16_t, __clc_vec16_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp16_t +__spirv_ocl_lgamma_r(__clc_vec16_fp16_t, __clc_vec16_int32_t __global *); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_log(__clc_fp32_t); _CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_vec8_char_t __spirv_ocl_clz(__clc_vec8_char_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_char_t - __spirv_ocl_clz(__clc_vec16_char_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_int8_t __spirv_ocl_clz(__clc_int8_t); +_CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t __spirv_ocl_log(__clc_vec2_fp32_t); _CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t __spirv_ocl_clz(__clc_vec2_int8_t); +_CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t __spirv_ocl_log(__clc_vec3_fp32_t); _CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t __spirv_ocl_clz(__clc_vec3_int8_t); +_CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t __spirv_ocl_log(__clc_vec4_fp32_t); _CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t __spirv_ocl_clz(__clc_vec4_int8_t); +_CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t __spirv_ocl_log(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_log(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_log(__clc_fp64_t); _CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t __spirv_ocl_clz(__clc_vec8_int8_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t - __spirv_ocl_clz(__clc_vec16_int8_t); +_CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t __spirv_ocl_log(__clc_vec2_fp64_t); _CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_int16_t __spirv_ocl_clz(__clc_int16_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int16_t - __spirv_ocl_clz(__clc_vec2_int16_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int16_t - __spirv_ocl_clz(__clc_vec3_int16_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int16_t - __spirv_ocl_clz(__clc_vec4_int16_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int16_t - __spirv_ocl_clz(__clc_vec8_int16_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int16_t - __spirv_ocl_clz(__clc_vec16_int16_t); +_CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t __spirv_ocl_log(__clc_vec3_fp64_t); _CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_int32_t __spirv_ocl_clz(__clc_int32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int32_t - __spirv_ocl_clz(__clc_vec2_int32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int32_t - __spirv_ocl_clz(__clc_vec3_int32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int32_t - __spirv_ocl_clz(__clc_vec4_int32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int32_t - __spirv_ocl_clz(__clc_vec8_int32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int32_t - __spirv_ocl_clz(__clc_vec16_int32_t); +_CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t __spirv_ocl_log(__clc_vec4_fp64_t); _CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_int64_t __spirv_ocl_clz(__clc_int64_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int64_t - __spirv_ocl_clz(__clc_vec2_int64_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int64_t - __spirv_ocl_clz(__clc_vec3_int64_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int64_t - __spirv_ocl_clz(__clc_vec4_int64_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int64_t - __spirv_ocl_clz(__clc_vec8_int64_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int64_t - __spirv_ocl_clz(__clc_vec16_int64_t); +_CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t __spirv_ocl_log(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_log(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_log(__clc_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t __spirv_ocl_log(__clc_vec2_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t __spirv_ocl_log(__clc_vec3_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t __spirv_ocl_log(__clc_vec4_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t __spirv_ocl_log(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_log(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_log10(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_log10(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_log10(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_log10(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_log10(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_log10(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_log10(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_log10(__clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_log10(__clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_log10(__clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_log10(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_log10(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_log10(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_log10(__clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_log10(__clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_log10(__clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_log10(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_log10(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_log1p(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_log1p(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_log1p(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_log1p(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_log1p(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_log1p(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_log1p(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_log1p(__clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_log1p(__clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_log1p(__clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_log1p(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_log1p(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_log1p(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_log1p(__clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_log1p(__clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_log1p(__clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_log1p(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_log1p(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_log2(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_log2(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_log2(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_log2(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_log2(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_log2(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 _CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_uint8_t __spirv_ocl_clz(__clc_uint8_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint8_t - __spirv_ocl_clz(__clc_vec2_uint8_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint8_t - __spirv_ocl_clz(__clc_vec3_uint8_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint8_t - __spirv_ocl_clz(__clc_vec4_uint8_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint8_t - __spirv_ocl_clz(__clc_vec8_uint8_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint8_t - __spirv_ocl_clz(__clc_vec16_uint8_t); +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_log2(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_log2(__clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_log2(__clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_log2(__clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_log2(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_log2(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 _CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_uint16_t __spirv_ocl_clz(__clc_uint16_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint16_t - __spirv_ocl_clz(__clc_vec2_uint16_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint16_t - __spirv_ocl_clz(__clc_vec3_uint16_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint16_t - __spirv_ocl_clz(__clc_vec4_uint16_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint16_t - __spirv_ocl_clz(__clc_vec8_uint16_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint16_t - __spirv_ocl_clz(__clc_vec16_uint16_t); +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_log2(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_log2(__clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_log2(__clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_log2(__clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_log2(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_log2(__clc_vec16_fp16_t); +#endif + _CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_uint32_t __spirv_ocl_clz(__clc_uint32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint32_t - __spirv_ocl_clz(__clc_vec2_uint32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint32_t - __spirv_ocl_clz(__clc_vec3_uint32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint32_t - __spirv_ocl_clz(__clc_vec4_uint32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint32_t - __spirv_ocl_clz(__clc_vec8_uint32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint32_t - __spirv_ocl_clz(__clc_vec16_uint32_t); +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_logb(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_logb(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_logb(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_logb(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_logb(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_logb(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 _CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_uint64_t __spirv_ocl_clz(__clc_uint64_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint64_t - __spirv_ocl_clz(__clc_vec2_uint64_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint64_t - __spirv_ocl_clz(__clc_vec3_uint64_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint64_t - __spirv_ocl_clz(__clc_vec4_uint64_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint64_t - __spirv_ocl_clz(__clc_vec8_uint64_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint64_t - __spirv_ocl_clz(__clc_vec16_uint64_t); +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_logb(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_logb(__clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_logb(__clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_logb(__clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_logb(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_logb(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_logb(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_logb(__clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_logb(__clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_logb(__clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_logb(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_logb(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_mad(__clc_fp32_t, + __clc_fp32_t, + __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_mad(__clc_vec2_fp32_t, __clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_mad(__clc_vec3_fp32_t, __clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_mad(__clc_vec4_fp32_t, __clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_mad(__clc_vec8_fp32_t, __clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_mad(__clc_vec16_fp32_t, __clc_vec16_fp32_t, __clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_mad(__clc_fp64_t, + __clc_fp64_t, + __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_mad(__clc_vec2_fp64_t, __clc_vec2_fp64_t, __clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_mad(__clc_vec3_fp64_t, __clc_vec3_fp64_t, __clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_mad(__clc_vec4_fp64_t, __clc_vec4_fp64_t, __clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_mad(__clc_vec8_fp64_t, __clc_vec8_fp64_t, __clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_mad(__clc_vec16_fp64_t, __clc_vec16_fp64_t, __clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_mad(__clc_fp16_t, + __clc_fp16_t, + __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_mad(__clc_vec2_fp16_t, __clc_vec2_fp16_t, __clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_mad(__clc_vec3_fp16_t, __clc_vec3_fp16_t, __clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_mad(__clc_vec4_fp16_t, __clc_vec4_fp16_t, __clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_mad(__clc_vec8_fp16_t, __clc_vec8_fp16_t, __clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_mad(__clc_vec16_fp16_t, __clc_vec16_fp16_t, __clc_vec16_fp16_t); +#endif _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t - __spirv_ocl_copysign(__clc_fp32_t, __clc_fp32_t); + __spirv_ocl_maxmag(__clc_fp32_t, __clc_fp32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t - __spirv_ocl_copysign(__clc_vec2_fp32_t, __clc_vec2_fp32_t); + __spirv_ocl_maxmag(__clc_vec2_fp32_t, __clc_vec2_fp32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t - __spirv_ocl_copysign(__clc_vec3_fp32_t, __clc_vec3_fp32_t); + __spirv_ocl_maxmag(__clc_vec3_fp32_t, __clc_vec3_fp32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t - __spirv_ocl_copysign(__clc_vec4_fp32_t, __clc_vec4_fp32_t); + __spirv_ocl_maxmag(__clc_vec4_fp32_t, __clc_vec4_fp32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t - __spirv_ocl_copysign(__clc_vec8_fp32_t, __clc_vec8_fp32_t); + __spirv_ocl_maxmag(__clc_vec8_fp32_t, __clc_vec8_fp32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t - __spirv_ocl_copysign(__clc_vec16_fp32_t, __clc_vec16_fp32_t); + __spirv_ocl_maxmag(__clc_vec16_fp32_t, __clc_vec16_fp32_t); #ifdef cl_khr_fp64 _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t - __spirv_ocl_copysign(__clc_fp64_t, __clc_fp64_t); + __spirv_ocl_maxmag(__clc_fp64_t, __clc_fp64_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t - __spirv_ocl_copysign(__clc_vec2_fp64_t, __clc_vec2_fp64_t); + __spirv_ocl_maxmag(__clc_vec2_fp64_t, __clc_vec2_fp64_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t - __spirv_ocl_copysign(__clc_vec3_fp64_t, __clc_vec3_fp64_t); + __spirv_ocl_maxmag(__clc_vec3_fp64_t, __clc_vec3_fp64_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t - __spirv_ocl_copysign(__clc_vec4_fp64_t, __clc_vec4_fp64_t); + __spirv_ocl_maxmag(__clc_vec4_fp64_t, __clc_vec4_fp64_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t - __spirv_ocl_copysign(__clc_vec8_fp64_t, __clc_vec8_fp64_t); + __spirv_ocl_maxmag(__clc_vec8_fp64_t, __clc_vec8_fp64_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t - __spirv_ocl_copysign(__clc_vec16_fp64_t, __clc_vec16_fp64_t); + __spirv_ocl_maxmag(__clc_vec16_fp64_t, __clc_vec16_fp64_t); #endif #ifdef cl_khr_fp16 _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t - __spirv_ocl_copysign(__clc_fp16_t, __clc_fp16_t); + __spirv_ocl_maxmag(__clc_fp16_t, __clc_fp16_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t - __spirv_ocl_copysign(__clc_vec2_fp16_t, __clc_vec2_fp16_t); + __spirv_ocl_maxmag(__clc_vec2_fp16_t, __clc_vec2_fp16_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t - __spirv_ocl_copysign(__clc_vec3_fp16_t, __clc_vec3_fp16_t); + __spirv_ocl_maxmag(__clc_vec3_fp16_t, __clc_vec3_fp16_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t - __spirv_ocl_copysign(__clc_vec4_fp16_t, __clc_vec4_fp16_t); + __spirv_ocl_maxmag(__clc_vec4_fp16_t, __clc_vec4_fp16_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t - __spirv_ocl_copysign(__clc_vec8_fp16_t, __clc_vec8_fp16_t); + __spirv_ocl_maxmag(__clc_vec8_fp16_t, __clc_vec8_fp16_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t - __spirv_ocl_copysign(__clc_vec16_fp16_t, __clc_vec16_fp16_t); + __spirv_ocl_maxmag(__clc_vec16_fp16_t, __clc_vec16_fp16_t); #endif +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_minmag(__clc_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_minmag(__clc_vec2_fp32_t, __clc_vec2_fp32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t - __spirv_ocl_cross(__clc_vec3_fp32_t, __clc_vec3_fp32_t); + __spirv_ocl_minmag(__clc_vec3_fp32_t, __clc_vec3_fp32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t - __spirv_ocl_cross(__clc_vec4_fp32_t, __clc_vec4_fp32_t); + __spirv_ocl_minmag(__clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_minmag(__clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_minmag(__clc_vec16_fp32_t, __clc_vec16_fp32_t); #ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t + __spirv_ocl_minmag(__clc_fp64_t, __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_minmag(__clc_vec2_fp64_t, __clc_vec2_fp64_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t - __spirv_ocl_cross(__clc_vec3_fp64_t, __clc_vec3_fp64_t); + __spirv_ocl_minmag(__clc_vec3_fp64_t, __clc_vec3_fp64_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t - __spirv_ocl_cross(__clc_vec4_fp64_t, __clc_vec4_fp64_t); + __spirv_ocl_minmag(__clc_vec4_fp64_t, __clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_minmag(__clc_vec8_fp64_t, __clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_minmag(__clc_vec16_fp64_t, __clc_vec16_fp64_t); #endif #ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t + __spirv_ocl_minmag(__clc_fp16_t, __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_minmag(__clc_vec2_fp16_t, __clc_vec2_fp16_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t - __spirv_ocl_cross(__clc_vec3_fp16_t, __clc_vec3_fp16_t); + __spirv_ocl_minmag(__clc_vec3_fp16_t, __clc_vec3_fp16_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t - __spirv_ocl_cross(__clc_vec4_fp16_t, __clc_vec4_fp16_t); + __spirv_ocl_minmag(__clc_vec4_fp16_t, __clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_minmag(__clc_vec8_fp16_t, __clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_minmag(__clc_vec16_fp16_t, __clc_vec16_fp16_t); #endif - -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_char_t __spirv_ocl_ctz(__clc_char_t); -_CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_vec2_char_t __spirv_ocl_ctz(__clc_vec2_char_t); -_CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_vec3_char_t __spirv_ocl_ctz(__clc_vec3_char_t); -_CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_vec4_char_t __spirv_ocl_ctz(__clc_vec4_char_t); -_CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_vec8_char_t __spirv_ocl_ctz(__clc_vec8_char_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_char_t - __spirv_ocl_ctz(__clc_vec16_char_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_int8_t __spirv_ocl_ctz(__clc_int8_t); -_CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_vec2_int8_t __spirv_ocl_ctz(__clc_vec2_int8_t); -_CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_vec3_int8_t __spirv_ocl_ctz(__clc_vec3_int8_t); -_CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_vec4_int8_t __spirv_ocl_ctz(__clc_vec4_int8_t); -_CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_vec8_int8_t __spirv_ocl_ctz(__clc_vec8_int8_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int8_t - __spirv_ocl_ctz(__clc_vec16_int8_t); -_CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_int16_t __spirv_ocl_ctz(__clc_int16_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int16_t - __spirv_ocl_ctz(__clc_vec2_int16_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int16_t - __spirv_ocl_ctz(__clc_vec3_int16_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int16_t - __spirv_ocl_ctz(__clc_vec4_int16_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int16_t - __spirv_ocl_ctz(__clc_vec8_int16_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int16_t - __spirv_ocl_ctz(__clc_vec16_int16_t); -_CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_int32_t __spirv_ocl_ctz(__clc_int32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int32_t - __spirv_ocl_ctz(__clc_vec2_int32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int32_t - __spirv_ocl_ctz(__clc_vec3_int32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int32_t - __spirv_ocl_ctz(__clc_vec4_int32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int32_t - __spirv_ocl_ctz(__clc_vec8_int32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int32_t - __spirv_ocl_ctz(__clc_vec16_int32_t); -_CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_int64_t __spirv_ocl_ctz(__clc_int64_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_int64_t - __spirv_ocl_ctz(__clc_vec2_int64_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_int64_t - __spirv_ocl_ctz(__clc_vec3_int64_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_int64_t - __spirv_ocl_ctz(__clc_vec4_int64_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_int64_t - __spirv_ocl_ctz(__clc_vec8_int64_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_int64_t - __spirv_ocl_ctz(__clc_vec16_int64_t); -_CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_uint8_t __spirv_ocl_ctz(__clc_uint8_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint8_t - __spirv_ocl_ctz(__clc_vec2_uint8_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint8_t - __spirv_ocl_ctz(__clc_vec3_uint8_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint8_t - __spirv_ocl_ctz(__clc_vec4_uint8_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint8_t - __spirv_ocl_ctz(__clc_vec8_uint8_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint8_t - __spirv_ocl_ctz(__clc_vec16_uint8_t); -_CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_uint16_t __spirv_ocl_ctz(__clc_uint16_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint16_t - __spirv_ocl_ctz(__clc_vec2_uint16_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint16_t - __spirv_ocl_ctz(__clc_vec3_uint16_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint16_t - __spirv_ocl_ctz(__clc_vec4_uint16_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint16_t - __spirv_ocl_ctz(__clc_vec8_uint16_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint16_t - __spirv_ocl_ctz(__clc_vec16_uint16_t); -_CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_uint32_t __spirv_ocl_ctz(__clc_uint32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint32_t - __spirv_ocl_ctz(__clc_vec2_uint32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint32_t - __spirv_ocl_ctz(__clc_vec3_uint32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint32_t - __spirv_ocl_ctz(__clc_vec4_uint32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint32_t - __spirv_ocl_ctz(__clc_vec8_uint32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint32_t - __spirv_ocl_ctz(__clc_vec16_uint32_t); -_CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_uint64_t __spirv_ocl_ctz(__clc_uint64_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint64_t - __spirv_ocl_ctz(__clc_vec2_uint64_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_uint64_t - __spirv_ocl_ctz(__clc_vec3_uint64_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_uint64_t - __spirv_ocl_ctz(__clc_vec4_uint64_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint64_t - __spirv_ocl_ctz(__clc_vec8_uint64_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint64_t - __spirv_ocl_ctz(__clc_vec16_uint64_t); - -_CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_degrees(__clc_fp32_t); + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_mix(__clc_fp32_t, + __clc_fp32_t, + __clc_fp32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t - __spirv_ocl_degrees(__clc_vec2_fp32_t); + __spirv_ocl_mix(__clc_vec2_fp32_t, __clc_vec2_fp32_t, __clc_vec2_fp32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t - __spirv_ocl_degrees(__clc_vec3_fp32_t); + __spirv_ocl_mix(__clc_vec3_fp32_t, __clc_vec3_fp32_t, __clc_vec3_fp32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t - __spirv_ocl_degrees(__clc_vec4_fp32_t); + __spirv_ocl_mix(__clc_vec4_fp32_t, __clc_vec4_fp32_t, __clc_vec4_fp32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t - __spirv_ocl_degrees(__clc_vec8_fp32_t); + __spirv_ocl_mix(__clc_vec8_fp32_t, __clc_vec8_fp32_t, __clc_vec8_fp32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t - __spirv_ocl_degrees(__clc_vec16_fp32_t); + __spirv_ocl_mix(__clc_vec16_fp32_t, __clc_vec16_fp32_t, __clc_vec16_fp32_t); #ifdef cl_khr_fp64 -_CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_degrees(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_mix(__clc_fp64_t, + __clc_fp64_t, + __clc_fp64_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t - __spirv_ocl_degrees(__clc_vec2_fp64_t); + __spirv_ocl_mix(__clc_vec2_fp64_t, __clc_vec2_fp64_t, __clc_vec2_fp64_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t - __spirv_ocl_degrees(__clc_vec3_fp64_t); + __spirv_ocl_mix(__clc_vec3_fp64_t, __clc_vec3_fp64_t, __clc_vec3_fp64_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t - __spirv_ocl_degrees(__clc_vec4_fp64_t); + __spirv_ocl_mix(__clc_vec4_fp64_t, __clc_vec4_fp64_t, __clc_vec4_fp64_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t - __spirv_ocl_degrees(__clc_vec8_fp64_t); + __spirv_ocl_mix(__clc_vec8_fp64_t, __clc_vec8_fp64_t, __clc_vec8_fp64_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t - __spirv_ocl_degrees(__clc_vec16_fp64_t); + __spirv_ocl_mix(__clc_vec16_fp64_t, __clc_vec16_fp64_t, __clc_vec16_fp64_t); #endif #ifdef cl_khr_fp16 -_CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_degrees(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_mix(__clc_fp16_t, + __clc_fp16_t, + __clc_fp16_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t - __spirv_ocl_degrees(__clc_vec2_fp16_t); + __spirv_ocl_mix(__clc_vec2_fp16_t, __clc_vec2_fp16_t, __clc_vec2_fp16_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t - __spirv_ocl_degrees(__clc_vec3_fp16_t); + __spirv_ocl_mix(__clc_vec3_fp16_t, __clc_vec3_fp16_t, __clc_vec3_fp16_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t - __spirv_ocl_degrees(__clc_vec4_fp16_t); + __spirv_ocl_mix(__clc_vec4_fp16_t, __clc_vec4_fp16_t, __clc_vec4_fp16_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t - __spirv_ocl_degrees(__clc_vec8_fp16_t); + __spirv_ocl_mix(__clc_vec8_fp16_t, __clc_vec8_fp16_t, __clc_vec8_fp16_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t - __spirv_ocl_degrees(__clc_vec16_fp16_t); + __spirv_ocl_mix(__clc_vec16_fp16_t, __clc_vec16_fp16_t, __clc_vec16_fp16_t); #endif -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t - __spirv_ocl_distance(__clc_fp32_t, __clc_fp32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t - __spirv_ocl_distance(__clc_vec2_fp32_t, __clc_vec2_fp32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t - __spirv_ocl_distance(__clc_vec3_fp32_t, __clc_vec3_fp32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t - __spirv_ocl_distance(__clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL __clc_fp32_t __spirv_ocl_modf(__clc_fp32_t, + __clc_fp32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_fp32_t __spirv_ocl_modf(__clc_fp32_t, + __clc_fp32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_fp32_t __spirv_ocl_modf(__clc_fp32_t, + __clc_fp32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp32_t __spirv_ocl_modf(__clc_vec2_fp32_t, + __clc_vec2_fp32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp32_t +__spirv_ocl_modf(__clc_vec2_fp32_t, __clc_vec2_fp32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp32_t +__spirv_ocl_modf(__clc_vec2_fp32_t, __clc_vec2_fp32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp32_t __spirv_ocl_modf(__clc_vec3_fp32_t, + __clc_vec3_fp32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp32_t +__spirv_ocl_modf(__clc_vec3_fp32_t, __clc_vec3_fp32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp32_t +__spirv_ocl_modf(__clc_vec3_fp32_t, __clc_vec3_fp32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp32_t __spirv_ocl_modf(__clc_vec4_fp32_t, + __clc_vec4_fp32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp32_t +__spirv_ocl_modf(__clc_vec4_fp32_t, __clc_vec4_fp32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp32_t +__spirv_ocl_modf(__clc_vec4_fp32_t, __clc_vec4_fp32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp32_t __spirv_ocl_modf(__clc_vec8_fp32_t, + __clc_vec8_fp32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp32_t +__spirv_ocl_modf(__clc_vec8_fp32_t, __clc_vec8_fp32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp32_t +__spirv_ocl_modf(__clc_vec8_fp32_t, __clc_vec8_fp32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp32_t +__spirv_ocl_modf(__clc_vec16_fp32_t, __clc_vec16_fp32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp32_t +__spirv_ocl_modf(__clc_vec16_fp32_t, __clc_vec16_fp32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp32_t +__spirv_ocl_modf(__clc_vec16_fp32_t, __clc_vec16_fp32_t __global *); #ifdef cl_khr_fp64 -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t - __spirv_ocl_distance(__clc_fp64_t, __clc_fp64_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t - __spirv_ocl_distance(__clc_vec2_fp64_t, __clc_vec2_fp64_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t - __spirv_ocl_distance(__clc_vec3_fp64_t, __clc_vec3_fp64_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t - __spirv_ocl_distance(__clc_vec4_fp64_t, __clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL __clc_fp64_t __spirv_ocl_modf(__clc_fp64_t, + __clc_fp64_t *); +_CLC_OVERLOAD _CLC_DECL __clc_fp64_t __spirv_ocl_modf(__clc_fp64_t, + __clc_fp64_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_fp64_t __spirv_ocl_modf(__clc_fp64_t, + __clc_fp64_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp64_t __spirv_ocl_modf(__clc_vec2_fp64_t, + __clc_vec2_fp64_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp64_t +__spirv_ocl_modf(__clc_vec2_fp64_t, __clc_vec2_fp64_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp64_t +__spirv_ocl_modf(__clc_vec2_fp64_t, __clc_vec2_fp64_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp64_t __spirv_ocl_modf(__clc_vec3_fp64_t, + __clc_vec3_fp64_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp64_t +__spirv_ocl_modf(__clc_vec3_fp64_t, __clc_vec3_fp64_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp64_t +__spirv_ocl_modf(__clc_vec3_fp64_t, __clc_vec3_fp64_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp64_t __spirv_ocl_modf(__clc_vec4_fp64_t, + __clc_vec4_fp64_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp64_t +__spirv_ocl_modf(__clc_vec4_fp64_t, __clc_vec4_fp64_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp64_t +__spirv_ocl_modf(__clc_vec4_fp64_t, __clc_vec4_fp64_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp64_t __spirv_ocl_modf(__clc_vec8_fp64_t, + __clc_vec8_fp64_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp64_t +__spirv_ocl_modf(__clc_vec8_fp64_t, __clc_vec8_fp64_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp64_t +__spirv_ocl_modf(__clc_vec8_fp64_t, __clc_vec8_fp64_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp64_t +__spirv_ocl_modf(__clc_vec16_fp64_t, __clc_vec16_fp64_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp64_t +__spirv_ocl_modf(__clc_vec16_fp64_t, __clc_vec16_fp64_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp64_t +__spirv_ocl_modf(__clc_vec16_fp64_t, __clc_vec16_fp64_t __global *); #endif #ifdef cl_khr_fp16 -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t - __spirv_ocl_distance(__clc_fp16_t, __clc_fp16_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t - __spirv_ocl_distance(__clc_vec2_fp16_t, __clc_vec2_fp16_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t - __spirv_ocl_distance(__clc_vec3_fp16_t, __clc_vec3_fp16_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t - __spirv_ocl_distance(__clc_vec4_fp16_t, __clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL __clc_fp16_t __spirv_ocl_modf(__clc_fp16_t, + __clc_fp16_t *); +_CLC_OVERLOAD _CLC_DECL __clc_fp16_t __spirv_ocl_modf(__clc_fp16_t, + __clc_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_fp16_t __spirv_ocl_modf(__clc_fp16_t, + __clc_fp16_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp16_t __spirv_ocl_modf(__clc_vec2_fp16_t, + __clc_vec2_fp16_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp16_t +__spirv_ocl_modf(__clc_vec2_fp16_t, __clc_vec2_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp16_t +__spirv_ocl_modf(__clc_vec2_fp16_t, __clc_vec2_fp16_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp16_t __spirv_ocl_modf(__clc_vec3_fp16_t, + __clc_vec3_fp16_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp16_t +__spirv_ocl_modf(__clc_vec3_fp16_t, __clc_vec3_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp16_t +__spirv_ocl_modf(__clc_vec3_fp16_t, __clc_vec3_fp16_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp16_t __spirv_ocl_modf(__clc_vec4_fp16_t, + __clc_vec4_fp16_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp16_t +__spirv_ocl_modf(__clc_vec4_fp16_t, __clc_vec4_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp16_t +__spirv_ocl_modf(__clc_vec4_fp16_t, __clc_vec4_fp16_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp16_t __spirv_ocl_modf(__clc_vec8_fp16_t, + __clc_vec8_fp16_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp16_t +__spirv_ocl_modf(__clc_vec8_fp16_t, __clc_vec8_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp16_t +__spirv_ocl_modf(__clc_vec8_fp16_t, __clc_vec8_fp16_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp16_t +__spirv_ocl_modf(__clc_vec16_fp16_t, __clc_vec16_fp16_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp16_t +__spirv_ocl_modf(__clc_vec16_fp16_t, __clc_vec16_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp16_t +__spirv_ocl_modf(__clc_vec16_fp16_t, __clc_vec16_fp16_t __global *); #endif -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t - __spirv_ocl_fast_distance(__clc_fp32_t, __clc_fp32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t - __spirv_ocl_fast_distance(__clc_vec2_fp32_t, __clc_vec2_fp32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t - __spirv_ocl_fast_distance(__clc_vec3_fp32_t, __clc_vec3_fp32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t - __spirv_ocl_fast_distance(__clc_vec4_fp32_t, __clc_vec4_fp32_t); - _CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_fast_length(__clc_fp32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t - __spirv_ocl_fast_length(__clc_vec2_fp32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t - __spirv_ocl_fast_length(__clc_vec3_fp32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t - __spirv_ocl_fast_length(__clc_vec4_fp32_t); - -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t - __spirv_ocl_fast_normalize(__clc_fp32_t); +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_nan(__clc_int32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_nan(__clc_uint32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t - __spirv_ocl_fast_normalize(__clc_vec2_fp32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t - __spirv_ocl_fast_normalize(__clc_vec3_fp32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t - __spirv_ocl_fast_normalize(__clc_vec4_fp32_t); - -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t - __spirv_ocl_fclamp(__clc_fp32_t, __clc_fp32_t, __clc_fp32_t); + __spirv_ocl_nan(__clc_vec2_int32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t - __spirv_ocl_fclamp(__clc_vec2_fp32_t, __clc_vec2_fp32_t, __clc_vec2_fp32_t); + __spirv_ocl_nan(__clc_vec2_uint32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t - __spirv_ocl_fclamp(__clc_vec3_fp32_t, __clc_vec3_fp32_t, __clc_vec3_fp32_t); + __spirv_ocl_nan(__clc_vec3_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_nan(__clc_vec3_uint32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t - __spirv_ocl_fclamp(__clc_vec4_fp32_t, __clc_vec4_fp32_t, __clc_vec4_fp32_t); + __spirv_ocl_nan(__clc_vec4_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_nan(__clc_vec4_uint32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t - __spirv_ocl_fclamp(__clc_vec8_fp32_t, __clc_vec8_fp32_t, __clc_vec8_fp32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t __spirv_ocl_fclamp( - __clc_vec16_fp32_t, __clc_vec16_fp32_t, __clc_vec16_fp32_t); + __spirv_ocl_nan(__clc_vec8_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_nan(__clc_vec8_uint32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_nan(__clc_vec16_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_nan(__clc_vec16_uint32_t); #ifdef cl_khr_fp64 -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t - __spirv_ocl_fclamp(__clc_fp64_t, __clc_fp64_t, __clc_fp64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_nan(__clc_int64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_nan(__clc_uint64_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t - __spirv_ocl_fclamp(__clc_vec2_fp64_t, __clc_vec2_fp64_t, __clc_vec2_fp64_t); + __spirv_ocl_nan(__clc_vec2_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_nan(__clc_vec2_uint64_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t - __spirv_ocl_fclamp(__clc_vec3_fp64_t, __clc_vec3_fp64_t, __clc_vec3_fp64_t); + __spirv_ocl_nan(__clc_vec3_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_nan(__clc_vec3_uint64_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t - __spirv_ocl_fclamp(__clc_vec4_fp64_t, __clc_vec4_fp64_t, __clc_vec4_fp64_t); + __spirv_ocl_nan(__clc_vec4_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_nan(__clc_vec4_uint64_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t - __spirv_ocl_fclamp(__clc_vec8_fp64_t, __clc_vec8_fp64_t, __clc_vec8_fp64_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t __spirv_ocl_fclamp( - __clc_vec16_fp64_t, __clc_vec16_fp64_t, __clc_vec16_fp64_t); + __spirv_ocl_nan(__clc_vec8_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_nan(__clc_vec8_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_nan(__clc_vec16_int64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_nan(__clc_vec16_uint64_t); #endif #ifdef cl_khr_fp16 -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t - __spirv_ocl_fclamp(__clc_fp16_t, __clc_fp16_t, __clc_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_nan(__clc_int16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_nan(__clc_uint16_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t - __spirv_ocl_fclamp(__clc_vec2_fp16_t, __clc_vec2_fp16_t, __clc_vec2_fp16_t); + __spirv_ocl_nan(__clc_vec2_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_nan(__clc_vec2_uint16_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t - __spirv_ocl_fclamp(__clc_vec3_fp16_t, __clc_vec3_fp16_t, __clc_vec3_fp16_t); + __spirv_ocl_nan(__clc_vec3_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_nan(__clc_vec3_uint16_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t - __spirv_ocl_fclamp(__clc_vec4_fp16_t, __clc_vec4_fp16_t, __clc_vec4_fp16_t); + __spirv_ocl_nan(__clc_vec4_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_nan(__clc_vec4_uint16_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t - __spirv_ocl_fclamp(__clc_vec8_fp16_t, __clc_vec8_fp16_t, __clc_vec8_fp16_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t __spirv_ocl_fclamp( - __clc_vec16_fp16_t, __clc_vec16_fp16_t, __clc_vec16_fp16_t); + __spirv_ocl_nan(__clc_vec8_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_nan(__clc_vec8_uint16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_nan(__clc_vec16_int16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_nan(__clc_vec16_uint16_t); #endif _CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_half_rsqrt(__clc_fp32_t); +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_native_cos(__clc_fp32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t - __spirv_ocl_half_rsqrt(__clc_vec2_fp32_t); + __spirv_ocl_native_cos(__clc_vec2_fp32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t - __spirv_ocl_half_rsqrt(__clc_vec3_fp32_t); + __spirv_ocl_native_cos(__clc_vec3_fp32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t - __spirv_ocl_half_rsqrt(__clc_vec4_fp32_t); + __spirv_ocl_native_cos(__clc_vec4_fp32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t - __spirv_ocl_half_rsqrt(__clc_vec8_fp32_t); + __spirv_ocl_native_cos(__clc_vec8_fp32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t - __spirv_ocl_half_rsqrt(__clc_vec16_fp32_t); + __spirv_ocl_native_cos(__clc_vec16_fp32_t); -_CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_half_sqrt(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_native_divide(__clc_fp32_t, __clc_fp32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t - __spirv_ocl_half_sqrt(__clc_vec2_fp32_t); + __spirv_ocl_native_divide(__clc_vec2_fp32_t, __clc_vec2_fp32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t - __spirv_ocl_half_sqrt(__clc_vec3_fp32_t); + __spirv_ocl_native_divide(__clc_vec3_fp32_t, __clc_vec3_fp32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t - __spirv_ocl_half_sqrt(__clc_vec4_fp32_t); + __spirv_ocl_native_divide(__clc_vec4_fp32_t, __clc_vec4_fp32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t - __spirv_ocl_half_sqrt(__clc_vec8_fp32_t); + __spirv_ocl_native_divide(__clc_vec8_fp32_t, __clc_vec8_fp32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t - __spirv_ocl_half_sqrt(__clc_vec16_fp32_t); + __spirv_ocl_native_divide(__clc_vec16_fp32_t, __clc_vec16_fp32_t); _CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_length(__clc_fp32_t); -_CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_length(__clc_vec2_fp32_t); -_CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_length(__clc_vec3_fp32_t); -_CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_length(__clc_vec4_fp32_t); +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_native_exp(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_native_exp(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_native_exp(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_native_exp(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_native_exp(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_native_exp(__clc_vec16_fp32_t); -#ifdef cl_khr_fp64 -_CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_length(__clc_fp64_t); -_CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_length(__clc_vec2_fp64_t); -_CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_length(__clc_vec3_fp64_t); _CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_length(__clc_vec4_fp64_t); -#endif +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_native_exp10(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_native_exp10(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_native_exp10(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_native_exp10(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_native_exp10(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_native_exp10(__clc_vec16_fp32_t); -#ifdef cl_khr_fp16 _CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_length(__clc_fp16_t); +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_native_exp2(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_native_exp2(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_native_exp2(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_native_exp2(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_native_exp2(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_native_exp2(__clc_vec16_fp32_t); + _CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_length(__clc_vec2_fp16_t); +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_native_log(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_native_log(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_native_log(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_native_log(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_native_log(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_native_log(__clc_vec16_fp32_t); + _CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_length(__clc_vec3_fp16_t); +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_native_log10(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_native_log10(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_native_log10(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_native_log10(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_native_log10(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_native_log10(__clc_vec16_fp32_t); + _CLC_OVERLOAD -_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_length(__clc_vec4_fp16_t); -#endif +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_native_log2(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_native_log2(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_native_log2(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_native_log2(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_native_log2(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_native_log2(__clc_vec16_fp32_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_mix(__clc_fp32_t, - __clc_fp32_t, - __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_native_powr(__clc_fp32_t, __clc_fp32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t - __spirv_ocl_mix(__clc_vec2_fp32_t, __clc_vec2_fp32_t, __clc_vec2_fp32_t); + __spirv_ocl_native_powr(__clc_vec2_fp32_t, __clc_vec2_fp32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t - __spirv_ocl_mix(__clc_vec3_fp32_t, __clc_vec3_fp32_t, __clc_vec3_fp32_t); + __spirv_ocl_native_powr(__clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_native_powr(__clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_native_powr(__clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_native_powr(__clc_vec16_fp32_t, __clc_vec16_fp32_t); + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_native_recip(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_native_recip(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_native_recip(__clc_vec3_fp32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t - __spirv_ocl_mix(__clc_vec4_fp32_t, __clc_vec4_fp32_t, __clc_vec4_fp32_t); + __spirv_ocl_native_recip(__clc_vec4_fp32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t - __spirv_ocl_mix(__clc_vec8_fp32_t, __clc_vec8_fp32_t, __clc_vec8_fp32_t); + __spirv_ocl_native_recip(__clc_vec8_fp32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t - __spirv_ocl_mix(__clc_vec16_fp32_t, __clc_vec16_fp32_t, __clc_vec16_fp32_t); - -#ifdef cl_khr_fp64 -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_mix(__clc_fp64_t, - __clc_fp64_t, - __clc_fp64_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t - __spirv_ocl_mix(__clc_vec2_fp64_t, __clc_vec2_fp64_t, __clc_vec2_fp64_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t - __spirv_ocl_mix(__clc_vec3_fp64_t, __clc_vec3_fp64_t, __clc_vec3_fp64_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t - __spirv_ocl_mix(__clc_vec4_fp64_t, __clc_vec4_fp64_t, __clc_vec4_fp64_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t - __spirv_ocl_mix(__clc_vec8_fp64_t, __clc_vec8_fp64_t, __clc_vec8_fp64_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t - __spirv_ocl_mix(__clc_vec16_fp64_t, __clc_vec16_fp64_t, __clc_vec16_fp64_t); -#endif - -#ifdef cl_khr_fp16 -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_mix(__clc_fp16_t, - __clc_fp16_t, - __clc_fp16_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t - __spirv_ocl_mix(__clc_vec2_fp16_t, __clc_vec2_fp16_t, __clc_vec2_fp16_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t - __spirv_ocl_mix(__clc_vec3_fp16_t, __clc_vec3_fp16_t, __clc_vec3_fp16_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t - __spirv_ocl_mix(__clc_vec4_fp16_t, __clc_vec4_fp16_t, __clc_vec4_fp16_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t - __spirv_ocl_mix(__clc_vec8_fp16_t, __clc_vec8_fp16_t, __clc_vec8_fp16_t); -_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t - __spirv_ocl_mix(__clc_vec16_fp16_t, __clc_vec16_fp16_t, __clc_vec16_fp16_t); -#endif + __spirv_ocl_native_recip(__clc_vec16_fp32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_native_rsqrt(__clc_fp32_t); @@ -13113,6 +15817,19 @@ _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t __spirv_ocl_native_rsqrt(__clc_vec16_fp32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_native_sin(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_native_sin(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_native_sin(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_native_sin(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_native_sin(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_native_sin(__clc_vec16_fp32_t); + _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_native_sqrt(__clc_fp32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t @@ -13126,6 +15843,62 @@ _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t __spirv_ocl_native_sqrt(__clc_vec16_fp32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_native_tan(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_native_tan(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_native_tan(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_native_tan(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_native_tan(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_native_tan(__clc_vec16_fp32_t); + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_nextafter(__clc_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_nextafter(__clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_nextafter(__clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_nextafter(__clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_nextafter(__clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_nextafter(__clc_vec16_fp32_t, __clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t + __spirv_ocl_nextafter(__clc_fp64_t, __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_nextafter(__clc_vec2_fp64_t, __clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_nextafter(__clc_vec3_fp64_t, __clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_nextafter(__clc_vec4_fp64_t, __clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_nextafter(__clc_vec8_fp64_t, __clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_nextafter(__clc_vec16_fp64_t, __clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t + __spirv_ocl_nextafter(__clc_fp16_t, __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_nextafter(__clc_vec2_fp16_t, __clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_nextafter(__clc_vec3_fp16_t, __clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_nextafter(__clc_vec4_fp16_t, __clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_nextafter(__clc_vec8_fp16_t, __clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_nextafter(__clc_vec16_fp16_t, __clc_vec16_fp16_t); +#endif + _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_normalize(__clc_fp32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t @@ -13266,6 +16039,135 @@ _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint64_t _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint64_t __spirv_ocl_popcount(__clc_vec16_uint64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_pow(__clc_fp32_t, + __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_pow(__clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_pow(__clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_pow(__clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_pow(__clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_pow(__clc_vec16_fp32_t, __clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_pow(__clc_fp64_t, + __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_pow(__clc_vec2_fp64_t, __clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_pow(__clc_vec3_fp64_t, __clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_pow(__clc_vec4_fp64_t, __clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_pow(__clc_vec8_fp64_t, __clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_pow(__clc_vec16_fp64_t, __clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_pow(__clc_fp16_t, + __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_pow(__clc_vec2_fp16_t, __clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_pow(__clc_vec3_fp16_t, __clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_pow(__clc_vec4_fp16_t, __clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_pow(__clc_vec8_fp16_t, __clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_pow(__clc_vec16_fp16_t, __clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_pown(__clc_fp32_t, __clc_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_pown(__clc_vec2_fp32_t, __clc_vec2_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_pown(__clc_vec3_fp32_t, __clc_vec3_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_pown(__clc_vec4_fp32_t, __clc_vec4_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_pown(__clc_vec8_fp32_t, __clc_vec8_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_pown(__clc_vec16_fp32_t, __clc_vec16_int32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t + __spirv_ocl_pown(__clc_fp64_t, __clc_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_pown(__clc_vec2_fp64_t, __clc_vec2_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_pown(__clc_vec3_fp64_t, __clc_vec3_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_pown(__clc_vec4_fp64_t, __clc_vec4_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_pown(__clc_vec8_fp64_t, __clc_vec8_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_pown(__clc_vec16_fp64_t, __clc_vec16_int32_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t + __spirv_ocl_pown(__clc_fp16_t, __clc_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_pown(__clc_vec2_fp16_t, __clc_vec2_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_pown(__clc_vec3_fp16_t, __clc_vec3_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_pown(__clc_vec4_fp16_t, __clc_vec4_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_pown(__clc_vec8_fp16_t, __clc_vec8_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_pown(__clc_vec16_fp16_t, __clc_vec16_int32_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_powr(__clc_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_powr(__clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_powr(__clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_powr(__clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_powr(__clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_powr(__clc_vec16_fp32_t, __clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t + __spirv_ocl_powr(__clc_fp64_t, __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_powr(__clc_vec2_fp64_t, __clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_powr(__clc_vec3_fp64_t, __clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_powr(__clc_vec4_fp64_t, __clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_powr(__clc_vec8_fp64_t, __clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_powr(__clc_vec16_fp64_t, __clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t + __spirv_ocl_powr(__clc_fp16_t, __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_powr(__clc_vec2_fp16_t, __clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_powr(__clc_vec3_fp16_t, __clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_powr(__clc_vec4_fp16_t, __clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_powr(__clc_vec8_fp16_t, __clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_powr(__clc_vec16_fp16_t, __clc_vec16_fp16_t); +#endif + _CLC_OVERLOAD _CLC_DECL void __spirv_ocl_prefetch(__clc_char_t const __global *, __clc_size_t); _CLC_OVERLOAD _CLC_DECL void @@ -13460,6 +16362,253 @@ _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t __spirv_ocl_radians(__clc_vec16_fp16_t); #endif +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_remainder(__clc_fp32_t, __clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_remainder(__clc_vec2_fp32_t, __clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_remainder(__clc_vec3_fp32_t, __clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_remainder(__clc_vec4_fp32_t, __clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_remainder(__clc_vec8_fp32_t, __clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_remainder(__clc_vec16_fp32_t, __clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t + __spirv_ocl_remainder(__clc_fp64_t, __clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_remainder(__clc_vec2_fp64_t, __clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_remainder(__clc_vec3_fp64_t, __clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_remainder(__clc_vec4_fp64_t, __clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_remainder(__clc_vec8_fp64_t, __clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_remainder(__clc_vec16_fp64_t, __clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t + __spirv_ocl_remainder(__clc_fp16_t, __clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_remainder(__clc_vec2_fp16_t, __clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_remainder(__clc_vec3_fp16_t, __clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_remainder(__clc_vec4_fp16_t, __clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_remainder(__clc_vec8_fp16_t, __clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_remainder(__clc_vec16_fp16_t, __clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL __clc_fp32_t __spirv_ocl_remquo(__clc_fp32_t, + __clc_fp32_t, + __clc_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_fp32_t +__spirv_ocl_remquo(__clc_fp32_t, __clc_fp32_t, __clc_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_fp32_t +__spirv_ocl_remquo(__clc_fp32_t, __clc_fp32_t, __clc_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp32_t +__spirv_ocl_remquo(__clc_vec2_fp32_t, __clc_vec2_fp32_t, __clc_vec2_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp32_t __spirv_ocl_remquo( + __clc_vec2_fp32_t, __clc_vec2_fp32_t, __clc_vec2_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp32_t __spirv_ocl_remquo( + __clc_vec2_fp32_t, __clc_vec2_fp32_t, __clc_vec2_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp32_t +__spirv_ocl_remquo(__clc_vec3_fp32_t, __clc_vec3_fp32_t, __clc_vec3_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp32_t __spirv_ocl_remquo( + __clc_vec3_fp32_t, __clc_vec3_fp32_t, __clc_vec3_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp32_t __spirv_ocl_remquo( + __clc_vec3_fp32_t, __clc_vec3_fp32_t, __clc_vec3_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp32_t +__spirv_ocl_remquo(__clc_vec4_fp32_t, __clc_vec4_fp32_t, __clc_vec4_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp32_t __spirv_ocl_remquo( + __clc_vec4_fp32_t, __clc_vec4_fp32_t, __clc_vec4_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp32_t __spirv_ocl_remquo( + __clc_vec4_fp32_t, __clc_vec4_fp32_t, __clc_vec4_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp32_t +__spirv_ocl_remquo(__clc_vec8_fp32_t, __clc_vec8_fp32_t, __clc_vec8_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp32_t __spirv_ocl_remquo( + __clc_vec8_fp32_t, __clc_vec8_fp32_t, __clc_vec8_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp32_t __spirv_ocl_remquo( + __clc_vec8_fp32_t, __clc_vec8_fp32_t, __clc_vec8_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp32_t __spirv_ocl_remquo( + __clc_vec16_fp32_t, __clc_vec16_fp32_t, __clc_vec16_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp32_t __spirv_ocl_remquo( + __clc_vec16_fp32_t, __clc_vec16_fp32_t, __clc_vec16_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp32_t __spirv_ocl_remquo( + __clc_vec16_fp32_t, __clc_vec16_fp32_t, __clc_vec16_int32_t __global *); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL __clc_fp64_t __spirv_ocl_remquo(__clc_fp64_t, + __clc_fp64_t, + __clc_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_fp64_t +__spirv_ocl_remquo(__clc_fp64_t, __clc_fp64_t, __clc_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_fp64_t +__spirv_ocl_remquo(__clc_fp64_t, __clc_fp64_t, __clc_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp64_t +__spirv_ocl_remquo(__clc_vec2_fp64_t, __clc_vec2_fp64_t, __clc_vec2_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp64_t __spirv_ocl_remquo( + __clc_vec2_fp64_t, __clc_vec2_fp64_t, __clc_vec2_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp64_t __spirv_ocl_remquo( + __clc_vec2_fp64_t, __clc_vec2_fp64_t, __clc_vec2_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp64_t +__spirv_ocl_remquo(__clc_vec3_fp64_t, __clc_vec3_fp64_t, __clc_vec3_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp64_t __spirv_ocl_remquo( + __clc_vec3_fp64_t, __clc_vec3_fp64_t, __clc_vec3_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp64_t __spirv_ocl_remquo( + __clc_vec3_fp64_t, __clc_vec3_fp64_t, __clc_vec3_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp64_t +__spirv_ocl_remquo(__clc_vec4_fp64_t, __clc_vec4_fp64_t, __clc_vec4_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp64_t __spirv_ocl_remquo( + __clc_vec4_fp64_t, __clc_vec4_fp64_t, __clc_vec4_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp64_t __spirv_ocl_remquo( + __clc_vec4_fp64_t, __clc_vec4_fp64_t, __clc_vec4_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp64_t +__spirv_ocl_remquo(__clc_vec8_fp64_t, __clc_vec8_fp64_t, __clc_vec8_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp64_t __spirv_ocl_remquo( + __clc_vec8_fp64_t, __clc_vec8_fp64_t, __clc_vec8_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp64_t __spirv_ocl_remquo( + __clc_vec8_fp64_t, __clc_vec8_fp64_t, __clc_vec8_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp64_t __spirv_ocl_remquo( + __clc_vec16_fp64_t, __clc_vec16_fp64_t, __clc_vec16_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp64_t __spirv_ocl_remquo( + __clc_vec16_fp64_t, __clc_vec16_fp64_t, __clc_vec16_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp64_t __spirv_ocl_remquo( + __clc_vec16_fp64_t, __clc_vec16_fp64_t, __clc_vec16_int32_t __global *); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL __clc_fp16_t __spirv_ocl_remquo(__clc_fp16_t, + __clc_fp16_t, + __clc_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_fp16_t +__spirv_ocl_remquo(__clc_fp16_t, __clc_fp16_t, __clc_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_fp16_t +__spirv_ocl_remquo(__clc_fp16_t, __clc_fp16_t, __clc_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp16_t +__spirv_ocl_remquo(__clc_vec2_fp16_t, __clc_vec2_fp16_t, __clc_vec2_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp16_t __spirv_ocl_remquo( + __clc_vec2_fp16_t, __clc_vec2_fp16_t, __clc_vec2_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp16_t __spirv_ocl_remquo( + __clc_vec2_fp16_t, __clc_vec2_fp16_t, __clc_vec2_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp16_t +__spirv_ocl_remquo(__clc_vec3_fp16_t, __clc_vec3_fp16_t, __clc_vec3_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp16_t __spirv_ocl_remquo( + __clc_vec3_fp16_t, __clc_vec3_fp16_t, __clc_vec3_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp16_t __spirv_ocl_remquo( + __clc_vec3_fp16_t, __clc_vec3_fp16_t, __clc_vec3_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp16_t +__spirv_ocl_remquo(__clc_vec4_fp16_t, __clc_vec4_fp16_t, __clc_vec4_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp16_t __spirv_ocl_remquo( + __clc_vec4_fp16_t, __clc_vec4_fp16_t, __clc_vec4_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp16_t __spirv_ocl_remquo( + __clc_vec4_fp16_t, __clc_vec4_fp16_t, __clc_vec4_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp16_t +__spirv_ocl_remquo(__clc_vec8_fp16_t, __clc_vec8_fp16_t, __clc_vec8_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp16_t __spirv_ocl_remquo( + __clc_vec8_fp16_t, __clc_vec8_fp16_t, __clc_vec8_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp16_t __spirv_ocl_remquo( + __clc_vec8_fp16_t, __clc_vec8_fp16_t, __clc_vec8_int32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp16_t __spirv_ocl_remquo( + __clc_vec16_fp16_t, __clc_vec16_fp16_t, __clc_vec16_int32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp16_t __spirv_ocl_remquo( + __clc_vec16_fp16_t, __clc_vec16_fp16_t, __clc_vec16_int32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp16_t __spirv_ocl_remquo( + __clc_vec16_fp16_t, __clc_vec16_fp16_t, __clc_vec16_int32_t __global *); +#endif + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_rint(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_rint(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_rint(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_rint(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_rint(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_rint(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_rint(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_rint(__clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_rint(__clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_rint(__clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_rint(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_rint(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_rint(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_rint(__clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_rint(__clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_rint(__clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_rint(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_rint(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t + __spirv_ocl_rootn(__clc_fp32_t, __clc_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_rootn(__clc_vec2_fp32_t, __clc_vec2_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_rootn(__clc_vec3_fp32_t, __clc_vec3_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_rootn(__clc_vec4_fp32_t, __clc_vec4_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_rootn(__clc_vec8_fp32_t, __clc_vec8_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_rootn(__clc_vec16_fp32_t, __clc_vec16_int32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t + __spirv_ocl_rootn(__clc_fp64_t, __clc_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_rootn(__clc_vec2_fp64_t, __clc_vec2_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_rootn(__clc_vec3_fp64_t, __clc_vec3_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_rootn(__clc_vec4_fp64_t, __clc_vec4_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_rootn(__clc_vec8_fp64_t, __clc_vec8_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_rootn(__clc_vec16_fp64_t, __clc_vec16_int32_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t + __spirv_ocl_rootn(__clc_fp16_t, __clc_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_rootn(__clc_vec2_fp16_t, __clc_vec2_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_rootn(__clc_vec3_fp16_t, __clc_vec3_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_rootn(__clc_vec4_fp16_t, __clc_vec4_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_rootn(__clc_vec8_fp16_t, __clc_vec8_int32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_rootn(__clc_vec16_fp16_t, __clc_vec16_int32_t); +#endif + _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_char_t __spirv_ocl_rotate(__clc_char_t, __clc_char_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_char_t @@ -13569,6 +16718,49 @@ _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_uint64_t _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_uint64_t __spirv_ocl_rotate(__clc_vec16_uint64_t, __clc_vec16_uint64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_round(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_round(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_round(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_round(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_round(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_round(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_round(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_round(__clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_round(__clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_round(__clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_round(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_round(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_round(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_round(__clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_round(__clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_round(__clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_round(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_round(__clc_vec16_fp16_t); +#endif + _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_rsqrt(__clc_fp32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t @@ -14613,6 +17805,247 @@ _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t __spirv_ocl_sign(__clc_vec16_fp16_t); #endif +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_sin(__clc_fp32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t __spirv_ocl_sin(__clc_vec2_fp32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t __spirv_ocl_sin(__clc_vec3_fp32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t __spirv_ocl_sin(__clc_vec4_fp32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t __spirv_ocl_sin(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_sin(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_sin(__clc_fp64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t __spirv_ocl_sin(__clc_vec2_fp64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t __spirv_ocl_sin(__clc_vec3_fp64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t __spirv_ocl_sin(__clc_vec4_fp64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t __spirv_ocl_sin(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_sin(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_sin(__clc_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t __spirv_ocl_sin(__clc_vec2_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t __spirv_ocl_sin(__clc_vec3_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t __spirv_ocl_sin(__clc_vec4_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t __spirv_ocl_sin(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_sin(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD _CLC_DECL __clc_fp32_t __spirv_ocl_sincos(__clc_fp32_t, + __clc_fp32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_fp32_t __spirv_ocl_sincos(__clc_fp32_t, + __clc_fp32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_fp32_t +__spirv_ocl_sincos(__clc_fp32_t, __clc_fp32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp32_t +__spirv_ocl_sincos(__clc_vec2_fp32_t, __clc_vec2_fp32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp32_t +__spirv_ocl_sincos(__clc_vec2_fp32_t, __clc_vec2_fp32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp32_t +__spirv_ocl_sincos(__clc_vec2_fp32_t, __clc_vec2_fp32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp32_t +__spirv_ocl_sincos(__clc_vec3_fp32_t, __clc_vec3_fp32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp32_t +__spirv_ocl_sincos(__clc_vec3_fp32_t, __clc_vec3_fp32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp32_t +__spirv_ocl_sincos(__clc_vec3_fp32_t, __clc_vec3_fp32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp32_t +__spirv_ocl_sincos(__clc_vec4_fp32_t, __clc_vec4_fp32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp32_t +__spirv_ocl_sincos(__clc_vec4_fp32_t, __clc_vec4_fp32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp32_t +__spirv_ocl_sincos(__clc_vec4_fp32_t, __clc_vec4_fp32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp32_t +__spirv_ocl_sincos(__clc_vec8_fp32_t, __clc_vec8_fp32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp32_t +__spirv_ocl_sincos(__clc_vec8_fp32_t, __clc_vec8_fp32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp32_t +__spirv_ocl_sincos(__clc_vec8_fp32_t, __clc_vec8_fp32_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp32_t +__spirv_ocl_sincos(__clc_vec16_fp32_t, __clc_vec16_fp32_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp32_t +__spirv_ocl_sincos(__clc_vec16_fp32_t, __clc_vec16_fp32_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp32_t +__spirv_ocl_sincos(__clc_vec16_fp32_t, __clc_vec16_fp32_t __global *); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL __clc_fp64_t __spirv_ocl_sincos(__clc_fp64_t, + __clc_fp64_t *); +_CLC_OVERLOAD _CLC_DECL __clc_fp64_t __spirv_ocl_sincos(__clc_fp64_t, + __clc_fp64_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_fp64_t +__spirv_ocl_sincos(__clc_fp64_t, __clc_fp64_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp64_t +__spirv_ocl_sincos(__clc_vec2_fp64_t, __clc_vec2_fp64_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp64_t +__spirv_ocl_sincos(__clc_vec2_fp64_t, __clc_vec2_fp64_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp64_t +__spirv_ocl_sincos(__clc_vec2_fp64_t, __clc_vec2_fp64_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp64_t +__spirv_ocl_sincos(__clc_vec3_fp64_t, __clc_vec3_fp64_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp64_t +__spirv_ocl_sincos(__clc_vec3_fp64_t, __clc_vec3_fp64_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp64_t +__spirv_ocl_sincos(__clc_vec3_fp64_t, __clc_vec3_fp64_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp64_t +__spirv_ocl_sincos(__clc_vec4_fp64_t, __clc_vec4_fp64_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp64_t +__spirv_ocl_sincos(__clc_vec4_fp64_t, __clc_vec4_fp64_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp64_t +__spirv_ocl_sincos(__clc_vec4_fp64_t, __clc_vec4_fp64_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp64_t +__spirv_ocl_sincos(__clc_vec8_fp64_t, __clc_vec8_fp64_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp64_t +__spirv_ocl_sincos(__clc_vec8_fp64_t, __clc_vec8_fp64_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp64_t +__spirv_ocl_sincos(__clc_vec8_fp64_t, __clc_vec8_fp64_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp64_t +__spirv_ocl_sincos(__clc_vec16_fp64_t, __clc_vec16_fp64_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp64_t +__spirv_ocl_sincos(__clc_vec16_fp64_t, __clc_vec16_fp64_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp64_t +__spirv_ocl_sincos(__clc_vec16_fp64_t, __clc_vec16_fp64_t __global *); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL __clc_fp16_t __spirv_ocl_sincos(__clc_fp16_t, + __clc_fp16_t *); +_CLC_OVERLOAD _CLC_DECL __clc_fp16_t __spirv_ocl_sincos(__clc_fp16_t, + __clc_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_fp16_t +__spirv_ocl_sincos(__clc_fp16_t, __clc_fp16_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp16_t +__spirv_ocl_sincos(__clc_vec2_fp16_t, __clc_vec2_fp16_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp16_t +__spirv_ocl_sincos(__clc_vec2_fp16_t, __clc_vec2_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec2_fp16_t +__spirv_ocl_sincos(__clc_vec2_fp16_t, __clc_vec2_fp16_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp16_t +__spirv_ocl_sincos(__clc_vec3_fp16_t, __clc_vec3_fp16_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp16_t +__spirv_ocl_sincos(__clc_vec3_fp16_t, __clc_vec3_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec3_fp16_t +__spirv_ocl_sincos(__clc_vec3_fp16_t, __clc_vec3_fp16_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp16_t +__spirv_ocl_sincos(__clc_vec4_fp16_t, __clc_vec4_fp16_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp16_t +__spirv_ocl_sincos(__clc_vec4_fp16_t, __clc_vec4_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec4_fp16_t +__spirv_ocl_sincos(__clc_vec4_fp16_t, __clc_vec4_fp16_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp16_t +__spirv_ocl_sincos(__clc_vec8_fp16_t, __clc_vec8_fp16_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp16_t +__spirv_ocl_sincos(__clc_vec8_fp16_t, __clc_vec8_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec8_fp16_t +__spirv_ocl_sincos(__clc_vec8_fp16_t, __clc_vec8_fp16_t __global *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp16_t +__spirv_ocl_sincos(__clc_vec16_fp16_t, __clc_vec16_fp16_t *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp16_t +__spirv_ocl_sincos(__clc_vec16_fp16_t, __clc_vec16_fp16_t __local *); +_CLC_OVERLOAD _CLC_DECL __clc_vec16_fp16_t +__spirv_ocl_sincos(__clc_vec16_fp16_t, __clc_vec16_fp16_t __global *); +#endif + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_sinh(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_sinh(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_sinh(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_sinh(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_sinh(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_sinh(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_sinh(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_sinh(__clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_sinh(__clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_sinh(__clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_sinh(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_sinh(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_sinh(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_sinh(__clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_sinh(__clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_sinh(__clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_sinh(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_sinh(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_sinpi(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_sinpi(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_sinpi(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_sinpi(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_sinpi(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_sinpi(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_sinpi(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_sinpi(__clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_sinpi(__clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_sinpi(__clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_sinpi(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_sinpi(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_sinpi(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_sinpi(__clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_sinpi(__clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_sinpi(__clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_sinpi(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_sinpi(__clc_vec16_fp16_t); +#endif + _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_smoothstep(__clc_fp32_t, __clc_fp32_t, __clc_fp32_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t __spirv_ocl_smoothstep( @@ -14742,6 +18175,218 @@ _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t __spirv_ocl_step(__clc_vec16_fp16_t, __clc_vec16_fp16_t); #endif +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_tan(__clc_fp32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t __spirv_ocl_tan(__clc_vec2_fp32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t __spirv_ocl_tan(__clc_vec3_fp32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t __spirv_ocl_tan(__clc_vec4_fp32_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t __spirv_ocl_tan(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_tan(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_tan(__clc_fp64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t __spirv_ocl_tan(__clc_vec2_fp64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t __spirv_ocl_tan(__clc_vec3_fp64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t __spirv_ocl_tan(__clc_vec4_fp64_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t __spirv_ocl_tan(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_tan(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_tan(__clc_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t __spirv_ocl_tan(__clc_vec2_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t __spirv_ocl_tan(__clc_vec3_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t __spirv_ocl_tan(__clc_vec4_fp16_t); +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t __spirv_ocl_tan(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_tan(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_tanh(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_tanh(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_tanh(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_tanh(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_tanh(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_tanh(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_tanh(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_tanh(__clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_tanh(__clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_tanh(__clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_tanh(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_tanh(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_tanh(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_tanh(__clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_tanh(__clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_tanh(__clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_tanh(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_tanh(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_tanpi(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_tanpi(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_tanpi(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_tanpi(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_tanpi(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_tanpi(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_tanpi(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_tanpi(__clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_tanpi(__clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_tanpi(__clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_tanpi(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_tanpi(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_tanpi(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_tanpi(__clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_tanpi(__clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_tanpi(__clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_tanpi(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_tanpi(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_tgamma(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_tgamma(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_tgamma(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_tgamma(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_tgamma(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_tgamma(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_tgamma(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_tgamma(__clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_tgamma(__clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_tgamma(__clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_tgamma(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_tgamma(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_tgamma(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_tgamma(__clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_tgamma(__clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_tgamma(__clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_tgamma(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_tgamma(__clc_vec16_fp16_t); +#endif + +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp32_t __spirv_ocl_trunc(__clc_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp32_t + __spirv_ocl_trunc(__clc_vec2_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp32_t + __spirv_ocl_trunc(__clc_vec3_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp32_t + __spirv_ocl_trunc(__clc_vec4_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp32_t + __spirv_ocl_trunc(__clc_vec8_fp32_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp32_t + __spirv_ocl_trunc(__clc_vec16_fp32_t); + +#ifdef cl_khr_fp64 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp64_t __spirv_ocl_trunc(__clc_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp64_t + __spirv_ocl_trunc(__clc_vec2_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp64_t + __spirv_ocl_trunc(__clc_vec3_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp64_t + __spirv_ocl_trunc(__clc_vec4_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp64_t + __spirv_ocl_trunc(__clc_vec8_fp64_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp64_t + __spirv_ocl_trunc(__clc_vec16_fp64_t); +#endif + +#ifdef cl_khr_fp16 +_CLC_OVERLOAD +_CLC_DECL _CLC_CONSTFN __clc_fp16_t __spirv_ocl_trunc(__clc_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_fp16_t + __spirv_ocl_trunc(__clc_vec2_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec3_fp16_t + __spirv_ocl_trunc(__clc_vec3_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec4_fp16_t + __spirv_ocl_trunc(__clc_vec4_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec8_fp16_t + __spirv_ocl_trunc(__clc_vec8_fp16_t); +_CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec16_fp16_t + __spirv_ocl_trunc(__clc_vec16_fp16_t); +#endif + _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_uint8_t __spirv_ocl_u_abs(__clc_uint8_t); _CLC_OVERLOAD _CLC_DECL _CLC_CONSTFN __clc_vec2_uint8_t diff --git a/libclc/generic/lib/SOURCES b/libclc/generic/lib/SOURCES index 42fbb1dcbc69e..0a7558459be24 100644 --- a/libclc/generic/lib/SOURCES +++ b/libclc/generic/lib/SOURCES @@ -105,7 +105,6 @@ math/floor.cl math/fma.cl math/fmax.cl math/fmin.cl -math/clc_fmod.cl math/fmod.cl math/fract.cl math/frexp.cl @@ -123,7 +122,6 @@ math/half_rsqrt.cl math/half_sin.cl math/half_sqrt.cl math/half_tan.cl -math/clc_hypot.cl math/hypot.cl math/ilogb.cl math/ldexp.cl @@ -153,19 +151,13 @@ math/native_rsqrt.cl math/native_sin.cl math/native_sqrt.cl math/native_tan.cl -math/clc_nextafter.cl math/nextafter.cl math/pow.cl -math/clc_pown.cl math/pown.cl -math/clc_powr.cl math/powr.cl -math/clc_remainder.cl math/remainder.cl -math/clc_remquo.cl math/remquo.cl math/rint.cl -math/clc_rootn.cl math/rootn.cl math/round.cl math/rsqrt.cl diff --git a/libclc/generic/lib/math/clc_fmod.cl b/libclc/generic/lib/math/clc_fmod.cl deleted file mode 100644 index ea9f0e47e7aa0..0000000000000 --- a/libclc/generic/lib/math/clc_fmod.cl +++ /dev/null @@ -1,184 +0,0 @@ -/* - * Copyright (c) 2014 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include - -#include -#include "../clcmacro.h" -#include "config.h" -#include "math.h" - -_CLC_DEF _CLC_OVERLOAD float __clc_fmod(float x, float y) -{ - int ux = as_int(x); - int ax = ux & EXSIGNBIT_SP32; - float xa = as_float(ax); - int sx = ux ^ ax; - int ex = ax >> EXPSHIFTBITS_SP32; - - int uy = as_int(y); - int ay = uy & EXSIGNBIT_SP32; - float ya = as_float(ay); - int ey = ay >> EXPSHIFTBITS_SP32; - - float xr = as_float(0x3f800000 | (ax & 0x007fffff)); - float yr = as_float(0x3f800000 | (ay & 0x007fffff)); - int c; - int k = ex - ey; - - while (k > 0) { - c = xr >= yr; - xr -= c ? yr : 0.0f; - xr += xr; - --k; - } - - c = xr >= yr; - xr -= c ? yr : 0.0f; - - int lt = ex < ey; - - xr = lt ? xa : xr; - yr = lt ? ya : yr; - - - float s = as_float(ey << EXPSHIFTBITS_SP32); - xr *= lt ? 1.0f : s; - - c = ax == ay; - xr = c ? 0.0f : xr; - - xr = as_float(sx ^ as_int(xr)); - - c = ax > PINFBITPATT_SP32 | ay > PINFBITPATT_SP32 | ax == PINFBITPATT_SP32 | ay == 0; - xr = c ? as_float(QNANBITPATT_SP32) : xr; - - return xr; - -} -_CLC_BINARY_VECTORIZE(_CLC_DEF _CLC_OVERLOAD, float, __clc_fmod, float, float); - -#ifdef cl_khr_fp64 -_CLC_DEF _CLC_OVERLOAD double __clc_fmod(double x, double y) -{ - ulong ux = as_ulong(x); - ulong ax = ux & ~SIGNBIT_DP64; - ulong xsgn = ux ^ ax; - double dx = as_double(ax); - int xexp = convert_int(ax >> EXPSHIFTBITS_DP64); - int xexp1 = 11 - (int) clz(ax & MANTBITS_DP64); - xexp1 = xexp < 1 ? xexp1 : xexp; - - ulong uy = as_ulong(y); - ulong ay = uy & ~SIGNBIT_DP64; - double dy = as_double(ay); - int yexp = convert_int(ay >> EXPSHIFTBITS_DP64); - int yexp1 = 11 - (int) clz(ay & MANTBITS_DP64); - yexp1 = yexp < 1 ? yexp1 : yexp; - - // First assume |x| > |y| - - // Set ntimes to the number of times we need to do a - // partial remainder. If the exponent of x is an exact multiple - // of 53 larger than the exponent of y, and the mantissa of x is - // less than the mantissa of y, ntimes will be one too large - // but it doesn't matter - it just means that we'll go round - // the loop below one extra time. - int ntimes = max(0, (xexp1 - yexp1) / 53); - double w = ldexp(dy, ntimes * 53); - w = ntimes == 0 ? dy : w; - double scale = ntimes == 0 ? 1.0 : 0x1.0p-53; - - // Each time round the loop we compute a partial remainder. - // This is done by subtracting a large multiple of w - // from x each time, where w is a scaled up version of y. - // The subtraction must be performed exactly in quad - // precision, though the result at each stage can - // fit exactly in a double precision number. - int i; - double t, v, p, pp; - - for (i = 0; i < ntimes; i++) { - // Compute integral multiplier - t = trunc(dx / w); - - // Compute w * t in quad precision - p = w * t; - pp = fma(w, t, -p); - - // Subtract w * t from dx - v = dx - p; - dx = v + (((dx - v) - p) - pp); - - // If t was one too large, dx will be negative. Add back one w. - dx += dx < 0.0 ? w : 0.0; - - // Scale w down by 2^(-53) for the next iteration - w *= scale; - } - - // One more time - // Variable todd says whether the integer t is odd or not - t = floor(dx / w); - long lt = (long)t; - int todd = lt & 1; - - p = w * t; - pp = fma(w, t, -p); - v = dx - p; - dx = v + (((dx - v) - p) - pp); - i = dx < 0.0; - todd ^= i; - dx += i ? w : 0.0; - - // At this point, dx lies in the range [0,dy) - double ret = as_double(xsgn ^ as_ulong(dx)); - dx = as_double(ax); - - // Now handle |x| == |y| - int c = dx == dy; - t = as_double(xsgn); - ret = c ? t : ret; - - // Next, handle |x| < |y| - c = dx < dy; - ret = c ? x : ret; - - // We don't need anything special for |x| == 0 - - // |y| is 0 - c = dy == 0.0; - ret = c ? as_double(QNANBITPATT_DP64) : ret; - - // y is +-Inf, NaN - c = yexp > BIASEDEMAX_DP64; - t = y == y ? x : y; - ret = c ? t : ret; - - // x is +=Inf, NaN - c = xexp > BIASEDEMAX_DP64; - ret = c ? as_double(QNANBITPATT_DP64) : ret; - - return ret; -} -_CLC_BINARY_VECTORIZE(_CLC_DEF _CLC_OVERLOAD, double, __clc_fmod, double, double); -#endif diff --git a/libclc/generic/lib/math/clc_nextafter.cl b/libclc/generic/lib/math/clc_nextafter.cl deleted file mode 100644 index d32ef7079e115..0000000000000 --- a/libclc/generic/lib/math/clc_nextafter.cl +++ /dev/null @@ -1,46 +0,0 @@ -#include -#include "../clcmacro.h" - -// This file provides OpenCL C implementations of nextafter for -// targets that don't support the clang builtin. - -#define AS_TYPE(x) as_##x - -#define NEXTAFTER(FLOAT_TYPE, UINT_TYPE, INT_TYPE) \ -_CLC_OVERLOAD _CLC_DEF FLOAT_TYPE __clc_nextafter(FLOAT_TYPE x, FLOAT_TYPE y) { \ - const UINT_TYPE sign_bit \ - = (UINT_TYPE)1 << (sizeof(INT_TYPE) * 8 - 1); \ - const UINT_TYPE sign_bit_mask = sign_bit - 1; \ - INT_TYPE ix = AS_TYPE(INT_TYPE)(x); \ - INT_TYPE ax = ix & sign_bit_mask; \ - INT_TYPE mx = sign_bit - ix; \ - mx = ix < 0 ? mx : ix; \ - INT_TYPE iy = AS_TYPE(INT_TYPE)(y); \ - INT_TYPE ay = iy & sign_bit_mask; \ - INT_TYPE my = sign_bit - iy; \ - my = iy < 0 ? my : iy; \ - INT_TYPE t = mx + (mx < my ? 1 : -1); \ - INT_TYPE r = sign_bit - t; \ - r = t < 0 ? r : t; \ - r = isnan(x) ? ix : r; \ - r = isnan(y) ? iy : r; \ - r = ((ax | ay) == 0 | ix == iy) ? iy : r; \ - return AS_TYPE(FLOAT_TYPE)(r); \ -} - -NEXTAFTER(float, uint, int) -_CLC_BINARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, float, __clc_nextafter, float, float) - -#ifdef cl_khr_fp64 -#pragma OPENCL EXTENSION cl_khr_fp64 : enable - -NEXTAFTER(double, ulong, long) -_CLC_BINARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, double, __clc_nextafter, double, double) -#endif - -#ifdef cl_khr_fp16 -#pragma OPENCL EXTENSION cl_khr_fp16 : enable - -NEXTAFTER(half, ushort, short) -_CLC_BINARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, half, __clc_nextafter, half, half) -#endif diff --git a/libclc/generic/lib/math/clc_pown.cl b/libclc/generic/lib/math/clc_pown.cl deleted file mode 100644 index ef630126d12eb..0000000000000 --- a/libclc/generic/lib/math/clc_pown.cl +++ /dev/null @@ -1,370 +0,0 @@ -/* - * Copyright (c) 2014 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include - -#include "config.h" -#include "math.h" -#include "../../libspirv/math/tables.h" -#include "../clcmacro.h" - -// compute pow using log and exp -// x^y = exp(y * log(x)) -// -// we take care not to lose precision in the intermediate steps -// -// When computing log, calculate it in splits, -// -// r = f * (p_invead + p_inv_tail) -// r = rh + rt -// -// calculate log polynomial using r, in end addition, do -// poly = poly + ((rh-r) + rt) -// -// lth = -r -// ltt = ((xexp * log2_t) - poly) + logT -// lt = lth + ltt -// -// lh = (xexp * log2_h) + logH -// l = lh + lt -// -// Calculate final log answer as gh and gt, -// gh = l & higher-half bits -// gt = (((ltt - (lt - lth)) + ((lh - l) + lt)) + (l - gh)) -// -// yh = y & higher-half bits -// yt = y - yh -// -// Before entering computation of exp, -// vs = ((yt*gt + yt*gh) + yh*gt) -// v = vs + yh*gh -// vt = ((yh*gh - v) + vs) -// -// In calculation of exp, add vt to r that is used for poly -// At the end of exp, do -// ((((expT * poly) + expT) + expH*poly) + expH) - -_CLC_DEF _CLC_OVERLOAD float __clc_pown(float x, int ny) -{ - float y = (float)ny; - - int ix = as_int(x); - int ax = ix & EXSIGNBIT_SP32; - int xpos = ix == ax; - - int iy = as_int(y); - int ay = iy & EXSIGNBIT_SP32; - int ypos = iy == ay; - - // Extra precise log calculation - // First handle case that x is close to 1 - float r = 1.0f - as_float(ax); - int near1 = fabs(r) < 0x1.0p-4f; - float r2 = r*r; - - // Coefficients are just 1/3, 1/4, 1/5 and 1/6 - float poly = mad(r, - mad(r, - mad(r, - mad(r, 0x1.24924ap-3f, 0x1.555556p-3f), - 0x1.99999ap-3f), - 0x1.000000p-2f), - 0x1.555556p-2f); - - poly *= r2*r; - - float lth_near1 = -r2 * 0.5f; - float ltt_near1 = -poly; - float lt_near1 = lth_near1 + ltt_near1; - float lh_near1 = -r; - float l_near1 = lh_near1 + lt_near1; - - // Computations for x not near 1 - int m = (int)(ax >> EXPSHIFTBITS_SP32) - EXPBIAS_SP32; - float mf = (float)m; - int ixs = as_int(as_float(ax | 0x3f800000) - 1.0f); - float mfs = (float)((ixs >> EXPSHIFTBITS_SP32) - 253); - int c = m == -127; - int ixn = c ? ixs : ax; - float mfn = c ? mfs : mf; - - int indx = (ixn & 0x007f0000) + ((ixn & 0x00008000) << 1); - - // F - Y - float f = as_float(0x3f000000 | indx) - as_float(0x3f000000 | (ixn & MANTBITS_SP32)); - - indx = indx >> 16; - float2 tv = USE_TABLE(log_inv_tbl_ep, indx); - float rh = f * tv.s0; - float rt = f * tv.s1; - r = rh + rt; - - poly = mad(r, mad(r, 0x1.0p-2f, 0x1.555556p-2f), 0x1.0p-1f) * (r*r); - poly += (rh - r) + rt; - - const float LOG2_HEAD = 0x1.62e000p-1f; // 0.693115234 - const float LOG2_TAIL = 0x1.0bfbe8p-15f; // 0.0000319461833 - tv = USE_TABLE(loge_tbl, indx); - float lth = -r; - float ltt = mad(mfn, LOG2_TAIL, -poly) + tv.s1; - float lt = lth + ltt; - float lh = mad(mfn, LOG2_HEAD, tv.s0); - float l = lh + lt; - - // Select near 1 or not - lth = near1 ? lth_near1 : lth; - ltt = near1 ? ltt_near1 : ltt; - lt = near1 ? lt_near1 : lt; - lh = near1 ? lh_near1 : lh; - l = near1 ? l_near1 : l; - - float gh = as_float(as_int(l) & 0xfffff000); - float gt = ((ltt - (lt - lth)) + ((lh - l) + lt)) + (l - gh); - - float yh = as_float(iy & 0xfffff000); - - float yt = (float)(ny - (int)yh); - - float ylogx_s = mad(gt, yh, mad(gh, yt, yt*gt)); - float ylogx = mad(yh, gh, ylogx_s); - float ylogx_t = mad(yh, gh, -ylogx) + ylogx_s; - - // Extra precise exp of ylogx - const float R_64_BY_LOG2 = 0x1.715476p+6f; // 64/log2 : 92.332482616893657 - int n = convert_int(ylogx * R_64_BY_LOG2); - float nf = (float) n; - - int j = n & 0x3f; - m = n >> 6; - int m2 = m << EXPSHIFTBITS_SP32; - - const float R_LOG2_BY_64_LD = 0x1.620000p-7f; // log2/64 lead: 0.0108032227 - const float R_LOG2_BY_64_TL = 0x1.c85fdep-16f; // log2/64 tail: 0.0000272020388 - r = mad(nf, -R_LOG2_BY_64_TL, mad(nf, -R_LOG2_BY_64_LD, ylogx)) + ylogx_t; - - // Truncated Taylor series for e^r - poly = mad(mad(mad(r, 0x1.555556p-5f, 0x1.555556p-3f), r, 0x1.000000p-1f), r*r, r); - - tv = USE_TABLE(exp_tbl_ep, j); - - float expylogx = mad(tv.s0, poly, mad(tv.s1, poly, tv.s1)) + tv.s0; - float sexpylogx = expylogx * as_float(0x1 << (m + 149)); - float texpylogx = as_float(as_int(expylogx) + m2); - expylogx = m < -125 ? sexpylogx : texpylogx; - - // Result is +-Inf if (ylogx + ylogx_t) > 128*log2 - expylogx = ((ylogx > 0x1.62e430p+6f) | (ylogx == 0x1.62e430p+6f & ylogx_t > -0x1.05c610p-22f)) ? as_float(PINFBITPATT_SP32) : expylogx; - - // Result is 0 if ylogx < -149*log2 - expylogx = ylogx < -0x1.9d1da0p+6f ? 0.0f : expylogx; - - // Classify y: - // inty = 0 means not an integer. - // inty = 1 means odd integer. - // inty = 2 means even integer. - - int inty = 2 - (ny & 1); - - float signval = as_float((as_uint(expylogx) ^ SIGNBIT_SP32)); - expylogx = ((inty == 1) & !xpos) ? signval : expylogx; - int ret = as_int(expylogx); - - // Corner case handling - int xinf = xpos ? PINFBITPATT_SP32 : NINFBITPATT_SP32; - ret = ((ax == 0) & !ypos & (inty == 1)) ? xinf : ret; - ret = ((ax == 0) & !ypos & (inty == 2)) ? PINFBITPATT_SP32 : ret; - ret = ((ax == 0) & ypos & (inty == 2)) ? 0 : ret; - int xzero = !xpos ? 0x80000000 : 0L; - ret = ((ax == 0) & ypos & (inty == 1)) ? xzero : ret; - ret = ((ix == NINFBITPATT_SP32) & !ypos & (inty == 1)) ? 0x80000000 : ret; - ret = ((ix == NINFBITPATT_SP32) & !ypos & (inty != 1)) ? 0 : ret; - ret = ((ix == NINFBITPATT_SP32) & ypos & (inty == 1)) ? NINFBITPATT_SP32 : ret; - ret = ((ix == NINFBITPATT_SP32) & ypos & (inty != 1)) ? PINFBITPATT_SP32 : ret; - ret = ((ix == PINFBITPATT_SP32) & !ypos) ? 0 : ret; - ret = ((ix == PINFBITPATT_SP32) & ypos) ? PINFBITPATT_SP32 : ret; - ret = ax > PINFBITPATT_SP32 ? ix : ret; - ret = ny == 0 ? 0x3f800000 : ret; - - return as_float(ret); -} -_CLC_BINARY_VECTORIZE(_CLC_DEF _CLC_OVERLOAD, float, __clc_pown, float, int) - -#ifdef cl_khr_fp64 -_CLC_DEF _CLC_OVERLOAD double __clc_pown(double x, int ny) -{ - const double real_log2_tail = 5.76999904754328540596e-08; - const double real_log2_lead = 6.93147122859954833984e-01; - - double y = (double) ny; - - long ux = as_long(x); - long ax = ux & (~SIGNBIT_DP64); - int xpos = ax == ux; - - long uy = as_long(y); - long ay = uy & (~SIGNBIT_DP64); - int ypos = ay == uy; - - // Extended precision log - double v, vt; - { - int exp = (int)(ax >> 52) - 1023; - int mask_exp_1023 = exp == -1023; - double xexp = (double) exp; - long mantissa = ax & 0x000FFFFFFFFFFFFFL; - - long temp_ux = as_long(as_double(0x3ff0000000000000L | mantissa) - 1.0); - exp = ((temp_ux & 0x7FF0000000000000L) >> 52) - 2045; - double xexp1 = (double) exp; - long mantissa1 = temp_ux & 0x000FFFFFFFFFFFFFL; - - xexp = mask_exp_1023 ? xexp1 : xexp; - mantissa = mask_exp_1023 ? mantissa1 : mantissa; - - long rax = (mantissa & 0x000ff00000000000) + ((mantissa & 0x0000080000000000) << 1); - int index = rax >> 44; - - double F = as_double(rax | 0x3FE0000000000000L); - double Y = as_double(mantissa | 0x3FE0000000000000L); - double f = F - Y; - double2 tv = USE_TABLE(log_f_inv_tbl, index); - double log_h = tv.s0; - double log_t = tv.s1; - double f_inv = (log_h + log_t) * f; - double r1 = as_double(as_long(f_inv) & 0xfffffffff8000000L); - double r2 = fma(-F, r1, f) * (log_h + log_t); - double r = r1 + r2; - - double poly = fma(r, - fma(r, - fma(r, - fma(r, 1.0/7.0, 1.0/6.0), - 1.0/5.0), - 1.0/4.0), - 1.0/3.0); - poly = poly * r * r * r; - - double hr1r1 = 0.5*r1*r1; - double poly0h = r1 + hr1r1; - double poly0t = r1 - poly0h + hr1r1; - poly = fma(r1, r2, fma(0.5*r2, r2, poly)) + r2 + poly0t; - - tv = USE_TABLE(powlog_tbl, index); - log_h = tv.s0; - log_t = tv.s1; - - double resT_t = fma(xexp, real_log2_tail, + log_t) - poly; - double resT = resT_t - poly0h; - double resH = fma(xexp, real_log2_lead, log_h); - double resT_h = poly0h; - - double H = resT + resH; - double H_h = as_double(as_long(H) & 0xfffffffff8000000L); - double T = (resH - H + resT) + (resT_t - (resT + resT_h)) + (H - H_h); - H = H_h; - - double y_head = as_double(uy & 0xfffffffff8000000L); - double y_tail = y - y_head; - - int mask_2_24 = ay > 0x4170000000000000; // 2^24 - int nyh = convert_int(y_head); - int nyt = ny - nyh; - double y_tail1 = (double)nyt; - y_tail = mask_2_24 ? y_tail1 : y_tail; - - double temp = fma(y_tail, H, fma(y_head, T, y_tail*T)); - v = fma(y_head, H, temp); - vt = fma(y_head, H, -v) + temp; - } - - // Now calculate exp of (v,vt) - - double expv; - { - const double max_exp_arg = 709.782712893384; - const double min_exp_arg = -745.1332191019411; - const double sixtyfour_by_lnof2 = 92.33248261689366; - const double lnof2_by_64_head = 0.010830424260348081; - const double lnof2_by_64_tail = -4.359010638708991e-10; - - double temp = v * sixtyfour_by_lnof2; - int n = (int)temp; - double dn = (double)n; - int j = n & 0x0000003f; - int m = n >> 6; - - double2 tv = USE_TABLE(two_to_jby64_ep_tbl, j); - double f1 = tv.s0; - double f2 = tv.s1; - double f = f1 + f2; - - double r1 = fma(dn, -lnof2_by_64_head, v); - double r2 = dn * lnof2_by_64_tail; - double r = (r1 + r2) + vt; - - double q = fma(r, - fma(r, - fma(r, - fma(r, 1.38889490863777199667e-03, 8.33336798434219616221e-03), - 4.16666666662260795726e-02), - 1.66666666665260878863e-01), - 5.00000000000000008883e-01); - q = fma(r*r, q, r); - - expv = fma(f, q, f2) + f1; - expv = ldexp(expv, m); - - expv = v > max_exp_arg ? as_double(0x7FF0000000000000L) : expv; - expv = v < min_exp_arg ? 0.0 : expv; - } - - // See whether y is an integer. - // inty = 0 means not an integer. - // inty = 1 means odd integer. - // inty = 2 means even integer. - - int inty = 2 - (ny & 1); - - expv *= ((inty == 1) & !xpos) ? -1.0 : 1.0; - - long ret = as_long(expv); - - // Now all the edge cases - long xinf = xpos ? PINFBITPATT_DP64 : NINFBITPATT_DP64; - ret = ((ax == 0L) & !ypos & (inty == 1)) ? xinf : ret; - ret = ((ax == 0L) & !ypos & (inty == 2)) ? PINFBITPATT_DP64 : ret; - ret = ((ax == 0L) & ypos & (inty == 2)) ? 0L : ret; - long xzero = !xpos ? 0x8000000000000000L : 0L; - ret = ((ax == 0L) & ypos & (inty == 1)) ? xzero : ret; - ret = ((ux == NINFBITPATT_DP64) & !ypos & (inty == 1)) ? 0x8000000000000000L : ret; - ret = ((ux == NINFBITPATT_DP64) & !ypos & (inty != 1)) ? 0L : ret; - ret = ((ux == NINFBITPATT_DP64) & ypos & (inty == 1)) ? NINFBITPATT_DP64 : ret; - ret = ((ux == NINFBITPATT_DP64) & ypos & (inty != 1)) ? PINFBITPATT_DP64 : ret; - ret = ((ux == PINFBITPATT_DP64) & !ypos) ? 0L : ret; - ret = ((ux == PINFBITPATT_DP64) & ypos) ? PINFBITPATT_DP64 : ret; - ret = ax > PINFBITPATT_DP64 ? ux : ret; - ret = ny == 0 ? 0x3ff0000000000000L : ret; - - return as_double(ret); -} -_CLC_BINARY_VECTORIZE(_CLC_DEF _CLC_OVERLOAD, double, __clc_pown, double, int) -#endif diff --git a/libclc/generic/lib/math/clc_powr.cl b/libclc/generic/lib/math/clc_powr.cl deleted file mode 100644 index 9087401a29ba9..0000000000000 --- a/libclc/generic/lib/math/clc_powr.cl +++ /dev/null @@ -1,381 +0,0 @@ -/* - * Copyright (c) 2014 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include - -#include "config.h" -#include "math.h" -#include "../../libspirv/math/tables.h" -#include "../clcmacro.h" - -// compute pow using log and exp -// x^y = exp(y * log(x)) -// -// we take care not to lose precision in the intermediate steps -// -// When computing log, calculate it in splits, -// -// r = f * (p_invead + p_inv_tail) -// r = rh + rt -// -// calculate log polynomial using r, in end addition, do -// poly = poly + ((rh-r) + rt) -// -// lth = -r -// ltt = ((xexp * log2_t) - poly) + logT -// lt = lth + ltt -// -// lh = (xexp * log2_h) + logH -// l = lh + lt -// -// Calculate final log answer as gh and gt, -// gh = l & higher-half bits -// gt = (((ltt - (lt - lth)) + ((lh - l) + lt)) + (l - gh)) -// -// yh = y & higher-half bits -// yt = y - yh -// -// Before entering computation of exp, -// vs = ((yt*gt + yt*gh) + yh*gt) -// v = vs + yh*gh -// vt = ((yh*gh - v) + vs) -// -// In calculation of exp, add vt to r that is used for poly -// At the end of exp, do -// ((((expT * poly) + expT) + expH*poly) + expH) - -_CLC_DEF _CLC_OVERLOAD float __clc_powr(float x, float y) -{ - int ix = as_int(x); - int ax = ix & EXSIGNBIT_SP32; - int xpos = ix == ax; - - int iy = as_int(y); - int ay = iy & EXSIGNBIT_SP32; - int ypos = iy == ay; - - // Extra precise log calculation - // First handle case that x is close to 1 - float r = 1.0f - as_float(ax); - int near1 = fabs(r) < 0x1.0p-4f; - float r2 = r*r; - - // Coefficients are just 1/3, 1/4, 1/5 and 1/6 - float poly = mad(r, - mad(r, - mad(r, - mad(r, 0x1.24924ap-3f, 0x1.555556p-3f), - 0x1.99999ap-3f), - 0x1.000000p-2f), - 0x1.555556p-2f); - - poly *= r2*r; - - float lth_near1 = -r2 * 0.5f; - float ltt_near1 = -poly; - float lt_near1 = lth_near1 + ltt_near1; - float lh_near1 = -r; - float l_near1 = lh_near1 + lt_near1; - - // Computations for x not near 1 - int m = (int)(ax >> EXPSHIFTBITS_SP32) - EXPBIAS_SP32; - float mf = (float)m; - int ixs = as_int(as_float(ax | 0x3f800000) - 1.0f); - float mfs = (float)((ixs >> EXPSHIFTBITS_SP32) - 253); - int c = m == -127; - int ixn = c ? ixs : ax; - float mfn = c ? mfs : mf; - - int indx = (ixn & 0x007f0000) + ((ixn & 0x00008000) << 1); - - // F - Y - float f = as_float(0x3f000000 | indx) - as_float(0x3f000000 | (ixn & MANTBITS_SP32)); - - indx = indx >> 16; - float2 tv = USE_TABLE(log_inv_tbl_ep, indx); - float rh = f * tv.s0; - float rt = f * tv.s1; - r = rh + rt; - - poly = mad(r, mad(r, 0x1.0p-2f, 0x1.555556p-2f), 0x1.0p-1f) * (r*r); - poly += (rh - r) + rt; - - const float LOG2_HEAD = 0x1.62e000p-1f; // 0.693115234 - const float LOG2_TAIL = 0x1.0bfbe8p-15f; // 0.0000319461833 - tv = USE_TABLE(loge_tbl, indx); - float lth = -r; - float ltt = mad(mfn, LOG2_TAIL, -poly) + tv.s1; - float lt = lth + ltt; - float lh = mad(mfn, LOG2_HEAD, tv.s0); - float l = lh + lt; - - // Select near 1 or not - lth = near1 ? lth_near1 : lth; - ltt = near1 ? ltt_near1 : ltt; - lt = near1 ? lt_near1 : lt; - lh = near1 ? lh_near1 : lh; - l = near1 ? l_near1 : l; - - float gh = as_float(as_int(l) & 0xfffff000); - float gt = ((ltt - (lt - lth)) + ((lh - l) + lt)) + (l - gh); - - float yh = as_float(iy & 0xfffff000); - - float yt = y - yh; - - float ylogx_s = mad(gt, yh, mad(gh, yt, yt*gt)); - float ylogx = mad(yh, gh, ylogx_s); - float ylogx_t = mad(yh, gh, -ylogx) + ylogx_s; - - // Extra precise exp of ylogx - const float R_64_BY_LOG2 = 0x1.715476p+6f; // 64/log2 : 92.332482616893657 - int n = convert_int(ylogx * R_64_BY_LOG2); - float nf = (float) n; - - int j = n & 0x3f; - m = n >> 6; - int m2 = m << EXPSHIFTBITS_SP32; - - const float R_LOG2_BY_64_LD = 0x1.620000p-7f; // log2/64 lead: 0.0108032227 - const float R_LOG2_BY_64_TL = 0x1.c85fdep-16f; // log2/64 tail: 0.0000272020388 - r = mad(nf, -R_LOG2_BY_64_TL, mad(nf, -R_LOG2_BY_64_LD, ylogx)) + ylogx_t; - - // Truncated Taylor series for e^r - poly = mad(mad(mad(r, 0x1.555556p-5f, 0x1.555556p-3f), r, 0x1.000000p-1f), r*r, r); - - tv = USE_TABLE(exp_tbl_ep, j); - - float expylogx = mad(tv.s0, poly, mad(tv.s1, poly, tv.s1)) + tv.s0; - float sexpylogx = expylogx * as_float(0x1 << (m + 149)); - float texpylogx = as_float(as_int(expylogx) + m2); - expylogx = m < -125 ? sexpylogx : texpylogx; - - // Result is +-Inf if (ylogx + ylogx_t) > 128*log2 - expylogx = ((ylogx > 0x1.62e430p+6f) | (ylogx == 0x1.62e430p+6f & ylogx_t > -0x1.05c610p-22f)) ? as_float(PINFBITPATT_SP32) : expylogx; - - // Result is 0 if ylogx < -149*log2 - expylogx = ylogx < -0x1.9d1da0p+6f ? 0.0f : expylogx; - - // Classify y: - // inty = 0 means not an integer. - // inty = 1 means odd integer. - // inty = 2 means even integer. - - int yexp = (int)(ay >> EXPSHIFTBITS_SP32) - EXPBIAS_SP32 + 1; - int mask = (1 << (24 - yexp)) - 1; - int yodd = ((iy >> (24 - yexp)) & 0x1) != 0; - int inty = yodd ? 1 : 2; - inty = (iy & mask) != 0 ? 0 : inty; - inty = yexp < 1 ? 0 : inty; - inty = yexp > 24 ? 2 : inty; - - float signval = as_float((as_uint(expylogx) ^ SIGNBIT_SP32)); - expylogx = ((inty == 1) & !xpos) ? signval : expylogx; - int ret = as_int(expylogx); - - // Corner case handling - ret = ax < 0x3f800000 & iy == NINFBITPATT_SP32 ? PINFBITPATT_SP32 : ret; - ret = ax < 0x3f800000 & iy == PINFBITPATT_SP32 ? 0 : ret; - ret = ax == 0x3f800000 & ay < PINFBITPATT_SP32 ? 0x3f800000 : ret; - ret = ax == 0x3f800000 & ay == PINFBITPATT_SP32 ? QNANBITPATT_SP32 : ret; - ret = ax > 0x3f800000 & iy == NINFBITPATT_SP32 ? 0 : ret; - ret = ax > 0x3f800000 & iy == PINFBITPATT_SP32 ? PINFBITPATT_SP32 : ret; - ret = ((ix < PINFBITPATT_SP32) & (ay == 0)) ? 0x3f800000 : ret; - ret = ((ax == PINFBITPATT_SP32) & !ypos) ? 0 : ret; - ret = ((ax == PINFBITPATT_SP32) & ypos) ? PINFBITPATT_SP32 : ret; - ret = ((ax == PINFBITPATT_SP32) & (iy == PINFBITPATT_SP32)) ? PINFBITPATT_SP32 : ret; - ret = ((ax == PINFBITPATT_SP32) & (ay == 0)) ? QNANBITPATT_SP32 : ret; - ret = ((ax == 0) & !ypos) ? PINFBITPATT_SP32 : ret; - ret = ((ax == 0) & ypos) ? 0 : ret; - ret = ((ax == 0) & (ay == 0)) ? QNANBITPATT_SP32 : ret; - ret = ((ax != 0) & !xpos) ? QNANBITPATT_SP32 : ret; - ret = ax > PINFBITPATT_SP32 ? ix : ret; - ret = ay > PINFBITPATT_SP32 ? iy : ret; - - return as_float(ret); -} -_CLC_BINARY_VECTORIZE(_CLC_DEF _CLC_OVERLOAD, float, __clc_powr, float, float) - -#ifdef cl_khr_fp64 -_CLC_DEF _CLC_OVERLOAD double __clc_powr(double x, double y) -{ - const double real_log2_tail = 5.76999904754328540596e-08; - const double real_log2_lead = 6.93147122859954833984e-01; - - long ux = as_long(x); - long ax = ux & (~SIGNBIT_DP64); - int xpos = ax == ux; - - long uy = as_long(y); - long ay = uy & (~SIGNBIT_DP64); - int ypos = ay == uy; - - // Extended precision log - double v, vt; - { - int exp = (int)(ax >> 52) - 1023; - int mask_exp_1023 = exp == -1023; - double xexp = (double) exp; - long mantissa = ax & 0x000FFFFFFFFFFFFFL; - - long temp_ux = as_long(as_double(0x3ff0000000000000L | mantissa) - 1.0); - exp = ((temp_ux & 0x7FF0000000000000L) >> 52) - 2045; - double xexp1 = (double) exp; - long mantissa1 = temp_ux & 0x000FFFFFFFFFFFFFL; - - xexp = mask_exp_1023 ? xexp1 : xexp; - mantissa = mask_exp_1023 ? mantissa1 : mantissa; - - long rax = (mantissa & 0x000ff00000000000) + ((mantissa & 0x0000080000000000) << 1); - int index = rax >> 44; - - double F = as_double(rax | 0x3FE0000000000000L); - double Y = as_double(mantissa | 0x3FE0000000000000L); - double f = F - Y; - double2 tv = USE_TABLE(log_f_inv_tbl, index); - double log_h = tv.s0; - double log_t = tv.s1; - double f_inv = (log_h + log_t) * f; - double r1 = as_double(as_long(f_inv) & 0xfffffffff8000000L); - double r2 = fma(-F, r1, f) * (log_h + log_t); - double r = r1 + r2; - - double poly = fma(r, - fma(r, - fma(r, - fma(r, 1.0/7.0, 1.0/6.0), - 1.0/5.0), - 1.0/4.0), - 1.0/3.0); - poly = poly * r * r * r; - - double hr1r1 = 0.5*r1*r1; - double poly0h = r1 + hr1r1; - double poly0t = r1 - poly0h + hr1r1; - poly = fma(r1, r2, fma(0.5*r2, r2, poly)) + r2 + poly0t; - - tv = USE_TABLE(powlog_tbl, index); - log_h = tv.s0; - log_t = tv.s1; - - double resT_t = fma(xexp, real_log2_tail, + log_t) - poly; - double resT = resT_t - poly0h; - double resH = fma(xexp, real_log2_lead, log_h); - double resT_h = poly0h; - - double H = resT + resH; - double H_h = as_double(as_long(H) & 0xfffffffff8000000L); - double T = (resH - H + resT) + (resT_t - (resT + resT_h)) + (H - H_h); - H = H_h; - - double y_head = as_double(uy & 0xfffffffff8000000L); - double y_tail = y - y_head; - - double temp = fma(y_tail, H, fma(y_head, T, y_tail*T)); - v = fma(y_head, H, temp); - vt = fma(y_head, H, -v) + temp; - } - - // Now calculate exp of (v,vt) - - double expv; - { - const double max_exp_arg = 709.782712893384; - const double min_exp_arg = -745.1332191019411; - const double sixtyfour_by_lnof2 = 92.33248261689366; - const double lnof2_by_64_head = 0.010830424260348081; - const double lnof2_by_64_tail = -4.359010638708991e-10; - - double temp = v * sixtyfour_by_lnof2; - int n = (int)temp; - double dn = (double)n; - int j = n & 0x0000003f; - int m = n >> 6; - - double2 tv = USE_TABLE(two_to_jby64_ep_tbl, j); - double f1 = tv.s0; - double f2 = tv.s1; - double f = f1 + f2; - - double r1 = fma(dn, -lnof2_by_64_head, v); - double r2 = dn * lnof2_by_64_tail; - double r = (r1 + r2) + vt; - - double q = fma(r, - fma(r, - fma(r, - fma(r, 1.38889490863777199667e-03, 8.33336798434219616221e-03), - 4.16666666662260795726e-02), - 1.66666666665260878863e-01), - 5.00000000000000008883e-01); - q = fma(r*r, q, r); - - expv = fma(f, q, f2) + f1; - expv = ldexp(expv, m); - - expv = v > max_exp_arg ? as_double(0x7FF0000000000000L) : expv; - expv = v < min_exp_arg ? 0.0 : expv; - } - - // See whether y is an integer. - // inty = 0 means not an integer. - // inty = 1 means odd integer. - // inty = 2 means even integer. - - int inty; - { - int yexp = (int)(ay >> EXPSHIFTBITS_DP64) - EXPBIAS_DP64 + 1; - inty = yexp < 1 ? 0 : 2; - inty = yexp > 53 ? 2 : inty; - long mask = (1L << (53 - yexp)) - 1L; - int inty1 = (((ay & ~mask) >> (53 - yexp)) & 1L) == 1L ? 1 : 2; - inty1 = (ay & mask) != 0 ? 0 : inty1; - inty = !(yexp < 1) & !(yexp > 53) ? inty1 : inty; - } - - expv *= ((inty == 1) & !xpos) ? -1.0 : 1.0; - - long ret = as_long(expv); - - // Now all the edge cases - ret = ax < 0x3ff0000000000000L & uy == NINFBITPATT_DP64 ? PINFBITPATT_DP64 : ret; - ret = ax < 0x3ff0000000000000L & uy == PINFBITPATT_DP64 ? 0L : ret; - ret = ax == 0x3ff0000000000000L & ay < PINFBITPATT_DP64 ? 0x3ff0000000000000L : ret; - ret = ax == 0x3ff0000000000000L & ay == PINFBITPATT_DP64 ? QNANBITPATT_DP64 : ret; - ret = ax > 0x3ff0000000000000L & uy == NINFBITPATT_DP64 ? 0L : ret; - ret = ax > 0x3ff0000000000000L & uy == PINFBITPATT_DP64 ? PINFBITPATT_DP64 : ret; - ret = ux < PINFBITPATT_DP64 & ay == 0L ? 0x3ff0000000000000L : ret; - ret = ((ax == PINFBITPATT_DP64) & !ypos) ? 0L : ret; - ret = ((ax == PINFBITPATT_DP64) & ypos) ? PINFBITPATT_DP64 : ret; - ret = ((ax == PINFBITPATT_DP64) & (uy == PINFBITPATT_DP64)) ? PINFBITPATT_DP64 : ret; - ret = ((ax == PINFBITPATT_DP64) & (ay == 0L)) ? QNANBITPATT_DP64 : ret; - ret = ((ax == 0L) & !ypos) ? PINFBITPATT_DP64 : ret; - ret = ((ax == 0L) & ypos) ? 0L : ret; - ret = ((ax == 0L) & (ay == 0L)) ? QNANBITPATT_DP64 : ret; - ret = ((ax != 0L) & !xpos) ? QNANBITPATT_DP64 : ret; - ret = ax > PINFBITPATT_DP64 ? ux : ret; - ret = ay > PINFBITPATT_DP64 ? uy : ret; - - return as_double(ret); -} -_CLC_BINARY_VECTORIZE(_CLC_DEF _CLC_OVERLOAD, double, __clc_powr, double, double) -#endif diff --git a/libclc/generic/lib/math/clc_remainder.cl b/libclc/generic/lib/math/clc_remainder.cl deleted file mode 100644 index ba50ee345191d..0000000000000 --- a/libclc/generic/lib/math/clc_remainder.cl +++ /dev/null @@ -1,218 +0,0 @@ -/* - * Copyright (c) 2014 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include - -#include -#include "../clcmacro.h" -#include "config.h" -#include "math.h" - -_CLC_DEF _CLC_OVERLOAD float __clc_remainder(float x, float y) -{ - int ux = as_int(x); - int ax = ux & EXSIGNBIT_SP32; - float xa = as_float(ax); - int sx = ux ^ ax; - int ex = ax >> EXPSHIFTBITS_SP32; - - int uy = as_int(y); - int ay = uy & EXSIGNBIT_SP32; - float ya = as_float(ay); - int ey = ay >> EXPSHIFTBITS_SP32; - - float xr = as_float(0x3f800000 | (ax & 0x007fffff)); - float yr = as_float(0x3f800000 | (ay & 0x007fffff)); - int c; - int k = ex - ey; - - uint q = 0; - - while (k > 0) { - c = xr >= yr; - q = (q << 1) | c; - xr -= c ? yr : 0.0f; - xr += xr; - --k; - } - - c = xr > yr; - q = (q << 1) | c; - xr -= c ? yr : 0.0f; - - int lt = ex < ey; - - q = lt ? 0 : q; - xr = lt ? xa : xr; - yr = lt ? ya : yr; - - c = (yr < 2.0f * xr) | ((yr == 2.0f * xr) & ((q & 0x1) == 0x1)); - xr -= c ? yr : 0.0f; - q += c; - - float s = as_float(ey << EXPSHIFTBITS_SP32); - xr *= lt ? 1.0f : s; - - c = ax == ay; - xr = c ? 0.0f : xr; - - xr = as_float(sx ^ as_int(xr)); - - c = ax > PINFBITPATT_SP32 | ay > PINFBITPATT_SP32 | ax == PINFBITPATT_SP32 | ay == 0; - xr = c ? as_float(QNANBITPATT_SP32) : xr; - - return xr; - -} -_CLC_BINARY_VECTORIZE(_CLC_DEF _CLC_OVERLOAD, float, __clc_remainder, float, float); - -#ifdef cl_khr_fp64 -_CLC_DEF _CLC_OVERLOAD double __clc_remainder(double x, double y) -{ - ulong ux = as_ulong(x); - ulong ax = ux & ~SIGNBIT_DP64; - ulong xsgn = ux ^ ax; - double dx = as_double(ax); - int xexp = convert_int(ax >> EXPSHIFTBITS_DP64); - int xexp1 = 11 - (int) clz(ax & MANTBITS_DP64); - xexp1 = xexp < 1 ? xexp1 : xexp; - - ulong uy = as_ulong(y); - ulong ay = uy & ~SIGNBIT_DP64; - double dy = as_double(ay); - int yexp = convert_int(ay >> EXPSHIFTBITS_DP64); - int yexp1 = 11 - (int) clz(ay & MANTBITS_DP64); - yexp1 = yexp < 1 ? yexp1 : yexp; - - int qsgn = ((ux ^ uy) & SIGNBIT_DP64) == 0UL ? 1 : -1; - - // First assume |x| > |y| - - // Set ntimes to the number of times we need to do a - // partial remainder. If the exponent of x is an exact multiple - // of 53 larger than the exponent of y, and the mantissa of x is - // less than the mantissa of y, ntimes will be one too large - // but it doesn't matter - it just means that we'll go round - // the loop below one extra time. - int ntimes = max(0, (xexp1 - yexp1) / 53); - double w = ldexp(dy, ntimes * 53); - w = ntimes == 0 ? dy : w; - double scale = ntimes == 0 ? 1.0 : 0x1.0p-53; - - // Each time round the loop we compute a partial remainder. - // This is done by subtracting a large multiple of w - // from x each time, where w is a scaled up version of y. - // The subtraction must be performed exactly in quad - // precision, though the result at each stage can - // fit exactly in a double precision number. - int i; - double t, v, p, pp; - - for (i = 0; i < ntimes; i++) { - // Compute integral multiplier - t = trunc(dx / w); - - // Compute w * t in quad precision - p = w * t; - pp = fma(w, t, -p); - - // Subtract w * t from dx - v = dx - p; - dx = v + (((dx - v) - p) - pp); - - // If t was one too large, dx will be negative. Add back one w. - dx += dx < 0.0 ? w : 0.0; - - // Scale w down by 2^(-53) for the next iteration - w *= scale; - } - - // One more time - // Variable todd says whether the integer t is odd or not - t = floor(dx / w); - long lt = (long)t; - int todd = lt & 1; - - p = w * t; - pp = fma(w, t, -p); - v = dx - p; - dx = v + (((dx - v) - p) - pp); - i = dx < 0.0; - todd ^= i; - dx += i ? w : 0.0; - - // At this point, dx lies in the range [0,dy) - - // For the fmod function, we're done apart from setting the correct sign. - // - // For the remainder function, we need to adjust dx - // so that it lies in the range (-y/2, y/2] by carefully - // subtracting w (== dy == y) if necessary. The rigmarole - // with todd is to get the correct sign of the result - // when x/y lies exactly half way between two integers, - // when we need to choose the even integer. - - int al = (2.0*dx > w) | (todd & (2.0*dx == w)); - double dxl = dx - (al ? w : 0.0); - - int ag = (dx > 0.5*w) | (todd & (dx == 0.5*w)); - double dxg = dx - (ag ? w : 0.0); - - dx = dy < 0x1.0p+1022 ? dxl : dxg; - - double ret = as_double(xsgn ^ as_ulong(dx)); - dx = as_double(ax); - - // Now handle |x| == |y| - int c = dx == dy; - t = as_double(xsgn); - ret = c ? t : ret; - - // Next, handle |x| < |y| - c = dx < dy; - ret = c ? x : ret; - - c &= (yexp < 1023 & 2.0*dx > dy) | (dx > 0.5*dy); - // we could use a conversion here instead since qsgn = +-1 - p = qsgn == 1 ? -1.0 : 1.0; - t = fma(y, p, x); - ret = c ? t : ret; - - // We don't need anything special for |x| == 0 - - // |y| is 0 - c = dy == 0.0; - ret = c ? as_double(QNANBITPATT_DP64) : ret; - - // y is +-Inf, NaN - c = yexp > BIASEDEMAX_DP64; - t = y == y ? x : y; - ret = c ? t : ret; - - // x is +=Inf, NaN - c = xexp > BIASEDEMAX_DP64; - ret = c ? as_double(QNANBITPATT_DP64) : ret; - - return ret; -} -_CLC_BINARY_VECTORIZE(_CLC_DEF _CLC_OVERLOAD, double, __clc_remainder, double, double); -#endif diff --git a/libclc/generic/lib/math/clc_remquo.cl b/libclc/generic/lib/math/clc_remquo.cl deleted file mode 100644 index 3b9159ac967ef..0000000000000 --- a/libclc/generic/lib/math/clc_remquo.cl +++ /dev/null @@ -1,256 +0,0 @@ -/* - * Copyright (c) 2014 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include - -#include -#include "../clcmacro.h" -#include "config.h" -#include "math.h" - -_CLC_DEF _CLC_OVERLOAD float __clc_remquo(float x, float y, __private int *quo) -{ - x = __clc_flush_denormal_if_not_supported(x); - y = __clc_flush_denormal_if_not_supported(y); - int ux = as_int(x); - int ax = ux & EXSIGNBIT_SP32; - float xa = as_float(ax); - int sx = ux ^ ax; - int ex = ax >> EXPSHIFTBITS_SP32; - - int uy = as_int(y); - int ay = uy & EXSIGNBIT_SP32; - float ya = as_float(ay); - int sy = uy ^ ay; - int ey = ay >> EXPSHIFTBITS_SP32; - - float xr = as_float(0x3f800000 | (ax & 0x007fffff)); - float yr = as_float(0x3f800000 | (ay & 0x007fffff)); - int c; - int k = ex - ey; - - uint q = 0; - - while (k > 0) { - c = xr >= yr; - q = (q << 1) | c; - xr -= c ? yr : 0.0f; - xr += xr; - --k; - } - - c = xr > yr; - q = (q << 1) | c; - xr -= c ? yr : 0.0f; - - int lt = ex < ey; - - q = lt ? 0 : q; - xr = lt ? xa : xr; - yr = lt ? ya : yr; - - c = (yr < 2.0f * xr) | ((yr == 2.0f * xr) & ((q & 0x1) == 0x1)); - xr -= c ? yr : 0.0f; - q += c; - - float s = as_float(ey << EXPSHIFTBITS_SP32); - xr *= lt ? 1.0f : s; - - int qsgn = sx == sy ? 1 : -1; - int quot = (q & 0x7f) * qsgn; - - c = ax == ay; - quot = c ? qsgn : quot; - xr = c ? 0.0f : xr; - - xr = as_float(sx ^ as_int(xr)); - - c = ax > PINFBITPATT_SP32 | ay > PINFBITPATT_SP32 | ax == PINFBITPATT_SP32 | ay == 0; - quot = c ? 0 : quot; - xr = c ? as_float(QNANBITPATT_SP32) : xr; - - *quo = quot; - - return xr; -} -// remquo singature is special, we don't have macro for this -#define __VEC_REMQUO(TYPE, VEC_SIZE, HALF_VEC_SIZE) \ -_CLC_DEF _CLC_OVERLOAD TYPE##VEC_SIZE __clc_remquo(TYPE##VEC_SIZE x, TYPE##VEC_SIZE y, __private int##VEC_SIZE *quo) \ -{ \ - int##HALF_VEC_SIZE lo, hi; \ - TYPE##VEC_SIZE ret; \ - ret.lo = __clc_remquo(x.lo, y.lo, &lo); \ - ret.hi = __clc_remquo(x.hi, y.hi, &hi); \ - (*quo).lo = lo; \ - (*quo).hi = hi; \ - return ret; \ -} -__VEC_REMQUO(float, 2,) -__VEC_REMQUO(float, 3, 2) -__VEC_REMQUO(float, 4, 2) -__VEC_REMQUO(float, 8, 4) -__VEC_REMQUO(float, 16, 8) - -#ifdef cl_khr_fp64 -_CLC_DEF _CLC_OVERLOAD double __clc_remquo(double x, double y, __private int *pquo) -{ - ulong ux = as_ulong(x); - ulong ax = ux & ~SIGNBIT_DP64; - ulong xsgn = ux ^ ax; - double dx = as_double(ax); - int xexp = convert_int(ax >> EXPSHIFTBITS_DP64); - int xexp1 = 11 - (int) clz(ax & MANTBITS_DP64); - xexp1 = xexp < 1 ? xexp1 : xexp; - - ulong uy = as_ulong(y); - ulong ay = uy & ~SIGNBIT_DP64; - double dy = as_double(ay); - int yexp = convert_int(ay >> EXPSHIFTBITS_DP64); - int yexp1 = 11 - (int) clz(ay & MANTBITS_DP64); - yexp1 = yexp < 1 ? yexp1 : yexp; - - int qsgn = ((ux ^ uy) & SIGNBIT_DP64) == 0UL ? 1 : -1; - - // First assume |x| > |y| - - // Set ntimes to the number of times we need to do a - // partial remainder. If the exponent of x is an exact multiple - // of 53 larger than the exponent of y, and the mantissa of x is - // less than the mantissa of y, ntimes will be one too large - // but it doesn't matter - it just means that we'll go round - // the loop below one extra time. - int ntimes = max(0, (xexp1 - yexp1) / 53); - double w = ldexp(dy, ntimes * 53); - w = ntimes == 0 ? dy : w; - double scale = ntimes == 0 ? 1.0 : 0x1.0p-53; - - // Each time round the loop we compute a partial remainder. - // This is done by subtracting a large multiple of w - // from x each time, where w is a scaled up version of y. - // The subtraction must be performed exactly in quad - // precision, though the result at each stage can - // fit exactly in a double precision number. - int i; - double t, v, p, pp; - - for (i = 0; i < ntimes; i++) { - // Compute integral multiplier - t = trunc(dx / w); - - // Compute w * t in quad precision - p = w * t; - pp = fma(w, t, -p); - - // Subtract w * t from dx - v = dx - p; - dx = v + (((dx - v) - p) - pp); - - // If t was one too large, dx will be negative. Add back one w. - dx += dx < 0.0 ? w : 0.0; - - // Scale w down by 2^(-53) for the next iteration - w *= scale; - } - - // One more time - // Variable todd says whether the integer t is odd or not - t = floor(dx / w); - long lt = (long)t; - int todd = lt & 1; - - p = w * t; - pp = fma(w, t, -p); - v = dx - p; - dx = v + (((dx - v) - p) - pp); - i = dx < 0.0; - todd ^= i; - dx += i ? w : 0.0; - - lt -= i; - - // At this point, dx lies in the range [0,dy) - - // For the remainder function, we need to adjust dx - // so that it lies in the range (-y/2, y/2] by carefully - // subtracting w (== dy == y) if necessary. The rigmarole - // with todd is to get the correct sign of the result - // when x/y lies exactly half way between two integers, - // when we need to choose the even integer. - - int al = (2.0*dx > w) | (todd & (2.0*dx == w)); - double dxl = dx - (al ? w : 0.0); - - int ag = (dx > 0.5*w) | (todd & (dx == 0.5*w)); - double dxg = dx - (ag ? w : 0.0); - - dx = dy < 0x1.0p+1022 ? dxl : dxg; - lt += dy < 0x1.0p+1022 ? al : ag; - int quo = ((int)lt & 0x7f) * qsgn; - - double ret = as_double(xsgn ^ as_ulong(dx)); - dx = as_double(ax); - - // Now handle |x| == |y| - int c = dx == dy; - t = as_double(xsgn); - quo = c ? qsgn : quo; - ret = c ? t : ret; - - // Next, handle |x| < |y| - c = dx < dy; - quo = c ? 0 : quo; - ret = c ? x : ret; - - c &= (yexp < 1023 & 2.0*dx > dy) | (dx > 0.5*dy); - quo = c ? qsgn : quo; - // we could use a conversion here instead since qsgn = +-1 - p = qsgn == 1 ? -1.0 : 1.0; - t = fma(y, p, x); - ret = c ? t : ret; - - // We don't need anything special for |x| == 0 - - // |y| is 0 - c = dy == 0.0; - quo = c ? 0 : quo; - ret = c ? as_double(QNANBITPATT_DP64) : ret; - - // y is +-Inf, NaN - c = yexp > BIASEDEMAX_DP64; - quo = c ? 0 : quo; - t = y == y ? x : y; - ret = c ? t : ret; - - // x is +=Inf, NaN - c = xexp > BIASEDEMAX_DP64; - quo = c ? 0 : quo; - ret = c ? as_double(QNANBITPATT_DP64) : ret; - - *pquo = quo; - return ret; -} -__VEC_REMQUO(double, 2,) -__VEC_REMQUO(double, 3, 2) -__VEC_REMQUO(double, 4, 2) -__VEC_REMQUO(double, 8, 4) -__VEC_REMQUO(double, 16, 8) -#endif diff --git a/libclc/generic/lib/math/clc_rootn.cl b/libclc/generic/lib/math/clc_rootn.cl deleted file mode 100644 index 947c5c4b9e0a7..0000000000000 --- a/libclc/generic/lib/math/clc_rootn.cl +++ /dev/null @@ -1,370 +0,0 @@ -/* - * Copyright (c) 2014 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include - -#include "config.h" -#include "math.h" -#include "../../libspirv/math/tables.h" -#include "../clcmacro.h" - -// compute pow using log and exp -// x^y = exp(y * log(x)) -// -// we take care not to lose precision in the intermediate steps -// -// When computing log, calculate it in splits, -// -// r = f * (p_invead + p_inv_tail) -// r = rh + rt -// -// calculate log polynomial using r, in end addition, do -// poly = poly + ((rh-r) + rt) -// -// lth = -r -// ltt = ((xexp * log2_t) - poly) + logT -// lt = lth + ltt -// -// lh = (xexp * log2_h) + logH -// l = lh + lt -// -// Calculate final log answer as gh and gt, -// gh = l & higher-half bits -// gt = (((ltt - (lt - lth)) + ((lh - l) + lt)) + (l - gh)) -// -// yh = y & higher-half bits -// yt = y - yh -// -// Before entering computation of exp, -// vs = ((yt*gt + yt*gh) + yh*gt) -// v = vs + yh*gh -// vt = ((yh*gh - v) + vs) -// -// In calculation of exp, add vt to r that is used for poly -// At the end of exp, do -// ((((expT * poly) + expT) + expH*poly) + expH) - -_CLC_DEF _CLC_OVERLOAD float __clc_rootn(float x, int ny) -{ - float y = MATH_RECIP((float)ny); - - int ix = as_int(x); - int ax = ix & EXSIGNBIT_SP32; - int xpos = ix == ax; - - int iy = as_int(y); - int ay = iy & EXSIGNBIT_SP32; - int ypos = iy == ay; - - // Extra precise log calculation - // First handle case that x is close to 1 - float r = 1.0f - as_float(ax); - int near1 = fabs(r) < 0x1.0p-4f; - float r2 = r*r; - - // Coefficients are just 1/3, 1/4, 1/5 and 1/6 - float poly = mad(r, - mad(r, - mad(r, - mad(r, 0x1.24924ap-3f, 0x1.555556p-3f), - 0x1.99999ap-3f), - 0x1.000000p-2f), - 0x1.555556p-2f); - - poly *= r2*r; - - float lth_near1 = -r2 * 0.5f; - float ltt_near1 = -poly; - float lt_near1 = lth_near1 + ltt_near1; - float lh_near1 = -r; - float l_near1 = lh_near1 + lt_near1; - - // Computations for x not near 1 - int m = (int)(ax >> EXPSHIFTBITS_SP32) - EXPBIAS_SP32; - float mf = (float)m; - int ixs = as_int(as_float(ax | 0x3f800000) - 1.0f); - float mfs = (float)((ixs >> EXPSHIFTBITS_SP32) - 253); - int c = m == -127; - int ixn = c ? ixs : ax; - float mfn = c ? mfs : mf; - - int indx = (ixn & 0x007f0000) + ((ixn & 0x00008000) << 1); - - // F - Y - float f = as_float(0x3f000000 | indx) - as_float(0x3f000000 | (ixn & MANTBITS_SP32)); - - indx = indx >> 16; - float2 tv = USE_TABLE(log_inv_tbl_ep, indx); - float rh = f * tv.s0; - float rt = f * tv.s1; - r = rh + rt; - - poly = mad(r, mad(r, 0x1.0p-2f, 0x1.555556p-2f), 0x1.0p-1f) * (r*r); - poly += (rh - r) + rt; - - const float LOG2_HEAD = 0x1.62e000p-1f; // 0.693115234 - const float LOG2_TAIL = 0x1.0bfbe8p-15f; // 0.0000319461833 - tv = USE_TABLE(loge_tbl, indx); - float lth = -r; - float ltt = mad(mfn, LOG2_TAIL, -poly) + tv.s1; - float lt = lth + ltt; - float lh = mad(mfn, LOG2_HEAD, tv.s0); - float l = lh + lt; - - // Select near 1 or not - lth = near1 ? lth_near1 : lth; - ltt = near1 ? ltt_near1 : ltt; - lt = near1 ? lt_near1 : lt; - lh = near1 ? lh_near1 : lh; - l = near1 ? l_near1 : l; - - float gh = as_float(as_int(l) & 0xfffff000); - float gt = ((ltt - (lt - lth)) + ((lh - l) + lt)) + (l - gh); - - float yh = as_float(iy & 0xfffff000); - - float fny = (float)ny; - float fnyh = as_float(as_int(fny) & 0xfffff000); - float fnyt = (float)(ny - (int)fnyh); - float yt = MATH_DIVIDE(mad(-fnyt, yh, mad(-fnyh, yh, 1.0f)), fny); - - float ylogx_s = mad(gt, yh, mad(gh, yt, yt*gt)); - float ylogx = mad(yh, gh, ylogx_s); - float ylogx_t = mad(yh, gh, -ylogx) + ylogx_s; - - // Extra precise exp of ylogx - const float R_64_BY_LOG2 = 0x1.715476p+6f; // 64/log2 : 92.332482616893657 - int n = convert_int(ylogx * R_64_BY_LOG2); - float nf = (float) n; - - int j = n & 0x3f; - m = n >> 6; - int m2 = m << EXPSHIFTBITS_SP32; - - const float R_LOG2_BY_64_LD = 0x1.620000p-7f; // log2/64 lead: 0.0108032227 - const float R_LOG2_BY_64_TL = 0x1.c85fdep-16f; // log2/64 tail: 0.0000272020388 - r = mad(nf, -R_LOG2_BY_64_TL, mad(nf, -R_LOG2_BY_64_LD, ylogx)) + ylogx_t; - - // Truncated Taylor series for e^r - poly = mad(mad(mad(r, 0x1.555556p-5f, 0x1.555556p-3f), r, 0x1.000000p-1f), r*r, r); - - tv = USE_TABLE(exp_tbl_ep, j); - - float expylogx = mad(tv.s0, poly, mad(tv.s1, poly, tv.s1)) + tv.s0; - float sexpylogx = __clc_fp32_subnormals_supported() ? expylogx * as_float(0x1 << (m + 149)) : 0.0f; - - float texpylogx = as_float(as_int(expylogx) + m2); - expylogx = m < -125 ? sexpylogx : texpylogx; - - // Result is +-Inf if (ylogx + ylogx_t) > 128*log2 - expylogx = ((ylogx > 0x1.62e430p+6f) | (ylogx == 0x1.62e430p+6f & ylogx_t > -0x1.05c610p-22f)) ? as_float(PINFBITPATT_SP32) : expylogx; - - // Result is 0 if ylogx < -149*log2 - expylogx = ylogx < -0x1.9d1da0p+6f ? 0.0f : expylogx; - - // Classify y: - // inty = 0 means not an integer. - // inty = 1 means odd integer. - // inty = 2 means even integer. - - int inty = 2 - (ny & 1); - - float signval = as_float((as_uint(expylogx) ^ SIGNBIT_SP32)); - expylogx = ((inty == 1) & !xpos) ? signval : expylogx; - int ret = as_int(expylogx); - - // Corner case handling - ret = (!xpos & (inty == 2)) ? QNANBITPATT_SP32 : ret; - int xinf = xpos ? PINFBITPATT_SP32 : NINFBITPATT_SP32; - ret = ((ax == 0) & !ypos & (inty == 1)) ? xinf : ret; - ret = ((ax == 0) & !ypos & (inty == 2)) ? PINFBITPATT_SP32 : ret; - ret = ((ax == 0) & ypos & (inty == 2)) ? 0 : ret; - int xzero = xpos ? 0 : 0x80000000; - ret = ((ax == 0) & ypos & (inty == 1)) ? xzero : ret; - ret = ((ix == NINFBITPATT_SP32) & ypos & (inty == 1)) ? NINFBITPATT_SP32 : ret; - ret = ((ix == NINFBITPATT_SP32) & !ypos & (inty == 1)) ? 0x80000000 : ret; - ret = ((ix == PINFBITPATT_SP32) & !ypos) ? 0 : ret; - ret = ((ix == PINFBITPATT_SP32) & ypos) ? PINFBITPATT_SP32 : ret; - ret = ax > PINFBITPATT_SP32 ? ix : ret; - ret = ny == 0 ? QNANBITPATT_SP32 : ret; - - return as_float(ret); -} -_CLC_BINARY_VECTORIZE(_CLC_DEF _CLC_OVERLOAD, float, __clc_rootn, float, int) - -#ifdef cl_khr_fp64 -_CLC_DEF _CLC_OVERLOAD double __clc_rootn(double x, int ny) -{ - const double real_log2_tail = 5.76999904754328540596e-08; - const double real_log2_lead = 6.93147122859954833984e-01; - - double dny = (double)ny; - double y = 1.0 / dny; - - long ux = as_long(x); - long ax = ux & (~SIGNBIT_DP64); - int xpos = ax == ux; - - long uy = as_long(y); - long ay = uy & (~SIGNBIT_DP64); - int ypos = ay == uy; - - // Extended precision log - double v, vt; - { - int exp = (int)(ax >> 52) - 1023; - int mask_exp_1023 = exp == -1023; - double xexp = (double) exp; - long mantissa = ax & 0x000FFFFFFFFFFFFFL; - - long temp_ux = as_long(as_double(0x3ff0000000000000L | mantissa) - 1.0); - exp = ((temp_ux & 0x7FF0000000000000L) >> 52) - 2045; - double xexp1 = (double) exp; - long mantissa1 = temp_ux & 0x000FFFFFFFFFFFFFL; - - xexp = mask_exp_1023 ? xexp1 : xexp; - mantissa = mask_exp_1023 ? mantissa1 : mantissa; - - long rax = (mantissa & 0x000ff00000000000) + ((mantissa & 0x0000080000000000) << 1); - int index = rax >> 44; - - double F = as_double(rax | 0x3FE0000000000000L); - double Y = as_double(mantissa | 0x3FE0000000000000L); - double f = F - Y; - double2 tv = USE_TABLE(log_f_inv_tbl, index); - double log_h = tv.s0; - double log_t = tv.s1; - double f_inv = (log_h + log_t) * f; - double r1 = as_double(as_long(f_inv) & 0xfffffffff8000000L); - double r2 = fma(-F, r1, f) * (log_h + log_t); - double r = r1 + r2; - - double poly = fma(r, - fma(r, - fma(r, - fma(r, 1.0/7.0, 1.0/6.0), - 1.0/5.0), - 1.0/4.0), - 1.0/3.0); - poly = poly * r * r * r; - - double hr1r1 = 0.5*r1*r1; - double poly0h = r1 + hr1r1; - double poly0t = r1 - poly0h + hr1r1; - poly = fma(r1, r2, fma(0.5*r2, r2, poly)) + r2 + poly0t; - - tv = USE_TABLE(powlog_tbl, index); - log_h = tv.s0; - log_t = tv.s1; - - double resT_t = fma(xexp, real_log2_tail, + log_t) - poly; - double resT = resT_t - poly0h; - double resH = fma(xexp, real_log2_lead, log_h); - double resT_h = poly0h; - - double H = resT + resH; - double H_h = as_double(as_long(H) & 0xfffffffff8000000L); - double T = (resH - H + resT) + (resT_t - (resT + resT_h)) + (H - H_h); - H = H_h; - - double y_head = as_double(uy & 0xfffffffff8000000L); - double y_tail = y - y_head; - - double fnyh = as_double(as_long(dny) & 0xfffffffffff00000); - double fnyt = (double)(ny - (int)fnyh); - y_tail = fma(-fnyt, y_head, fma(-fnyh, y_head, 1.0))/ dny; - - double temp = fma(y_tail, H, fma(y_head, T, y_tail*T)); - v = fma(y_head, H, temp); - vt = fma(y_head, H, -v) + temp; - } - - // Now calculate exp of (v,vt) - - double expv; - { - const double max_exp_arg = 709.782712893384; - const double min_exp_arg = -745.1332191019411; - const double sixtyfour_by_lnof2 = 92.33248261689366; - const double lnof2_by_64_head = 0.010830424260348081; - const double lnof2_by_64_tail = -4.359010638708991e-10; - - double temp = v * sixtyfour_by_lnof2; - int n = (int)temp; - double dn = (double)n; - int j = n & 0x0000003f; - int m = n >> 6; - - double2 tv = USE_TABLE(two_to_jby64_ep_tbl, j); - double f1 = tv.s0; - double f2 = tv.s1; - double f = f1 + f2; - - double r1 = fma(dn, -lnof2_by_64_head, v); - double r2 = dn * lnof2_by_64_tail; - double r = (r1 + r2) + vt; - - double q = fma(r, - fma(r, - fma(r, - fma(r, 1.38889490863777199667e-03, 8.33336798434219616221e-03), - 4.16666666662260795726e-02), - 1.66666666665260878863e-01), - 5.00000000000000008883e-01); - q = fma(r*r, q, r); - - expv = fma(f, q, f2) + f1; - expv = ldexp(expv, m); - - expv = v > max_exp_arg ? as_double(0x7FF0000000000000L) : expv; - expv = v < min_exp_arg ? 0.0 : expv; - } - - // See whether y is an integer. - // inty = 0 means not an integer. - // inty = 1 means odd integer. - // inty = 2 means even integer. - - int inty = 2 - (ny & 1); - - expv *= ((inty == 1) & !xpos) ? -1.0 : 1.0; - - long ret = as_long(expv); - - // Now all the edge cases - ret = (!xpos & (inty == 2)) ? QNANBITPATT_DP64 : ret; - long xinf = xpos ? PINFBITPATT_DP64 : NINFBITPATT_DP64; - ret = ((ax == 0L) & !ypos & (inty == 1)) ? xinf : ret; - ret = ((ax == 0L) & !ypos & (inty == 2)) ? PINFBITPATT_DP64 : ret; - ret = ((ax == 0L) & ypos & (inty == 2)) ? 0L : ret; - long xzero = xpos ? 0L : 0x8000000000000000L; - ret = ((ax == 0L) & ypos & (inty == 1)) ? xzero : ret; - ret = ((ux == NINFBITPATT_DP64) & ypos & (inty == 1)) ? NINFBITPATT_DP64 : ret; - ret = ((ux == NINFBITPATT_DP64) & !ypos & (inty == 1)) ? 0x8000000000000000L : ret; - ret = ((ux == PINFBITPATT_DP64) & !ypos) ? 0L : ret; - ret = ((ux == PINFBITPATT_DP64) & ypos) ? PINFBITPATT_DP64 : ret; - ret = ax > PINFBITPATT_DP64 ? ux : ret; - ret = ny == 0 ? QNANBITPATT_DP64 : ret; - return as_double(ret); -} -_CLC_BINARY_VECTORIZE(_CLC_DEF _CLC_OVERLOAD, double, __clc_rootn, double, int) -#endif diff --git a/libclc/generic/libspirv/SOURCES b/libclc/generic/libspirv/SOURCES index bdbe46a64e291..f52fadf1a43e3 100644 --- a/libclc/generic/libspirv/SOURCES +++ b/libclc/generic/libspirv/SOURCES @@ -66,37 +66,86 @@ integer/rhadd.cl integer/rotate.cl integer/sub_sat.cl integer/upsample.cl +math/acos.cl +math/acosh.cl +math/acospi.cl +math/asin.cl +math/asinh.cl +math/asinpi.cl +math/atan.cl +math/atan2.cl +math/atan2pi.cl +math/atanh.cl +math/atanpi.cl +math/cbrt.cl math/ceil.cl math/clc_exp10.cl math/clc_fma.cl +math/clc_fmod.cl +math/clc_hypot.cl math/clc_ldexp.cl +math/clc_nextafter.cl math/clc_pow.cl +math/clc_pown.cl +math/clc_powr.cl +math/clc_remainder.cl +math/clc_remquo.cl +math/clc_rootn.cl math/clc_sqrt.cl math/clc_tan.cl math/clc_tanpi.cl math/copysign.cl math/cos.cl +math/cosh.cl math/cospi.cl +math/ep_log.cl +math/erf.cl +math/erfc.cl math/exp.cl math/exp10.cl math/exp2.cl math/exp_helper.cl math/expm1.cl math/fabs.cl +math/fdim.cl math/floor.cl math/fma.cl math/fmax.cl +math/fmax_common.cl math/fmin.cl +math/fmin_common.cl math/fmod.cl math/fract.cl +math/frexp.cl +math/half_cos.cl +math/half_divide.cl +math/half_exp.cl +math/half_exp10.cl +math/half_exp2.cl +math/half_log.cl +math/half_log10.cl +math/half_log2.cl +math/half_powr.cl +math/half_recip.cl math/half_rsqrt.cl +math/half_sin.cl math/half_sqrt.cl +math/half_tan.cl +math/hypot.cl +math/ilogb.cl math/ldexp.cl +math/lgamma.cl +math/lgamma_r.cl math/log.cl math/log10.cl +math/log1p.cl math/log2.cl math/logb.cl math/mad.cl +math/maxmag.cl +math/minmag.cl +math/modf.cl +math/nan.cl math/native_cos.cl math/native_divide.cl math/native_exp.cl @@ -111,16 +160,27 @@ math/native_rsqrt.cl math/native_sin.cl math/native_sqrt.cl math/native_tan.cl +math/nextafter.cl math/pow.cl +math/pown.cl +math/powr.cl +math/remainer.cl +math/remquo.cl math/rint.cl +math/rootn.cl math/round.cl math/sin.cl math/sincos.cl math/sincos_helpers.cl +math/sinh.cl math/sinpi.cl math/sqrt.cl math/rsqrt.cl math/tables.cl +math/tan.cl +math/tanh.cl +math/tanpi.cl +math/tgamma.cl math/trunc.cl relational/all.cl relational/any.cl diff --git a/libclc/generic/libspirv/common/degrees.cl b/libclc/generic/libspirv/common/degrees.cl index 1c42a41a3fc23..bf95dc19088b3 100644 --- a/libclc/generic/libspirv/common/degrees.cl +++ b/libclc/generic/libspirv/common/degrees.cl @@ -8,7 +8,7 @@ #include -#include "../../lib/clcmacro.h" +#include _CLC_OVERLOAD _CLC_DEF float __spirv_ocl_degrees(float radians) { // 180/pi = ~57.29577951308232087685 or 0x1.ca5dc1a63c1f8p+5 or 0x1.ca5dc2p+5F diff --git a/libclc/generic/libspirv/common/radians.cl b/libclc/generic/libspirv/common/radians.cl index 0b106157eb11b..c8936125a45ba 100644 --- a/libclc/generic/libspirv/common/radians.cl +++ b/libclc/generic/libspirv/common/radians.cl @@ -8,7 +8,7 @@ #include -#include "../../lib/clcmacro.h" +#include _CLC_OVERLOAD _CLC_DEF float __spirv_ocl_radians(float degrees) { // pi/180 = ~0.01745329251994329577 or 0x1.1df46a2529d39p-6 or 0x1.1df46ap-6F diff --git a/libclc/generic/libspirv/common/sign.cl b/libclc/generic/libspirv/common/sign.cl index c48ac4e6a7518..5f8fcecbe9e09 100644 --- a/libclc/generic/libspirv/common/sign.cl +++ b/libclc/generic/libspirv/common/sign.cl @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "../../lib/clcmacro.h" +#include #include #define SIGN(TYPE, F) \ diff --git a/libclc/generic/libspirv/common/step.cl b/libclc/generic/libspirv/common/step.cl index bec9b4e0bf735..79477f547a4cc 100644 --- a/libclc/generic/libspirv/common/step.cl +++ b/libclc/generic/libspirv/common/step.cl @@ -8,7 +8,7 @@ #include -#include "../../lib/clcmacro.h" +#include #define STEP_DEF(TYPE, TYPOSTFIX) \ _CLC_OVERLOAD _CLC_DEF TYPE __spirv_ocl_step(TYPE edge, TYPE x) { \ diff --git a/libclc/generic/include/spirv/math/frexp.h b/libclc/generic/libspirv/math/acos.cl similarity index 80% rename from libclc/generic/include/spirv/math/frexp.h rename to libclc/generic/libspirv/math/acos.cl index 0d343956ef31f..f7842db9ec9ca 100644 --- a/libclc/generic/include/spirv/math/frexp.h +++ b/libclc/generic/libspirv/math/acos.cl @@ -6,5 +6,7 @@ // //===----------------------------------------------------------------------===// -#define __SPIRV_BODY -#include +#include + +#define __CLC_BODY +#include diff --git a/libclc/generic/libspirv/math/acos.inc b/libclc/generic/libspirv/math/acos.inc new file mode 100644 index 0000000000000..4b437283f60ec --- /dev/null +++ b/libclc/generic/libspirv/math/acos.inc @@ -0,0 +1,42 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +/* + * There are multiple formulas for calculating arccosine of x: + * 1) acos(x) = (1/2*pi) + i * ln(i*x + sqrt(1-x^2)) (notice the 'i'...) + * 2) acos(x) = pi/2 + asin(-x) (asin isn't implemented yet) + * 3) acos(x) = pi/2 - asin(x) (ditto) + * 4) acos(x) = 2*atan2(sqrt(1-x), sqrt(1+x)) + * 5) acos(x) = pi/2 - atan2(x, ( sqrt(1-x^2) ) ) + * + * Options 1-3 are not currently usable, #5 generates more concise radeonsi + * bitcode and assembly than #4 (134 vs 132 instructions on radeonsi), but + * precision of #4 may be better. + */ + +// TODO: Enable half precision when atan2 is implemented +#if __CLC_FPSIZE > 16 + +#if __CLC_FPSIZE == 64 +#define __CLC_CONST(x) x +#elif __CLC_FPSIZE == 32 +#define __CLC_CONST(x) x##f +#elif __CLC_FPSIZE == 16 +#define __CLC_CONST(x) x##h +#endif + +_CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE __spirv_ocl_acos(__CLC_GENTYPE x) { + return ( + (__CLC_GENTYPE)__CLC_CONST(2.0) * + __spirv_ocl_atan2(__spirv_ocl_sqrt((__CLC_GENTYPE)__CLC_CONST(1.0) - x), + __spirv_ocl_sqrt((__CLC_GENTYPE)__CLC_CONST(1.0) + x))); +} + +#undef __CLC_CONST + +#endif diff --git a/libclc/generic/libspirv/math/acosh.cl b/libclc/generic/libspirv/math/acosh.cl new file mode 100644 index 0000000000000..6945d3f6e2c8d --- /dev/null +++ b/libclc/generic/libspirv/math/acosh.cl @@ -0,0 +1,115 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include "ep_log.h" +#include +#include + +_CLC_OVERLOAD _CLC_DEF float __spirv_ocl_acosh(float x) { + uint ux = as_uint(x); + + // Arguments greater than 1/sqrt(epsilon) in magnitude are + // approximated by acosh(x) = ln(2) + ln(x) + // For 2.0 <= x <= 1/sqrt(epsilon) the approximation is + // acosh(x) = ln(x + sqrt(x*x-1)) */ + int high = ux > 0x46000000U; + int med = ux > 0x40000000U; + + float w = x - 1.0f; + float s = w * w + 2.0f * w; + float t = x * x - 1.0f; + float r = __spirv_ocl_sqrt(med ? t : s) + (med ? x : w); + float v = (high ? x : r) - (med ? 1.0f : 0.0f); + float z = __spirv_ocl_log1p(v) + (high ? 0x1.62e430p-1f : 0.0f); + + z = ux >= PINFBITPATT_SP32 ? x : z; + z = x < 1.0f ? as_float(QNANBITPATT_SP32) : z; + + return z; +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, float, __spirv_ocl_acosh, float) + +#ifdef cl_khr_fp64 +#pragma OPENCL EXTENSION cl_khr_fp64 : enable + +_CLC_OVERLOAD _CLC_DEF double __spirv_ocl_acosh(double x) { + const double recrteps = + 0x1.6a09e667f3bcdp+26; // 1/sqrt(eps) = 9.49062656242515593767e+07 + // log2_lead and log2_tail sum to an extra-precise version of log(2) + const double log2_lead = 0x1.62e42ep-1; + const double log2_tail = 0x1.efa39ef35793cp-25; + + // Handle x >= 128 here + int xlarge = x > recrteps; + double r = x + __spirv_ocl_sqrt(__spirv_ocl_fma(x, x, -1.0)); + r = xlarge ? x : r; + + int xexp; + double r1, r2; + __clc_ep_log(r, &xexp, &r1, &r2); + + double dxexp = xexp + xlarge; + r1 = __spirv_ocl_fma(dxexp, log2_lead, r1); + r2 = __spirv_ocl_fma(dxexp, log2_tail, r2); + + double ret1 = r1 + r2; + + // Handle 1 < x < 128 here + // We compute the value + // t = x - 1.0 + sqrt(2.0*(x - 1.0) + (x - 1.0)*(x - 1.0)) + // using simulated quad precision. + double t = x - 1.0; + double u1 = t * 2.0; + + // (t,0) * (t,0) -> (v1, v2) + double v1 = t * t; + double v2 = __spirv_ocl_fma(t, t, -v1); + + // (u1,0) + (v1,v2) -> (w1,w2) + r = u1 + v1; + double s = (((u1 - r) + v1) + v2); + double w1 = r + s; + double w2 = (r - w1) + s; + + // sqrt(w1,w2) -> (u1,u2) + double p1 = __spirv_ocl_sqrt(w1); + double a1 = p1 * p1; + double a2 = __spirv_ocl_fma(p1, p1, -a1); + double temp = (((w1 - a1) - a2) + w2); + double p2 = MATH_DIVIDE(temp * 0.5, p1); + u1 = p1 + p2; + double u2 = (p1 - u1) + p2; + + // (u1,u2) + (t,0) -> (r1,r2) + r = u1 + t; + s = ((u1 - r) + t) + u2; + // r1 = r + s; + // r2 = (r - r1) + s; + // t = r1 + r2; + t = r + s; + + // For arguments 1.13 <= x <= 1.5 the log1p function is good enough + double ret2 = __spirv_ocl_log1p(t); + + ulong ux = as_ulong(x); + double ret = x >= 128.0 ? ret1 : ret2; + + ret = ux >= 0x7FF0000000000000 ? x : ret; + ret = x == 1.0 ? 0.0 : ret; + ret = + (ux & SIGNBIT_DP64) != 0UL || x < 1.0 ? as_double(QNANBITPATT_DP64) : ret; + + return ret; +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, double, __spirv_ocl_acosh, double) + +#endif diff --git a/libclc/generic/libspirv/math/acospi.cl b/libclc/generic/libspirv/math/acospi.cl new file mode 100644 index 0000000000000..e14f3dd0a4719 --- /dev/null +++ b/libclc/generic/libspirv/math/acospi.cl @@ -0,0 +1,184 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include +#include + +_CLC_OVERLOAD _CLC_DEF float __spirv_ocl_acospi(float x) { + // Computes arccos(x). + // The argument is first reduced by noting that arccos(x) + // is invalid for abs(x) > 1. For denormal and small + // arguments arccos(x) = pi/2 to machine accuracy. + // Remaining argument ranges are handled as follows. + // For abs(x) <= 0.5 use + // arccos(x) = pi/2 - arcsin(x) + // = pi/2 - (x + x^3*R(x^2)) + // where R(x^2) is a rational minimax approximation to + // (arcsin(x) - x)/x^3. + // For abs(x) > 0.5 exploit the identity: + // arccos(x) = pi - 2*arcsin(sqrt(1-x)/2) + // together with the above rational approximation, and + // reconstruct the terms carefully. + + // Some constants and split constants. + const float pi = 3.1415926535897933e+00f; + const float piby2_head = 1.5707963267948965580e+00f; /* 0x3ff921fb54442d18 */ + const float piby2_tail = 6.12323399573676603587e-17f; /* 0x3c91a62633145c07 */ + + uint ux = as_uint(x); + uint aux = ux & ~SIGNBIT_SP32; + int xneg = ux != aux; + int xexp = (int)(aux >> EXPSHIFTBITS_SP32) - EXPBIAS_SP32; + + float y = as_float(aux); + + // transform if |x| >= 0.5 + int transform = xexp >= -1; + + float y2 = y * y; + float yt = 0.5f * (1.0f - y); + float r = transform ? yt : y2; + + // Use a rational approximation for [0.0, 0.5] + float a = __spirv_ocl_mad( + r, + __spirv_ocl_mad(r, + __spirv_ocl_mad(r, -0.00396137437848476485201154797087F, + -0.0133819288943925804214011424456F), + -0.0565298683201845211985026327361F), + 0.184161606965100694821398249421F); + float b = __spirv_ocl_mad(r, -0.836411276854206731913362287293F, + 1.10496961524520294485512696706F); + float u = r * MATH_DIVIDE(a, b); + + float s = __spirv_ocl_sqrt(r); + y = s; + float s1 = as_float(as_uint(s) & 0xffff0000); + float c = MATH_DIVIDE(r - s1 * s1, s + s1); + // float rettn = 1.0f - MATH_DIVIDE(2.0f * (s + (y * u - piby2_tail)), pi); + float rettn = + 1.0f - MATH_DIVIDE(2.0f * (s + __spirv_ocl_mad(y, u, -piby2_tail)), pi); + // float rettp = MATH_DIVIDE(2.0F * s1 + (2.0F * c + 2.0F * y * u), pi); + float rettp = MATH_DIVIDE(2.0f * (s1 + __spirv_ocl_mad(y, u, c)), pi); + float rett = xneg ? rettn : rettp; + // float ret = MATH_DIVIDE(piby2_head - (x - (piby2_tail - x * u)), pi); + float ret = + MATH_DIVIDE(piby2_head - (x - __spirv_ocl_mad(x, -u, piby2_tail)), pi); + + ret = transform ? rett : ret; + ret = aux > 0x3f800000U ? as_float(QNANBITPATT_SP32) : ret; + ret = ux == 0x3f800000U ? 0.0f : ret; + ret = ux == 0xbf800000U ? 1.0f : ret; + ret = xexp < -26 ? 0.5f : ret; + return ret; +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, float, __spirv_ocl_acospi, float) + +#ifdef cl_khr_fp64 +#pragma OPENCL EXTENSION cl_khr_fp64 : enable + +_CLC_OVERLOAD _CLC_DEF double __spirv_ocl_acospi(double x) { + // Computes arccos(x). + // The argument is first reduced by noting that arccos(x) + // is invalid for abs(x) > 1. For denormal and small + // arguments arccos(x) = pi/2 to machine accuracy. + // Remaining argument ranges are handled as follows. + // For abs(x) <= 0.5 use + // arccos(x) = pi/2 - arcsin(x) + // = pi/2 - (x + x^3*R(x^2)) + // where R(x^2) is a rational minimax approximation to + // (arcsin(x) - x)/x^3. + // For abs(x) > 0.5 exploit the identity: + // arccos(x) = pi - 2*arcsin(sqrt(1-x)/2) + // together with the above rational approximation, and + // reconstruct the terms carefully. + + const double pi = 0x1.921fb54442d18p+1; + const double piby2_tail = 6.12323399573676603587e-17; /* 0x3c91a62633145c07 */ + + double y = __spirv_ocl_fabs(x); + int xneg = as_int2(x).hi < 0; + int xexp = (as_int2(y).hi >> 20) - EXPBIAS_DP64; + + // abs(x) >= 0.5 + int transform = xexp >= -1; + + // Transform y into the range [0,0.5) + double r1 = 0.5 * (1.0 - y); + double s = __spirv_ocl_sqrt(r1); + double r = y * y; + r = transform ? r1 : r; + y = transform ? s : y; + + // Use a rational approximation for [0.0, 0.5] + double un = __spirv_ocl_fma( + r, + __spirv_ocl_fma( + r, + __spirv_ocl_fma( + r, + __spirv_ocl_fma( + r, + __spirv_ocl_fma(r, 0.0000482901920344786991880522822991, + 0.00109242697235074662306043804220), + -0.0549989809235685841612020091328), + 0.275558175256937652532686256258), + -0.445017216867635649900123110649), + 0.227485835556935010735943483075); + + double ud = __spirv_ocl_fma( + r, + __spirv_ocl_fma( + r, + __spirv_ocl_fma(r, + __spirv_ocl_fma(r, 0.105869422087204370341222318533, + -0.943639137032492685763471240072), + 2.76568859157270989520376345954), + -3.28431505720958658909889444194), + 1.36491501334161032038194214209); + + double u = r * MATH_DIVIDE(un, ud); + + // Reconstruct acos carefully in transformed region + double res1 = __spirv_ocl_fma( + -2.0, MATH_DIVIDE(s + __spirv_ocl_fma(y, u, -piby2_tail), pi), 1.0); + double s1 = as_double(as_ulong(s) & 0xffffffff00000000UL); + double c = MATH_DIVIDE(__spirv_ocl_fma(-s1, s1, r), s + s1); + double res2 = MATH_DIVIDE( + __spirv_ocl_fma(2.0, s1, __spirv_ocl_fma(2.0, c, 2.0 * y * u)), pi); + res1 = xneg ? res1 : res2; + res2 = 0.5 - __spirv_ocl_fma(x, u, x) / pi; + res1 = transform ? res1 : res2; + + const double qnan = as_double(QNANBITPATT_DP64); + res2 = x == 1.0 ? 0.0 : qnan; + res2 = x == -1.0 ? 1.0 : res2; + res1 = xexp >= 0 ? res2 : res1; + res1 = xexp < -56 ? 0.5 : res1; + + return res1; +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, double, __spirv_ocl_acospi, double) + +#endif + +#ifdef cl_khr_fp16 +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +_CLC_OVERLOAD _CLC_DEF half __spirv_ocl_acospi(half x) { + float t = x; + return __spirv_ocl_acospi(t); +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, half, __spirv_ocl_acospi, half) + +#endif diff --git a/libclc/generic/include/spirv/math/ilogb.inc b/libclc/generic/libspirv/math/asin.cl similarity index 80% rename from libclc/generic/include/spirv/math/ilogb.inc rename to libclc/generic/libspirv/math/asin.cl index 6472a3e119a78..83f1a55db7e52 100644 --- a/libclc/generic/include/spirv/math/ilogb.inc +++ b/libclc/generic/libspirv/math/asin.cl @@ -6,4 +6,7 @@ // //===----------------------------------------------------------------------===// -_CLC_OVERLOAD _CLC_DECL __SPIRV_INTN __spirv_ocl_ilogb(__SPIRV_GENTYPE x); +#include + +#define __CLC_BODY +#include diff --git a/libclc/generic/libspirv/math/asin.inc b/libclc/generic/libspirv/math/asin.inc new file mode 100644 index 0000000000000..ebacd008f0352 --- /dev/null +++ b/libclc/generic/libspirv/math/asin.inc @@ -0,0 +1,26 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// TODO: Enable half precision when atan2 is implemented +#if __CLC_FPSIZE > 16 + +#if __CLC_FPSIZE == 64 +#define __CLC_CONST(x) x +#elif __CLC_FPSIZE == 32 +#define __CLC_CONST(x) x##f +#elif __CLC_FPSIZE == 16 +#define __CLC_CONST(x) x##h +#endif + +_CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE __spirv_ocl_asin(__CLC_GENTYPE x) { + return __spirv_ocl_atan2( + x, __spirv_ocl_sqrt((__CLC_GENTYPE)__CLC_CONST(1.0) - (x * x))); +} + +#undef __CLC_CONST + +#endif diff --git a/libclc/generic/libspirv/math/asinh.cl b/libclc/generic/libspirv/math/asinh.cl new file mode 100644 index 0000000000000..10d206846fd45 --- /dev/null +++ b/libclc/generic/libspirv/math/asinh.cl @@ -0,0 +1,363 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include "ep_log.h" +#include +#include + +_CLC_OVERLOAD _CLC_DEF float __spirv_ocl_asinh(float x) { + uint ux = as_uint(x); + uint ax = ux & EXSIGNBIT_SP32; + uint xsgn = ax ^ ux; + + // |x| <= 2 + float t = x * x; + float a = __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, + __spirv_ocl_mad(t, + __spirv_ocl_mad(t, -1.177198915954942694e-4f, + -4.162727710583425360e-2f), + -5.063201055468483248e-1f), + -1.480204186473758321f), + -1.152965835871758072f); + float b = __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, + __spirv_ocl_mad(t, + __spirv_ocl_mad(t, 6.284381367285534560e-2f, + 1.260024978680227945f), + 6.582362487198468066f), + 11.99423176003939087f), + 6.917795026025976739f); + + float q = MATH_DIVIDE(a, b); + float z1 = __spirv_ocl_mad(x * t, q, x); + + // |x| > 2 + + // Arguments greater than 1/sqrt(epsilon) in magnitude are + // approximated by asinh(x) = ln(2) + ln(abs(x)), with sign of x + // Arguments such that 4.0 <= abs(x) <= 1/sqrt(epsilon) are + // approximated by asinhf(x) = ln(abs(x) + sqrt(x*x+1)) + // with the sign of x (see Abramowitz and Stegun 4.6.20) + + float absx = as_float(ax); + int hi = ax > 0x46000000U; + float y = MATH_SQRT(absx * absx + 1.0f) + absx; + y = hi ? absx : y; + float r = __spirv_ocl_log(y) + (hi ? 0x1.62e430p-1f : 0.0f); + float z2 = as_float(xsgn | as_uint(r)); + + float z = ax <= 0x40000000 ? z1 : z2; + z = ax < 0x39800000U || ax >= PINFBITPATT_SP32 ? x : z; + + return z; +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, float, __spirv_ocl_asinh, float) + +#ifdef cl_khr_fp64 +#pragma OPENCL EXTENSION cl_khr_fp64 : enable + +#define NA0 -0.12845379283524906084997e0 +#define NA1 -0.21060688498409799700819e0 +#define NA2 -0.10188951822578188309186e0 +#define NA3 -0.13891765817243625541799e-1 +#define NA4 -0.10324604871728082428024e-3 + +#define DA0 0.77072275701149440164511e0 +#define DA1 0.16104665505597338100747e1 +#define DA2 0.11296034614816689554875e1 +#define DA3 0.30079351943799465092429e0 +#define DA4 0.235224464765951442265117e-1 + +#define NB0 -0.12186605129448852495563e0 +#define NB1 -0.19777978436593069928318e0 +#define NB2 -0.94379072395062374824320e-1 +#define NB3 -0.12620141363821680162036e-1 +#define NB4 -0.903396794842691998748349e-4 + +#define DB0 0.73119630776696495279434e0 +#define DB1 0.15157170446881616648338e1 +#define DB2 0.10524909506981282725413e1 +#define DB3 0.27663713103600182193817e0 +#define DB4 0.21263492900663656707646e-1 + +#define NC0 -0.81210026327726247622500e-1 +#define NC1 -0.12327355080668808750232e0 +#define NC2 -0.53704925162784720405664e-1 +#define NC3 -0.63106739048128554465450e-2 +#define NC4 -0.35326896180771371053534e-4 + +#define DC0 0.48726015805581794231182e0 +#define DC1 0.95890837357081041150936e0 +#define DC2 0.62322223426940387752480e0 +#define DC3 0.15028684818508081155141e0 +#define DC4 0.10302171620320141529445e-1 + +#define ND0 -0.4638179204422665073e-1 +#define ND1 -0.7162729496035415183e-1 +#define ND2 -0.3247795155696775148e-1 +#define ND3 -0.4225785421291932164e-2 +#define ND4 -0.3808984717603160127e-4 +#define ND5 0.8023464184964125826e-6 + +#define DD0 0.2782907534642231184e0 +#define DD1 0.5549945896829343308e0 +#define DD2 0.3700732511330698879e0 +#define DD3 0.9395783438240780722e-1 +#define DD4 0.7200057974217143034e-2 + +#define NE0 -0.121224194072430701e-4 +#define NE1 -0.273145455834305218e-3 +#define NE2 -0.152866982560895737e-2 +#define NE3 -0.292231744584913045e-2 +#define NE4 -0.174670900236060220e-2 +#define NE5 -0.891754209521081538e-12 + +#define DE0 0.499426632161317606e-4 +#define DE1 0.139591210395547054e-2 +#define DE2 0.107665231109108629e-1 +#define DE3 0.325809818749873406e-1 +#define DE4 0.415222526655158363e-1 +#define DE5 0.186315628774716763e-1 + +#define NF0 -0.195436610112717345e-4 +#define NF1 -0.233315515113382977e-3 +#define NF2 -0.645380957611087587e-3 +#define NF3 -0.478948863920281252e-3 +#define NF4 -0.805234112224091742e-12 +#define NF5 0.246428598194879283e-13 + +#define DF0 0.822166621698664729e-4 +#define DF1 0.135346265620413852e-2 +#define DF2 0.602739242861830658e-2 +#define DF3 0.972227795510722956e-2 +#define DF4 0.510878800983771167e-2 + +#define NG0 -0.209689451648100728e-6 +#define NG1 -0.219252358028695992e-5 +#define NG2 -0.551641756327550939e-5 +#define NG3 -0.382300259826830258e-5 +#define NG4 -0.421182121910667329e-17 +#define NG5 0.492236019998237684e-19 + +#define DG0 0.889178444424237735e-6 +#define DG1 0.131152171690011152e-4 +#define DG2 0.537955850185616847e-4 +#define DG3 0.814966175170941864e-4 +#define DG4 0.407786943832260752e-4 + +#define NH0 -0.178284193496441400e-6 +#define NH1 -0.928734186616614974e-6 +#define NH2 -0.923318925566302615e-6 +#define NH3 -0.776417026702577552e-19 +#define NH4 0.290845644810826014e-21 + +#define DH0 0.786694697277890964e-6 +#define DH1 0.685435665630965488e-5 +#define DH2 0.153780175436788329e-4 +#define DH3 0.984873520613417917e-5 + +#define NI0 -0.538003743384069117e-10 +#define NI1 -0.273698654196756169e-9 +#define NI2 -0.268129826956403568e-9 +#define NI3 -0.804163374628432850e-29 + +#define DI0 0.238083376363471960e-9 +#define DI1 0.203579344621125934e-8 +#define DI2 0.450836980450693209e-8 +#define DI3 0.286005148753497156e-8 + +_CLC_OVERLOAD _CLC_DEF double __spirv_ocl_asinh(double x) { + const double rteps = 0x1.6a09e667f3bcdp-27; + const double recrteps = 0x1.6a09e667f3bcdp+26; + + // log2_lead and log2_tail sum to an extra-precise version of log(2) + const double log2_lead = 0x1.62e42ep-1; + const double log2_tail = 0x1.efa39ef35793cp-25; + + ulong ux = as_ulong(x); + ulong ax = ux & ~SIGNBIT_DP64; + double absx = as_double(ax); + + double t = x * x; + double pn, tn, pd, td; + + // XXX we are betting here that we can evaluate 8 pairs of + // polys faster than we can grab 12 coefficients from a table + // This also uses fewer registers + + // |x| >= 8 + pn = __spirv_ocl_fma(t, __spirv_ocl_fma(t, __spirv_ocl_fma(t, NI3, NI2), NI1), + NI0); + pd = __spirv_ocl_fma(t, __spirv_ocl_fma(t, __spirv_ocl_fma(t, DI3, DI2), DI1), + DI0); + + tn = __spirv_ocl_fma( + t, + __spirv_ocl_fma(t, __spirv_ocl_fma(t, __spirv_ocl_fma(t, NH4, NH3), NH2), + NH1), + NH0); + td = __spirv_ocl_fma(t, __spirv_ocl_fma(t, __spirv_ocl_fma(t, DH3, DH2), DH1), + DH0); + pn = absx < 8.0 ? tn : pn; + pd = absx < 8.0 ? td : pd; + + tn = __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, __spirv_ocl_fma(t, __spirv_ocl_fma(t, NG5, NG4), NG3), NG2), + NG1), + NG0); + td = __spirv_ocl_fma( + t, + __spirv_ocl_fma(t, __spirv_ocl_fma(t, __spirv_ocl_fma(t, DG4, DG3), DG2), + DG1), + DG0); + pn = absx < 4.0 ? tn : pn; + pd = absx < 4.0 ? td : pd; + + tn = __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, __spirv_ocl_fma(t, __spirv_ocl_fma(t, NF5, NF4), NF3), NF2), + NF1), + NF0); + td = __spirv_ocl_fma( + t, + __spirv_ocl_fma(t, __spirv_ocl_fma(t, __spirv_ocl_fma(t, DF4, DF3), DF2), + DF1), + DF0); + pn = absx < 2.0 ? tn : pn; + pd = absx < 2.0 ? td : pd; + + tn = __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, __spirv_ocl_fma(t, __spirv_ocl_fma(t, NE5, NE4), NE3), NE2), + NE1), + NE0); + td = __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, __spirv_ocl_fma(t, __spirv_ocl_fma(t, DE5, DE4), DE3), DE2), + DE1), + DE0); + pn = absx < 1.5 ? tn : pn; + pd = absx < 1.5 ? td : pd; + + tn = __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, __spirv_ocl_fma(t, __spirv_ocl_fma(t, ND5, ND4), ND3), ND2), + ND1), + ND0); + td = __spirv_ocl_fma( + t, + __spirv_ocl_fma(t, __spirv_ocl_fma(t, __spirv_ocl_fma(t, DD4, DD3), DD2), + DD1), + DD0); + pn = absx <= 1.0 ? tn : pn; + pd = absx <= 1.0 ? td : pd; + + tn = __spirv_ocl_fma( + t, + __spirv_ocl_fma(t, __spirv_ocl_fma(t, __spirv_ocl_fma(t, NC4, NC3), NC2), + NC1), + NC0); + td = __spirv_ocl_fma( + t, + __spirv_ocl_fma(t, __spirv_ocl_fma(t, __spirv_ocl_fma(t, DC4, DC3), DC2), + DC1), + DC0); + pn = absx < 0.75 ? tn : pn; + pd = absx < 0.75 ? td : pd; + + tn = __spirv_ocl_fma( + t, + __spirv_ocl_fma(t, __spirv_ocl_fma(t, __spirv_ocl_fma(t, NB4, NB3), NB2), + NB1), + NB0); + td = __spirv_ocl_fma( + t, + __spirv_ocl_fma(t, __spirv_ocl_fma(t, __spirv_ocl_fma(t, DB4, DB3), DB2), + DB1), + DB0); + pn = absx < 0.5 ? tn : pn; + pd = absx < 0.5 ? td : pd; + + tn = __spirv_ocl_fma( + t, + __spirv_ocl_fma(t, __spirv_ocl_fma(t, __spirv_ocl_fma(t, NA4, NA3), NA2), + NA1), + NA0); + td = __spirv_ocl_fma( + t, + __spirv_ocl_fma(t, __spirv_ocl_fma(t, __spirv_ocl_fma(t, DA4, DA3), DA2), + DA1), + DA0); + pn = absx < 0.25 ? tn : pn; + pd = absx < 0.25 ? td : pd; + + double pq = MATH_DIVIDE(pn, pd); + + // |x| <= 1 + double result1 = __spirv_ocl_fma(absx * t, pq, absx); + + // Other ranges + int xout = absx <= 32.0 | absx > recrteps; + double y = absx + __spirv_ocl_sqrt(__spirv_ocl_fma(absx, absx, 1.0)); + y = xout ? absx : y; + + double r1, r2; + int xexp; + __clc_ep_log(y, &xexp, &r1, &r2); + + double dxexp = (double)(xexp + xout); + r1 = __spirv_ocl_fma(dxexp, log2_lead, r1); + r2 = __spirv_ocl_fma(dxexp, log2_tail, r2); + + // 1 < x <= 32 + double v2 = (pq + 0.25) / t; + double r = v2 + r1; + double s = ((r1 - r) + v2) + r2; + double v1 = r + s; + v2 = (r - v1) + s; + double result2 = v1 + v2; + + // x > 32 + double result3 = r1 + r2; + + double ret = absx > 1.0 ? result2 : result1; + ret = absx > 32.0 ? result3 : ret; + ret = x < 0.0 ? -ret : ret; + + // NaN, +-Inf, or x small enough that asinh(x) = x + ret = ax >= PINFBITPATT_DP64 || absx < rteps ? x : ret; + return ret; +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, double, __spirv_ocl_asinh, double) + +#endif diff --git a/libclc/generic/libspirv/math/asinpi.cl b/libclc/generic/libspirv/math/asinpi.cl new file mode 100644 index 0000000000000..f58aad0cbaa28 --- /dev/null +++ b/libclc/generic/libspirv/math/asinpi.cl @@ -0,0 +1,176 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include +#include + +_CLC_OVERLOAD _CLC_DEF float __spirv_ocl_asinpi(float x) { + // Computes arcsin(x). + // The argument is first reduced by noting that arcsin(x) + // is invalid for abs(x) > 1 and arcsin(-x) = -arcsin(x). + // For denormal and small arguments arcsin(x) = x to machine + // accuracy. Remaining argument ranges are handled as follows. + // For abs(x) <= 0.5 use + // arcsin(x) = x + x^3*R(x^2) + // where R(x^2) is a rational minimax approximation to + // (arcsin(x) - x)/x^3. + // For abs(x) > 0.5 exploit the identity: + // arcsin(x) = pi/2 - 2*arcsin(sqrt(1-x)/2) + // together with the above rational approximation, and + // reconstruct the terms carefully. + + const float pi = 3.1415926535897933e+00f; + const float piby2_tail = 7.5497894159e-08F; /* 0x33a22168 */ + const float hpiby2_head = 7.8539812565e-01F; /* 0x3f490fda */ + + uint ux = as_uint(x); + uint aux = ux & EXSIGNBIT_SP32; + uint xs = ux ^ aux; + float shalf = as_float(xs | as_uint(0.5f)); + + int xexp = (int)(aux >> EXPSHIFTBITS_SP32) - EXPBIAS_SP32; + + float y = as_float(aux); + + // abs(x) >= 0.5 + int transform = xexp >= -1; + + float y2 = y * y; + float rt = 0.5f * (1.0f - y); + float r = transform ? rt : y2; + + // Use a rational approximation for [0.0, 0.5] + float a = __spirv_ocl_mad( + r, + __spirv_ocl_mad(r, + __spirv_ocl_mad(r, -0.00396137437848476485201154797087F, + -0.0133819288943925804214011424456F), + -0.0565298683201845211985026327361F), + 0.184161606965100694821398249421F); + float b = __spirv_ocl_mad(r, -0.836411276854206731913362287293F, + 1.10496961524520294485512696706F); + float u = r * MATH_DIVIDE(a, b); + + float s = MATH_SQRT(r); + float s1 = as_float(as_uint(s) & 0xffff0000); + float c = MATH_DIVIDE(__spirv_ocl_mad(-s1, s1, r), s + s1); + float p = + __spirv_ocl_mad(2.0f * s, u, -__spirv_ocl_mad(c, -2.0f, piby2_tail)); + float q = __spirv_ocl_mad(s1, -2.0f, hpiby2_head); + float vt = hpiby2_head - (p - q); + float v = __spirv_ocl_mad(y, u, y); + v = transform ? vt : v; + v = MATH_DIVIDE(v, pi); + float xbypi = MATH_DIVIDE(x, pi); + + float ret = as_float(xs | as_uint(v)); + ret = aux > 0x3f800000U ? as_float(QNANBITPATT_SP32) : ret; + ret = aux == 0x3f800000U ? shalf : ret; + ret = xexp < -14 ? xbypi : ret; + + return ret; +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, float, __spirv_ocl_asinpi, float) + +#ifdef cl_khr_fp64 +#pragma OPENCL EXTENSION cl_khr_fp64 : enable + +_CLC_OVERLOAD _CLC_DEF double __spirv_ocl_asinpi(double x) { + // Computes arcsin(x). + // The argument is first reduced by noting that arcsin(x) + // is invalid for abs(x) > 1 and arcsin(-x) = -arcsin(x). + // For denormal and small arguments arcsin(x) = x to machine + // accuracy. Remaining argument ranges are handled as follows. + // For abs(x) <= 0.5 use + // arcsin(x) = x + x^3*R(x^2) + // where R(x^2) is a rational minimax approximation to + // (arcsin(x) - x)/x^3. + // For abs(x) > 0.5 exploit the identity: + // arcsin(x) = pi/2 - 2*arcsin(sqrt(1-x)/2) + // together with the above rational approximation, and + // reconstruct the terms carefully. + + const double pi = 0x1.921fb54442d18p+1; + const double piby2_tail = 6.1232339957367660e-17; /* 0x3c91a62633145c07 */ + const double hpiby2_head = 7.8539816339744831e-01; /* 0x3fe921fb54442d18 */ + + double y = __spirv_ocl_fabs(x); + int xneg = as_int2(x).hi < 0; + int xexp = (as_int2(y).hi >> 20) - EXPBIAS_DP64; + + // abs(x) >= 0.5 + int transform = xexp >= -1; + + double rt = 0.5 * (1.0 - y); + double y2 = y * y; + double r = transform ? rt : y2; + + // Use a rational approximation for [0.0, 0.5] + double un = __spirv_ocl_fma( + r, + __spirv_ocl_fma( + r, + __spirv_ocl_fma( + r, + __spirv_ocl_fma( + r, + __spirv_ocl_fma(r, 0.0000482901920344786991880522822991, + 0.00109242697235074662306043804220), + -0.0549989809235685841612020091328), + 0.275558175256937652532686256258), + -0.445017216867635649900123110649), + 0.227485835556935010735943483075); + + double ud = __spirv_ocl_fma( + r, + __spirv_ocl_fma( + r, + __spirv_ocl_fma(r, + __spirv_ocl_fma(r, 0.105869422087204370341222318533, + -0.943639137032492685763471240072), + 2.76568859157270989520376345954), + -3.28431505720958658909889444194), + 1.36491501334161032038194214209); + + double u = r * MATH_DIVIDE(un, ud); + + // Reconstruct asin carefully in transformed region + double s = __spirv_ocl_sqrt(r); + double sh = as_double(as_ulong(s) & 0xffffffff00000000UL); + double c = MATH_DIVIDE(__spirv_ocl_fma(-sh, sh, r), s + sh); + double p = __spirv_ocl_fma(2.0 * s, u, -__spirv_ocl_fma(-2.0, c, piby2_tail)); + double q = __spirv_ocl_fma(-2.0, sh, hpiby2_head); + double vt = hpiby2_head - (p - q); + double v = __spirv_ocl_fma(y, u, y); + v = transform ? vt : v; + + v = xexp < -28 ? y : v; + v = MATH_DIVIDE(v, pi); + v = xexp >= 0 ? as_double(QNANBITPATT_DP64) : v; + v = y == 1.0 ? 0.5 : v; + return xneg ? -v : v; +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, double, __spirv_ocl_asinpi, double) + +#endif + +#ifdef cl_khr_fp16 +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +_CLC_OVERLOAD _CLC_DEF half __spirv_ocl_asinpi(half x) { + float t = x; + return __spirv_ocl_asinpi(t); +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, half, __spirv_ocl_asinpi, half) + +#endif diff --git a/libclc/generic/libspirv/math/atan.cl b/libclc/generic/libspirv/math/atan.cl new file mode 100644 index 0000000000000..4dadde766f286 --- /dev/null +++ b/libclc/generic/libspirv/math/atan.cl @@ -0,0 +1,175 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include +#include + +_CLC_OVERLOAD _CLC_DEF float __spirv_ocl_atan(float x) { + const float piby2 = 1.5707963267948966f; // 0x3ff921fb54442d18 + + uint ux = as_uint(x); + uint aux = ux & EXSIGNBIT_SP32; + uint sx = ux ^ aux; + + float spiby2 = as_float(sx | as_uint(piby2)); + + float v = as_float(aux); + + // Return for NaN + float ret = x; + + // 2^26 <= |x| <= Inf => atan(x) is close to piby2 + ret = aux <= PINFBITPATT_SP32 ? spiby2 : ret; + + // Reduce arguments 2^-19 <= |x| < 2^26 + + // 39/16 <= x < 2^26 + x = -MATH_RECIP(v); + float c = 1.57079632679489655800f; // atan(infinity) + + // 19/16 <= x < 39/16 + int l = aux < 0x401c0000; + float xx = MATH_DIVIDE(v - 1.5f, __spirv_ocl_mad(v, 1.5f, 1.0f)); + x = l ? xx : x; + c = l ? 9.82793723247329054082e-01f : c; // atan(1.5) + + // 11/16 <= x < 19/16 + l = aux < 0x3f980000U; + xx = MATH_DIVIDE(v - 1.0f, 1.0f + v); + x = l ? xx : x; + c = l ? 7.85398163397448278999e-01f : c; // atan(1) + + // 7/16 <= x < 11/16 + l = aux < 0x3f300000; + xx = MATH_DIVIDE(__spirv_ocl_mad(v, 2.0f, -1.0f), 2.0f + v); + x = l ? xx : x; + c = l ? 4.63647609000806093515e-01f : c; // atan(0.5) + + // 2^-19 <= x < 7/16 + l = aux < 0x3ee00000; + x = l ? v : x; + c = l ? 0.0f : c; + + // Core approximation: Remez(2,2) on [-7/16,7/16] + + float s = x * x; + float a = + __spirv_ocl_mad(s, + __spirv_ocl_mad(s, 0.470677934286149214138357545549e-2f, + 0.192324546402108583211697690500f), + 0.296528598819239217902158651186f); + + float b = + __spirv_ocl_mad(s, + __spirv_ocl_mad(s, 0.299309699959659728404442796915f, + 0.111072499995399550138837673349e1f), + 0.889585796862432286486651434570f); + + float q = x * s * MATH_DIVIDE(a, b); + + float z = c - (q - x); + float zs = as_float(sx | as_uint(z)); + + ret = aux < 0x4c800000 ? zs : ret; + + // |x| < 2^-19 + ret = aux < 0x36000000 ? as_float(ux) : ret; + return ret; +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, float, __spirv_ocl_atan, float); + +#ifdef cl_khr_fp64 + +#pragma OPENCL EXTENSION cl_khr_fp64 : enable + +_CLC_OVERLOAD _CLC_DEF double __spirv_ocl_atan(double x) { + const double piby2 = 1.5707963267948966e+00; // 0x3ff921fb54442d18 + + double v = __spirv_ocl_fabs(x); + + // 2^56 > v > 39/16 + double a = -1.0; + double b = v; + // (chi + clo) = arctan(infinity) + double chi = 1.57079632679489655800e+00; + double clo = 6.12323399573676480327e-17; + + double ta = v - 1.5; + double tb = 1.0 + 1.5 * v; + int l = v <= 0x1.38p+1; // 39/16 > v > 19/16 + a = l ? ta : a; + b = l ? tb : b; + // (chi + clo) = arctan(1.5) + chi = l ? 9.82793723247329054082e-01 : chi; + clo = l ? 1.39033110312309953701e-17 : clo; + + ta = v - 1.0; + tb = 1.0 + v; + l = v <= 0x1.3p+0; // 19/16 > v > 11/16 + a = l ? ta : a; + b = l ? tb : b; + // (chi + clo) = arctan(1.) + chi = l ? 7.85398163397448278999e-01 : chi; + clo = l ? 3.06161699786838240164e-17 : clo; + + ta = 2.0 * v - 1.0; + tb = 2.0 + v; + l = v <= 0x1.6p-1; // 11/16 > v > 7/16 + a = l ? ta : a; + b = l ? tb : b; + // (chi + clo) = arctan(0.5) + chi = l ? 4.63647609000806093515e-01 : chi; + clo = l ? 2.26987774529616809294e-17 : clo; + + l = v <= 0x1.cp-2; // v < 7/16 + a = l ? v : a; + b = l ? 1.0 : b; + ; + chi = l ? 0.0 : chi; + clo = l ? 0.0 : clo; + + // Core approximation: Remez(4,4) on [-7/16,7/16] + double r = a / b; + double s = r * r; + double qn = __spirv_ocl_fma( + s, + __spirv_ocl_fma( + s, + __spirv_ocl_fma(s, + __spirv_ocl_fma(s, 0.142316903342317766e-3, + 0.304455919504853031e-1), + 0.220638780716667420e0), + 0.447677206805497472e0), + 0.268297920532545909e0); + + double qd = __spirv_ocl_fma( + s, + __spirv_ocl_fma( + s, + __spirv_ocl_fma(s, + __spirv_ocl_fma(s, 0.389525873944742195e-1, + 0.424602594203847109e0), + 0.141254259931958921e1), + 0.182596787737507063e1), + 0.804893761597637733e0); + + double q = r * s * qn / qd; + r = chi - ((q - clo) - r); + + double z = __spirv_IsNan(x) ? x : piby2; + z = v <= 0x1.0p+56 ? r : z; + z = v < 0x1.0p-26 ? v : z; + return x == v ? z : -z; +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, double, __spirv_ocl_atan, double); + +#endif // cl_khr_fp64 diff --git a/libclc/generic/libspirv/math/atan2.cl b/libclc/generic/libspirv/math/atan2.cl new file mode 100644 index 0000000000000..e6cce7868ff3b --- /dev/null +++ b/libclc/generic/libspirv/math/atan2.cl @@ -0,0 +1,247 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include "tables.h" +#include +#include + +_CLC_OVERLOAD _CLC_DEF float __spirv_ocl_atan2(float y, float x) { + const float pi = 0x1.921fb6p+1f; + const float piby2 = 0x1.921fb6p+0f; + const float piby4 = 0x1.921fb6p-1f; + const float threepiby4 = 0x1.2d97c8p+1f; + + float ax = __spirv_ocl_fabs(x); + float ay = __spirv_ocl_fabs(y); + float v = __spirv_ocl_fmin(ax, ay); + float u = __spirv_ocl_fmax(ax, ay); + + // Scale since u could be large, as in "regular" divide + float s = u > 0x1.0p+96f ? 0x1.0p-32f : 1.0f; + float vbyu = s * MATH_DIVIDE(v, s * u); + + float vbyu2 = vbyu * vbyu; + +#define USE_2_2_APPROXIMATION +#if defined USE_2_2_APPROXIMATION + float p = __spirv_ocl_mad( + vbyu2, __spirv_ocl_mad(vbyu2, -0x1.7e1f78p-9f, -0x1.7d1b98p-3f), + -0x1.5554d0p-2f) * + vbyu2 * vbyu; + float q = __spirv_ocl_mad( + vbyu2, __spirv_ocl_mad(vbyu2, 0x1.1a714cp-2f, 0x1.287c56p+0f), 1.0f); +#else + float p = __spirv_ocl_mad( + vbyu2, __spirv_ocl_mad(vbyu2, -0x1.55cd22p-5f, -0x1.26cf76p-2f), + -0x1.55554ep-2f) * + vbyu2 * vbyu; + float q = __spirv_ocl_mad( + vbyu2, + __spirv_ocl_mad(vbyu2, + __spirv_ocl_mad(vbyu2, 0x1.9f1304p-5f, 0x1.2656fap-1f), + 0x1.76b4b8p+0f), + 1.0f); +#endif + + // Octant 0 result + float a = __spirv_ocl_mad(p, MATH_RECIP(q), vbyu); + + // Fix up 3 other octants + float at = piby2 - a; + a = ay > ax ? at : a; + at = pi - a; + a = x < 0.0F ? at : a; + + // y == 0 => 0 for x >= 0, pi for x < 0 + at = as_int(x) < 0 ? pi : 0.0f; + a = y == 0.0f ? at : a; + + // if (!FINITE_ONLY()) { + // x and y are +- Inf + at = x > 0.0f ? piby4 : threepiby4; + a = ax == INFINITY && ay == INFINITY ? at : a; + + // x or y is NaN + a = __spirv_IsNan(x) || __spirv_IsNan(y) ? as_float(QNANBITPATT_SP32) : a; + // } + + // Fixup sign and return + return __spirv_ocl_copysign(a, y); +} + +_CLC_BINARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, float, __spirv_ocl_atan2, float, + float); + +#ifdef cl_khr_fp64 + +#pragma OPENCL EXTENSION cl_khr_fp64 : enable + +_CLC_OVERLOAD _CLC_DEF double __spirv_ocl_atan2(double y, double x) { + const double pi = 3.1415926535897932e+00; /* 0x400921fb54442d18 */ + const double piby2 = 1.5707963267948966e+00; /* 0x3ff921fb54442d18 */ + const double piby4 = 7.8539816339744831e-01; /* 0x3fe921fb54442d18 */ + const double three_piby4 = 2.3561944901923449e+00; /* 0x4002d97c7f3321d2 */ + const double pi_head = 3.1415926218032836e+00; /* 0x400921fb50000000 */ + const double pi_tail = 3.1786509547056392e-08; /* 0x3e6110b4611a6263 */ + const double piby2_head = 1.5707963267948965e+00; /* 0x3ff921fb54442d18 */ + const double piby2_tail = 6.1232339957367660e-17; /* 0x3c91a62633145c07 */ + + double x2 = x; + int xneg = as_int2(x).hi < 0; + int xexp = (as_int2(x).hi >> 20) & 0x7ff; + + double y2 = y; + int yneg = as_int2(y).hi < 0; + int yexp = (as_int2(y).hi >> 20) & 0x7ff; + + int cond2 = (xexp < 1021) & (yexp < 1021); + int diffexp = yexp - xexp; + + // Scale up both x and y if they are both below 1/4 + double x1 = __spirv_ocl_ldexp(x, 1024); + int xexp1 = (as_int2(x1).hi >> 20) & 0x7ff; + double y1 = __spirv_ocl_ldexp(y, 1024); + int yexp1 = (as_int2(y1).hi >> 20) & 0x7ff; + int diffexp1 = yexp1 - xexp1; + + diffexp = cond2 ? diffexp1 : diffexp; + x = cond2 ? x1 : x; + y = cond2 ? y1 : y; + + // General case: take absolute values of arguments + double u = __spirv_ocl_fabs(x); + double v = __spirv_ocl_fabs(y); + + // Swap u and v if necessary to obtain 0 < v < u. Compute v/u. + int swap_vu = u < v; + double uu = u; + u = swap_vu ? v : u; + v = swap_vu ? uu : v; + + double vbyu = v / u; + double q1, q2; + + // General values of v/u. Use a look-up table and series expansion. + + { + double val = vbyu > 0.0625 ? vbyu : 0.063; + int index = __spirv_ConvertFToS_Rint(__spirv_ocl_fma(256.0, val, 0.5)); + double2 tv = USE_TABLE(atan_jby256_tbl, index - 16); + q1 = tv.s0; + q2 = tv.s1; + double c = (double)index * 0x1.0p-8; + + // We're going to scale u and v by 2^(-u_exponent) to bring them close to 1 + // u_exponent could be EMAX so we have to do it in 2 steps + int m = -((int)(as_ulong(u) >> EXPSHIFTBITS_DP64) - EXPBIAS_DP64); + // double um = __amdil_ldexp_f64(u, m); + // double vm = __amdil_ldexp_f64(v, m); + double um = __spirv_ocl_ldexp(u, m); + double vm = __spirv_ocl_ldexp(v, m); + + // 26 leading bits of u + double u1 = as_double(as_ulong(um) & 0xfffffffff8000000UL); + double u2 = um - u1; + + double r = MATH_DIVIDE(__spirv_ocl_fma(-c, u2, __spirv_ocl_fma(-c, u1, vm)), + __spirv_ocl_fma(c, vm, um)); + + // Polynomial approximation to atan(r) + double s = r * r; + q2 = q2 + __spirv_ocl_fma((s * __spirv_ocl_fma(-s, 0.19999918038989143496, + 0.33333333333224095522)), + -r, r); + } + + double q3, q4; + { + q3 = 0.0; + q4 = vbyu; + } + + double q5, q6; + { + double u1 = as_double(as_ulong(u) & 0xffffffff00000000UL); + double u2 = u - u1; + double vu1 = as_double(as_ulong(vbyu) & 0xffffffff00000000UL); + double vu2 = vbyu - vu1; + + q5 = 0.0; + double s = vbyu * vbyu; + q6 = vbyu + + __spirv_ocl_fma( + -vbyu * s, + __spirv_ocl_fma( + -s, + __spirv_ocl_fma( + -s, + __spirv_ocl_fma(-s, + __spirv_ocl_fma(-s, + 0.90029810285449784439E-01, + 0.11110736283514525407), + 0.14285713561807169030), + 0.19999999999393223405), + 0.33333333333333170500), + MATH_DIVIDE( + __spirv_ocl_fma( + -u, vu2, + __spirv_ocl_fma(-u2, vu1, __spirv_ocl_fma(-u1, vu1, v))), + u)); + } + + q3 = vbyu < 0x1.d12ed0af1a27fp-27 ? q3 : q5; + q4 = vbyu < 0x1.d12ed0af1a27fp-27 ? q4 : q6; + + q1 = vbyu > 0.0625 ? q1 : q3; + q2 = vbyu > 0.0625 ? q2 : q4; + + // Tidy-up according to which quadrant the arguments lie in + double res1, res2, res3, res4; + q1 = swap_vu ? piby2_head - q1 : q1; + q2 = swap_vu ? piby2_tail - q2 : q2; + q1 = xneg ? pi_head - q1 : q1; + q2 = xneg ? pi_tail - q2 : q2; + q1 = q1 + q2; + res4 = yneg ? -q1 : q1; + + res1 = yneg ? -three_piby4 : three_piby4; + res2 = yneg ? -piby4 : piby4; + res3 = xneg ? res1 : res2; + + res3 = __spirv_IsInf(x2) && __spirv_IsInf(y2) ? res3 : res4; + res1 = yneg ? -pi : pi; + + // abs(x)/abs(y) > 2^56 and x < 0 + res3 = (diffexp < -56 && xneg) ? res1 : res3; + + res4 = MATH_DIVIDE(y, x); + // x positive and dominant over y by a factor of 2^28 + res3 = diffexp < -28 && xneg == 0 ? res4 : res3; + + // abs(y)/abs(x) > 2^56 + res4 = yneg ? -piby2 : piby2; // atan(y/x) is insignificant compared to piby2 + res3 = diffexp > 56 ? res4 : res3; + + res3 = x2 == 0.0 ? res4 : res3; // Zero x gives +- pi/2 depending on sign of y + res4 = xneg ? res1 : y2; + + res3 = y2 == 0.0 + ? res4 + : res3; // Zero y gives +-0 for positive x and +-pi for negative x + res3 = __spirv_IsNan(y2) ? y2 : res3; + res3 = __spirv_IsNan(x2) ? x2 : res3; + + return res3; +} + +_CLC_BINARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, double, __spirv_ocl_atan2, double, + double); + +#endif diff --git a/libclc/generic/libspirv/math/atan2pi.cl b/libclc/generic/libspirv/math/atan2pi.cl new file mode 100644 index 0000000000000..487fb4bb0003b --- /dev/null +++ b/libclc/generic/libspirv/math/atan2pi.cl @@ -0,0 +1,236 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include "tables.h" +#include +#include + +_CLC_OVERLOAD _CLC_DEF float __spirv_ocl_atan2pi(float y, float x) { + const float pi = 0x1.921fb6p+1f; + + float ax = __spirv_ocl_fabs(x); + float ay = __spirv_ocl_fabs(y); + float v = __spirv_ocl_fmin(ax, ay); + float u = __spirv_ocl_fmax(ax, ay); + + // Scale since u could be large, as in "regular" divide + float s = u > 0x1.0p+96f ? 0x1.0p-32f : 1.0f; + float vbyu = s * MATH_DIVIDE(v, s * u); + + float vbyu2 = vbyu * vbyu; + + float p = __spirv_ocl_mad( + vbyu2, __spirv_ocl_mad(vbyu2, -0x1.7e1f78p-9f, -0x1.7d1b98p-3f), + -0x1.5554d0p-2f) * + vbyu2 * vbyu; + float q = __spirv_ocl_mad( + vbyu2, __spirv_ocl_mad(vbyu2, 0x1.1a714cp-2f, 0x1.287c56p+0f), 1.0f); + + // Octant 0 result + float a = MATH_DIVIDE(__spirv_ocl_mad(p, MATH_RECIP(q), vbyu), pi); + + // Fix up 3 other octants + float at = 0.5f - a; + a = ay > ax ? at : a; + at = 1.0f - a; + a = x < 0.0F ? at : a; + + // y == 0 => 0 for x >= 0, pi for x < 0 + at = as_int(x) < 0 ? 1.0f : 0.0f; + a = y == 0.0f ? at : a; + + // if (!FINITE_ONLY()) { + // x and y are +- Inf + at = x > 0.0f ? 0.25f : 0.75f; + a = ax == INFINITY && ay == INFINITY ? at : a; + + // x or y is NaN + a = __spirv_IsNan(x) || __spirv_IsNan(y) ? as_float(QNANBITPATT_SP32) : a; + // } + + // Fixup sign and return + return __spirv_ocl_copysign(a, y); +} + +_CLC_BINARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, float, __spirv_ocl_atan2pi, float, + float) + +#ifdef cl_khr_fp64 +#pragma OPENCL EXTENSION cl_khr_fp64 : enable + +_CLC_OVERLOAD _CLC_DEF double __spirv_ocl_atan2pi(double y, double x) { + const double pi = 3.1415926535897932e+00; /* 0x400921fb54442d18 */ + const double pi_head = 3.1415926218032836e+00; /* 0x400921fb50000000 */ + const double pi_tail = 3.1786509547056392e-08; /* 0x3e6110b4611a6263 */ + const double piby2_head = 1.5707963267948965e+00; /* 0x3ff921fb54442d18 */ + const double piby2_tail = 6.1232339957367660e-17; /* 0x3c91a62633145c07 */ + + double x2 = x; + int xneg = as_int2(x).hi < 0; + int xexp = (as_int2(x).hi >> 20) & 0x7ff; + + double y2 = y; + int yneg = as_int2(y).hi < 0; + int yexp = (as_int2(y).hi >> 20) & 0x7ff; + + int cond2 = (xexp < 1021) & (yexp < 1021); + int diffexp = yexp - xexp; + + // Scale up both x and y if they are both below 1/4 + double x1 = __spirv_ocl_ldexp(x, 1024); + int xexp1 = (as_int2(x1).hi >> 20) & 0x7ff; + double y1 = __spirv_ocl_ldexp(y, 1024); + int yexp1 = (as_int2(y1).hi >> 20) & 0x7ff; + int diffexp1 = yexp1 - xexp1; + + diffexp = cond2 ? diffexp1 : diffexp; + x = cond2 ? x1 : x; + y = cond2 ? y1 : y; + + // General case: take absolute values of arguments + double u = __spirv_ocl_fabs(x); + double v = __spirv_ocl_fabs(y); + + // Swap u and v if necessary to obtain 0 < v < u. Compute v/u. + int swap_vu = u < v; + double uu = u; + u = swap_vu ? v : u; + v = swap_vu ? uu : v; + + double vbyu = v / u; + double q1, q2; + + // General values of v/u. Use a look-up table and series expansion. + + { + double val = vbyu > 0.0625 ? vbyu : 0.063; + int index = __spirv_ConvertFToS_Rint(__spirv_ocl_fma(256.0, val, 0.5)); + double2 tv = USE_TABLE(atan_jby256_tbl, (index - 16)); + q1 = tv.s0; + q2 = tv.s1; + double c = (double)index * 0x1.0p-8; + + // We're going to scale u and v by 2^(-u_exponent) to bring them close to 1 + // u_exponent could be EMAX so we have to do it in 2 steps + int m = -((int)(as_ulong(u) >> EXPSHIFTBITS_DP64) - EXPBIAS_DP64); + double um = __spirv_ocl_ldexp(u, m); + double vm = __spirv_ocl_ldexp(v, m); + + // 26 leading bits of u + double u1 = as_double(as_ulong(um) & 0xfffffffff8000000UL); + double u2 = um - u1; + + double r = MATH_DIVIDE(__spirv_ocl_fma(-c, u2, __spirv_ocl_fma(-c, u1, vm)), + __spirv_ocl_fma(c, vm, um)); + + // Polynomial approximation to atan(r) + double s = r * r; + q2 = q2 + __spirv_ocl_fma((s * __spirv_ocl_fma(-s, 0.19999918038989143496, + 0.33333333333224095522)), + -r, r); + } + + double q3, q4; + { + q3 = 0.0; + q4 = vbyu; + } + + double q5, q6; + { + double u1 = as_double(as_ulong(u) & 0xffffffff00000000UL); + double u2 = u - u1; + double vu1 = as_double(as_ulong(vbyu) & 0xffffffff00000000UL); + double vu2 = vbyu - vu1; + + q5 = 0.0; + double s = vbyu * vbyu; + q6 = vbyu + + __spirv_ocl_fma( + -vbyu * s, + __spirv_ocl_fma( + -s, + __spirv_ocl_fma( + -s, + __spirv_ocl_fma(-s, + __spirv_ocl_fma(-s, + 0.90029810285449784439E-01, + 0.11110736283514525407), + 0.14285713561807169030), + 0.19999999999393223405), + 0.33333333333333170500), + MATH_DIVIDE( + __spirv_ocl_fma( + -u, vu2, + __spirv_ocl_fma(-u2, vu1, __spirv_ocl_fma(-u1, vu1, v))), + u)); + } + + q3 = vbyu < 0x1.d12ed0af1a27fp-27 ? q3 : q5; + q4 = vbyu < 0x1.d12ed0af1a27fp-27 ? q4 : q6; + + q1 = vbyu > 0.0625 ? q1 : q3; + q2 = vbyu > 0.0625 ? q2 : q4; + + // Tidy-up according to which quadrant the arguments lie in + double res1, res2, res3, res4; + q1 = swap_vu ? piby2_head - q1 : q1; + q2 = swap_vu ? piby2_tail - q2 : q2; + q1 = xneg ? pi_head - q1 : q1; + q2 = xneg ? pi_tail - q2 : q2; + q1 = MATH_DIVIDE(q1 + q2, pi); + res4 = yneg ? -q1 : q1; + + res1 = yneg ? -0.75 : 0.75; + res2 = yneg ? -0.25 : 0.25; + res3 = xneg ? res1 : res2; + + res3 = __spirv_IsInf(y2) && __spirv_IsInf(x2) ? res3 : res4; + res1 = yneg ? -1.0 : 1.0; + + // abs(x)/abs(y) > 2^56 and x < 0 + res3 = (diffexp < -56 && xneg) ? res1 : res3; + + res4 = MATH_DIVIDE(MATH_DIVIDE(y, x), pi); + // x positive and dominant over y by a factor of 2^28 + res3 = diffexp < -28 && xneg == 0 ? res4 : res3; + + // abs(y)/abs(x) > 2^56 + res4 = yneg ? -0.5 : 0.5; // atan(y/x) is insignificant compared to piby2 + res3 = diffexp > 56 ? res4 : res3; + + res3 = x2 == 0.0 ? res4 : res3; // Zero x gives +- pi/2 depending on sign of y + res4 = xneg ? res1 : y2; + + res3 = y2 == 0.0 + ? res4 + : res3; // Zero y gives +-0 for positive x and +-pi for negative x + res3 = __spirv_IsNan(y2) ? y2 : res3; + res3 = __spirv_IsNan(x2) ? x2 : res3; + + return res3; +} + +_CLC_BINARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, double, __spirv_ocl_atan2pi, + double, double) + +#endif + +#ifdef cl_khr_fp16 +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +_CLC_OVERLOAD _CLC_DEF half __spirv_ocl_atan2pi(half x, half y) { + return __spirv_ocl_atan2pi((float)x, (float)y); +} + +_CLC_BINARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, half, __spirv_ocl_atan2pi, half, + half) + +#endif diff --git a/libclc/generic/libspirv/math/atanh.cl b/libclc/generic/libspirv/math/atanh.cl new file mode 100644 index 0000000000000..57c79ead97118 --- /dev/null +++ b/libclc/generic/libspirv/math/atanh.cl @@ -0,0 +1,124 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include +#include + +_CLC_OVERLOAD _CLC_DEF float __spirv_ocl_atanh(float x) { + uint ux = as_uint(x); + uint ax = ux & EXSIGNBIT_SP32; + uint xs = ux ^ ax; + + // |x| > 1 or NaN + float z = as_float(QNANBITPATT_SP32); + + // |x| == 1 + float t = as_float(xs | PINFBITPATT_SP32); + z = ax == 0x3f800000U ? t : z; + + // 1/2 <= |x| < 1 + t = as_float(ax); + t = MATH_DIVIDE(2.0f * t, 1.0f - t); + t = 0.5f * __spirv_ocl_log1p(t); + t = as_float(xs | as_uint(t)); + z = ax < 0x3f800000U ? t : z; + + // |x| < 1/2 + t = x * x; + float a = + __spirv_ocl_mad(__spirv_ocl_mad(0.92834212715e-2f, t, -0.28120347286e0f), + t, 0.39453629046e0f); + float b = + __spirv_ocl_mad(__spirv_ocl_mad(0.45281890445e0f, t, -0.15537744551e1f), + t, 0.11836088638e1f); + float p = MATH_DIVIDE(a, b); + t = __spirv_ocl_mad(x * t, p, x); + z = ax < 0x3f000000 ? t : z; + + // |x| < 2^-13 + z = ax < 0x39000000U ? x : z; + + return z; +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, float, __spirv_ocl_atanh, float) + +#ifdef cl_khr_fp64 +#pragma OPENCL EXTENSION cl_khr_fp64 : enable + +_CLC_OVERLOAD _CLC_DEF double __spirv_ocl_atanh(double x) { + double absx = __spirv_ocl_fabs(x); + + double ret = + absx == 1.0 ? as_double(PINFBITPATT_DP64) : as_double(QNANBITPATT_DP64); + + // |x| >= 0.5 + // Note that atanh(x) = 0.5 * ln((1+x)/(1-x)) + // For greater accuracy we use + // ln((1+x)/(1-x)) = ln(1 + 2x/(1-x)) = log1p(2x/(1-x)). + double r = 0.5 * __spirv_ocl_log1p(2.0 * absx / (1.0 - absx)); + ret = absx < 1.0 ? r : ret; + + r = -ret; + ret = x < 0.0 ? r : ret; + + // Arguments up to 0.5 in magnitude are + // approximated by a [5,5] minimax polynomial + double t = x * x; + + double pn = __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, + __spirv_ocl_fma(t, + __spirv_ocl_fma(t, -0.10468158892753136958e-3, + 0.28728638600548514553e-1), + -0.28180210961780814148e0), + 0.88468142536501647470e0), + -0.11028356797846341457e1), + 0.47482573589747356373e0); + + double pd = __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, + __spirv_ocl_fma(t, + __spirv_ocl_fma(t, -0.35861554370169537512e-1, + 0.49561196555503101989e0), + -0.22608883748988489342e1), + 0.45414700626084508355e1), + -0.41631933639693546274e1), + 0.14244772076924206909e1); + + r = __spirv_ocl_fma(x * t, pn / pd, x); + ret = absx < 0.5 ? r : ret; + + return ret; +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, double, __spirv_ocl_atanh, double) + +#endif + +#ifdef cl_khr_fp16 +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +_CLC_OVERLOAD _CLC_DEF half __spirv_ocl_atanh(half x) { + float t = x; + return __spirv_ocl_atanh(t); +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, half, __spirv_ocl_atanh, half) + +#endif diff --git a/libclc/generic/libspirv/math/atanpi.cl b/libclc/generic/libspirv/math/atanpi.cl new file mode 100644 index 0000000000000..d387d9e7b4b89 --- /dev/null +++ b/libclc/generic/libspirv/math/atanpi.cl @@ -0,0 +1,189 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include +#include + +_CLC_OVERLOAD _CLC_DEF float __spirv_ocl_atanpi(float x) { + const float pi = 3.1415926535897932f; + + uint ux = as_uint(x); + uint aux = ux & EXSIGNBIT_SP32; + uint sx = ux ^ aux; + + float xbypi = MATH_DIVIDE(x, pi); + float shalf = as_float(sx | as_uint(0.5f)); + + float v = as_float(aux); + + // Return for NaN + float ret = x; + + // 2^26 <= |x| <= Inf => atan(x) is close to piby2 + ret = aux <= PINFBITPATT_SP32 ? shalf : ret; + + // Reduce arguments 2^-19 <= |x| < 2^26 + + // 39/16 <= x < 2^26 + x = -MATH_RECIP(v); + float c = 1.57079632679489655800f; // atan(infinity) + + // 19/16 <= x < 39/16 + int l = aux < 0x401c0000; + float xx = MATH_DIVIDE(v - 1.5f, __spirv_ocl_mad(v, 1.5f, 1.0f)); + x = l ? xx : x; + c = l ? 9.82793723247329054082e-01f : c; // atan(1.5) + + // 11/16 <= x < 19/16 + l = aux < 0x3f980000U; + xx = MATH_DIVIDE(v - 1.0f, 1.0f + v); + x = l ? xx : x; + c = l ? 7.85398163397448278999e-01f : c; // atan(1) + + // 7/16 <= x < 11/16 + l = aux < 0x3f300000; + xx = MATH_DIVIDE(__spirv_ocl_mad(v, 2.0f, -1.0f), 2.0f + v); + x = l ? xx : x; + c = l ? 4.63647609000806093515e-01f : c; // atan(0.5) + + // 2^-19 <= x < 7/16 + l = aux < 0x3ee00000; + x = l ? v : x; + c = l ? 0.0f : c; + + // Core approximation: Remez(2,2) on [-7/16,7/16] + + float s = x * x; + float a = + __spirv_ocl_mad(s, + __spirv_ocl_mad(s, 0.470677934286149214138357545549e-2f, + 0.192324546402108583211697690500f), + 0.296528598819239217902158651186f); + + float b = + __spirv_ocl_mad(s, + __spirv_ocl_mad(s, 0.299309699959659728404442796915f, + 0.111072499995399550138837673349e1f), + 0.889585796862432286486651434570f); + + float q = x * s * MATH_DIVIDE(a, b); + + float z = c - (q - x); + z = MATH_DIVIDE(z, pi); + float zs = as_float(sx | as_uint(z)); + + ret = aux < 0x4c800000 ? zs : ret; + + // |x| < 2^-19 + ret = aux < 0x36000000 ? xbypi : ret; + return ret; +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, float, __spirv_ocl_atanpi, float) + +#ifdef cl_khr_fp64 +#pragma OPENCL EXTENSION cl_khr_fp64 : enable + +_CLC_OVERLOAD _CLC_DEF double __spirv_ocl_atanpi(double x) { + const double pi = 0x1.921fb54442d18p+1; + + double v = __spirv_ocl_fabs(x); + + // 2^56 > v > 39/16 + double a = -1.0; + double b = v; + // (chi + clo) = arctan(infinity) + double chi = 1.57079632679489655800e+00; + double clo = 6.12323399573676480327e-17; + + double ta = v - 1.5; + double tb = 1.0 + 1.5 * v; + int l = v <= 0x1.38p+1; // 39/16 > v > 19/16 + a = l ? ta : a; + b = l ? tb : b; + // (chi + clo) = arctan(1.5) + chi = l ? 9.82793723247329054082e-01 : chi; + clo = l ? 1.39033110312309953701e-17 : clo; + + ta = v - 1.0; + tb = 1.0 + v; + l = v <= 0x1.3p+0; // 19/16 > v > 11/16 + a = l ? ta : a; + b = l ? tb : b; + // (chi + clo) = arctan(1.) + chi = l ? 7.85398163397448278999e-01 : chi; + clo = l ? 3.06161699786838240164e-17 : clo; + + ta = 2.0 * v - 1.0; + tb = 2.0 + v; + l = v <= 0x1.6p-1; // 11/16 > v > 7/16 + a = l ? ta : a; + b = l ? tb : b; + // (chi + clo) = arctan(0.5) + chi = l ? 4.63647609000806093515e-01 : chi; + clo = l ? 2.26987774529616809294e-17 : clo; + + l = v <= 0x1.cp-2; // v < 7/16 + a = l ? v : a; + b = l ? 1.0 : b; + ; + chi = l ? 0.0 : chi; + clo = l ? 0.0 : clo; + + // Core approximation: Remez(4,4) on [-7/16,7/16] + double r = a / b; + double s = r * r; + double qn = __spirv_ocl_fma( + s, + __spirv_ocl_fma( + s, + __spirv_ocl_fma(s, + __spirv_ocl_fma(s, 0.142316903342317766e-3, + 0.304455919504853031e-1), + 0.220638780716667420e0), + 0.447677206805497472e0), + 0.268297920532545909e0); + + double qd = __spirv_ocl_fma( + s, + __spirv_ocl_fma( + s, + __spirv_ocl_fma(s, + __spirv_ocl_fma(s, 0.389525873944742195e-1, + 0.424602594203847109e0), + 0.141254259931958921e1), + 0.182596787737507063e1), + 0.804893761597637733e0); + + double q = r * s * qn / qd; + r = (chi - ((q - clo) - r)) / pi; + double vp = v / pi; + + double z = __spirv_IsNan(x) ? x : 0.5; + z = v <= 0x1.0p+56 ? r : z; + z = v < 0x1.0p-26 ? vp : z; + return x == v ? z : -z; +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, double, __spirv_ocl_atanpi, double) + +#endif + +#ifdef cl_khr_fp16 +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +_CLC_OVERLOAD _CLC_DEF half __spirv_ocl_atanpi(half x) { + float t = x; + return __spirv_ocl_atanpi(t); +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, half, __spirv_ocl_atanpi, half) + +#endif diff --git a/libclc/generic/libspirv/math/cbrt.cl b/libclc/generic/libspirv/math/cbrt.cl new file mode 100644 index 0000000000000..98bff27b9c979 --- /dev/null +++ b/libclc/generic/libspirv/math/cbrt.cl @@ -0,0 +1,146 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include "tables.h" +#include +#include + +_CLC_OVERLOAD _CLC_DEF float __spirv_ocl_cbrt(float x) { + + uint xi = as_uint(x); + uint axi = xi & EXSIGNBIT_SP32; + uint xsign = axi ^ xi; + xi = axi; + + int m = (xi >> EXPSHIFTBITS_SP32) - EXPBIAS_SP32; + + // Treat subnormals + uint xisub = as_uint(as_float(xi | 0x3f800000) - 1.0f); + int msub = (xisub >> EXPSHIFTBITS_SP32) - 253; + int c = m == -127; + xi = c ? xisub : xi; + m = c ? msub : m; + + int m3 = m / 3; + int rem = m - m3 * 3; + float mf = as_float((m3 + EXPBIAS_SP32) << EXPSHIFTBITS_SP32); + + uint indx = (xi & 0x007f0000) + ((xi & 0x00008000) << 1); + float f = + as_float((xi & MANTBITS_SP32) | 0x3f000000) - as_float(indx | 0x3f000000); + + indx >>= 16; + float r = f * USE_TABLE(log_inv_tbl, indx); + float poly = + __spirv_ocl_mad(__spirv_ocl_mad(r, 0x1.f9add4p-5f, -0x1.c71c72p-4f), + r * r, r * 0x1.555556p-2f); + + // This could also be done with a 5-element table + float remH = 0x1.428000p-1f; + float remT = 0x1.45f31ap-14f; + + remH = rem == -1 ? 0x1.964000p-1f : remH; + remT = rem == -1 ? 0x1.fea53ep-13f : remT; + + remH = rem == 0 ? 0x1.000000p+0f : remH; + remT = rem == 0 ? 0x0.000000p+0f : remT; + + remH = rem == 1 ? 0x1.428000p+0f : remH; + remT = rem == 1 ? 0x1.45f31ap-13f : remT; + + remH = rem == 2 ? 0x1.964000p+0f : remH; + remT = rem == 2 ? 0x1.fea53ep-12f : remT; + + float2 tv = USE_TABLE(cbrt_tbl, indx); + float cbrtH = tv.s0; + float cbrtT = tv.s1; + + float bH = cbrtH * remH; + float bT = + __spirv_ocl_mad(cbrtH, remT, __spirv_ocl_mad(cbrtT, remH, cbrtT * remT)); + + float z = __spirv_ocl_mad(poly, bH, __spirv_ocl_mad(poly, bT, bT)) + bH; + z *= mf; + z = as_float(as_uint(z) | xsign); + c = axi >= EXPBITS_SP32 | axi == 0; + z = c ? x : z; + return z; +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, float, __spirv_ocl_cbrt, float); + +#ifdef cl_khr_fp64 +#pragma OPENCL EXTENSION cl_khr_fp64 : enable + +_CLC_OVERLOAD _CLC_DEF double __spirv_ocl_cbrt(double x) { + + int return_x = __spirv_IsInf(x) | __spirv_IsNan(x) | x == 0.0; + ulong ux = as_ulong(__spirv_ocl_fabs(x)); + int m = (as_int2(ux).hi >> 20) - 1023; + + // Treat subnormals + ulong uxs = as_ulong(as_double(0x3ff0000000000000UL | ux) - 1.0); + int ms = m + (as_int2(uxs).hi >> 20) - 1022; + + int c = m == -1023; + ux = c ? uxs : ux; + m = c ? ms : m; + + int mby3 = m / 3; + int rem = m - 3 * mby3; + + double mf = as_double((ulong)(mby3 + 1023) << 52); + + ux &= 0x000fffffffffffffUL; + double Y = as_double(0x3fe0000000000000UL | ux); + + // nearest integer + int index = as_int2(ux).hi >> 11; + index = (0x100 | (index >> 1)) + (index & 1); + double F = (double)index * 0x1.0p-9; + + double f = Y - F; + double r = f * USE_TABLE(cbrt_inv_tbl, index - 256); + + double z = + r * __spirv_ocl_fma( + r, + __spirv_ocl_fma( + r, + __spirv_ocl_fma( + r, + __spirv_ocl_fma(r, + __spirv_ocl_fma(r, -0x1.8090d6221a247p-6, + 0x1.ee7113506ac13p-6), + -0x1.511e8d2b3183bp-5), + 0x1.f9add3c0ca458p-5), + -0x1.c71c71c71c71cp-4), + 0x1.5555555555555p-2); + + double2 tv = USE_TABLE(cbrt_rem_tbl, rem + 2); + double Rem_h = tv.s0; + double Rem_t = tv.s1; + + tv = USE_TABLE(cbrt_dbl_tbl, index - 256); + double F_h = tv.s0; + double F_t = tv.s1; + + double b_h = F_h * Rem_h; + double b_t = + __spirv_ocl_fma(Rem_t, F_h, __spirv_ocl_fma(F_t, Rem_h, F_t * Rem_t)); + + double ans = __spirv_ocl_fma(z, b_h, __spirv_ocl_fma(z, b_t, b_t)) + b_h; + ans = __spirv_ocl_copysign(ans * mf, x); + return return_x ? x : ans; +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, double, __spirv_ocl_cbrt, double) + +#endif diff --git a/libclc/generic/libspirv/math/ceil.cl b/libclc/generic/libspirv/math/ceil.cl index 16db46989e8de..f94b6c2050be0 100644 --- a/libclc/generic/libspirv/math/ceil.cl +++ b/libclc/generic/libspirv/math/ceil.cl @@ -6,14 +6,14 @@ // //===----------------------------------------------------------------------===// +#include #include -#include "../../lib/clcmacro.h" // Map the llvm intrinsic to an OpenCL function. #define __CLC_FUNCTION __clc___spirv_ocl_ceil #define __CLC_INTRINSIC "llvm.ceil" -#include "math/unary_intrin.inc" +#include #undef __CLC_FUNCTION #define __CLC_FUNCTION __spirv_ocl_ceil -#include "unary_builtin.inc" +#include diff --git a/libclc/generic/libspirv/math/clc_exp10.cl b/libclc/generic/libspirv/math/clc_exp10.cl index 9bf2d4f3f1b46..d5b9621aa9888 100644 --- a/libclc/generic/libspirv/math/clc_exp10.cl +++ b/libclc/generic/libspirv/math/clc_exp10.cl @@ -22,10 +22,10 @@ #include -#include "config.h" #include "tables.h" -#include "../../lib/math/math.h" -#include "../../lib/clcmacro.h" +#include +#include +#include // Algorithm: // diff --git a/libclc/generic/libspirv/math/clc_fma.cl b/libclc/generic/libspirv/math/clc_fma.cl index 074ed7bad43c9..cc7605922e136 100644 --- a/libclc/generic/libspirv/math/clc_fma.cl +++ b/libclc/generic/libspirv/math/clc_fma.cl @@ -23,9 +23,9 @@ #include #include -#include "../../lib/clcmacro.h" -#include "../../lib/math/math.h" -#include "config.h" +#include +#include +#include struct fp { ulong mantissa; diff --git a/libclc/generic/libspirv/math/clc_fmod.cl b/libclc/generic/libspirv/math/clc_fmod.cl new file mode 100644 index 0000000000000..f84c1155b49c3 --- /dev/null +++ b/libclc/generic/libspirv/math/clc_fmod.cl @@ -0,0 +1,168 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include +#include +#include +#include + +_CLC_DEF _CLC_OVERLOAD float __clc_fmod(float x, float y) { + int ux = as_int(x); + int ax = ux & EXSIGNBIT_SP32; + float xa = as_float(ax); + int sx = ux ^ ax; + int ex = ax >> EXPSHIFTBITS_SP32; + + int uy = as_int(y); + int ay = uy & EXSIGNBIT_SP32; + float ya = as_float(ay); + int ey = ay >> EXPSHIFTBITS_SP32; + + float xr = as_float(0x3f800000 | (ax & 0x007fffff)); + float yr = as_float(0x3f800000 | (ay & 0x007fffff)); + int c; + int k = ex - ey; + + while (k > 0) { + c = xr >= yr; + xr -= c ? yr : 0.0f; + xr += xr; + --k; + } + + c = xr >= yr; + xr -= c ? yr : 0.0f; + + int lt = ex < ey; + + xr = lt ? xa : xr; + yr = lt ? ya : yr; + + float s = as_float(ey << EXPSHIFTBITS_SP32); + xr *= lt ? 1.0f : s; + + c = ax == ay; + xr = c ? 0.0f : xr; + + xr = as_float(sx ^ as_int(xr)); + + c = ax > PINFBITPATT_SP32 | ay > PINFBITPATT_SP32 | ax == PINFBITPATT_SP32 | + ay == 0; + xr = c ? as_float(QNANBITPATT_SP32) : xr; + + return xr; +} +_CLC_BINARY_VECTORIZE(_CLC_DEF _CLC_OVERLOAD, float, __clc_fmod, float, float); + +#ifdef cl_khr_fp64 +_CLC_DEF _CLC_OVERLOAD double __clc_fmod(double x, double y) { + ulong ux = as_ulong(x); + ulong ax = ux & ~SIGNBIT_DP64; + ulong xsgn = ux ^ ax; + double dx = as_double(ax); + int xexp = __spirv_SatConvertUToS_Rint(ax >> EXPSHIFTBITS_DP64); + int xexp1 = 11 - (int)__spirv_ocl_clz(ax & MANTBITS_DP64); + xexp1 = xexp < 1 ? xexp1 : xexp; + + ulong uy = as_ulong(y); + ulong ay = uy & ~SIGNBIT_DP64; + double dy = as_double(ay); + int yexp = __spirv_SatConvertUToS_Rint(ay >> EXPSHIFTBITS_DP64); + int yexp1 = 11 - (int)__spirv_ocl_clz(ay & MANTBITS_DP64); + yexp1 = yexp < 1 ? yexp1 : yexp; + + // First assume |x| > |y| + + // Set ntimes to the number of times we need to do a + // partial remainder. If the exponent of x is an exact multiple + // of 53 larger than the exponent of y, and the mantissa of x is + // less than the mantissa of y, ntimes will be one too large + // but it doesn't matter - it just means that we'll go round + // the loop below one extra time. + int ntimes = __spirv_ocl_s_max(0, (xexp1 - yexp1) / 53); + double w = __spirv_ocl_ldexp(dy, ntimes * 53); + w = ntimes == 0 ? dy : w; + double scale = ntimes == 0 ? 1.0 : 0x1.0p-53; + + // Each time round the loop we compute a partial remainder. + // This is done by subtracting a large multiple of w + // from x each time, where w is a scaled up version of y. + // The subtraction must be performed exactly in quad + // precision, though the result at each stage can + // fit exactly in a double precision number. + int i; + double t, v, p, pp; + + for (i = 0; i < ntimes; i++) { + // Compute integral multiplier + t = __spirv_ocl_trunc(dx / w); + + // Compute w * t in quad precision + p = w * t; + pp = __spirv_ocl_fma(w, t, -p); + + // Subtract w * t from dx + v = dx - p; + dx = v + (((dx - v) - p) - pp); + + // If t was one too large, dx will be negative. Add back one w. + dx += dx < 0.0 ? w : 0.0; + + // Scale w down by 2^(-53) for the next iteration + w *= scale; + } + + // One more time + // Variable todd says whether the integer t is odd or not + t = __spirv_ocl_floor(dx / w); + long lt = (long)t; + int todd = lt & 1; + + p = w * t; + pp = __spirv_ocl_fma(w, t, -p); + v = dx - p; + dx = v + (((dx - v) - p) - pp); + i = dx < 0.0; + todd ^= i; + dx += i ? w : 0.0; + + // At this point, dx lies in the range [0,dy) + double ret = as_double(xsgn ^ as_ulong(dx)); + dx = as_double(ax); + + // Now handle |x| == |y| + int c = dx == dy; + t = as_double(xsgn); + ret = c ? t : ret; + + // Next, handle |x| < |y| + c = dx < dy; + ret = c ? x : ret; + + // We don't need anything special for |x| == 0 + + // |y| is 0 + c = dy == 0.0; + ret = c ? as_double(QNANBITPATT_DP64) : ret; + + // y is +-Inf, NaN + c = yexp > BIASEDEMAX_DP64; + t = y == y ? x : y; + ret = c ? t : ret; + + // x is +=Inf, NaN + c = xexp > BIASEDEMAX_DP64; + ret = c ? as_double(QNANBITPATT_DP64) : ret; + + return ret; +} +_CLC_BINARY_VECTORIZE(_CLC_DEF _CLC_OVERLOAD, double, __clc_fmod, double, + double); +#endif diff --git a/libclc/generic/lib/math/clc_hypot.cl b/libclc/generic/libspirv/math/clc_hypot.cl similarity index 54% rename from libclc/generic/lib/math/clc_hypot.cl rename to libclc/generic/libspirv/math/clc_hypot.cl index 35532a9532062..d99fceccf77c7 100644 --- a/libclc/generic/lib/math/clc_hypot.cl +++ b/libclc/generic/libspirv/math/clc_hypot.cl @@ -1,31 +1,17 @@ -/* - * Copyright (c) 2014 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include +#include #include - -#include "config.h" -#include "math.h" -#include "../clcmacro.h" +#include // Returns sqrt(x*x + y*y) with no overflow or underflow unless the result warrants it _CLC_DEF _CLC_OVERLOAD float __clc_hypot(float x, float y) @@ -39,15 +25,18 @@ _CLC_DEF _CLC_OVERLOAD float __clc_hypot(float x, float y) ux = c ? aux : auy; uy = c ? auy : aux; - int xexp = clamp((int)(ux >> EXPSHIFTBITS_SP32) - EXPBIAS_SP32, -126, 126); + int xexp = __spirv_ocl_s_clamp( + (int)(ux >> EXPSHIFTBITS_SP32) - EXPBIAS_SP32, -126, 126); float fx_exp = as_float((xexp + EXPBIAS_SP32) << EXPSHIFTBITS_SP32); float fi_exp = as_float((-xexp + EXPBIAS_SP32) << EXPSHIFTBITS_SP32); float fx = as_float(ux) * fi_exp; float fy = as_float(uy) * fi_exp; - retval = sqrt(mad(fx, fx, fy*fy)) * fx_exp; + retval = __spirv_ocl_sqrt(__spirv_ocl_mad(fx, fx, fy * fy)) * fx_exp; - retval = ux > PINFBITPATT_SP32 | uy == 0 ? as_float(ux) : retval; - retval = ux == PINFBITPATT_SP32 | uy == PINFBITPATT_SP32 ? as_float(PINFBITPATT_SP32) : retval; + retval = ux > PINFBITPATT_SP32 || uy == 0 ? as_float(ux) : retval; + retval = ux == PINFBITPATT_SP32 || uy == PINFBITPATT_SP32 + ? as_float(PINFBITPATT_SP32) + : retval; return retval; } _CLC_BINARY_VECTORIZE(_CLC_DEF _CLC_OVERLOAD, float, __clc_hypot, float, float) @@ -75,16 +64,16 @@ _CLC_DEF _CLC_OVERLOAD double __clc_hypot(double x, double y) double ay = y * preadjust; // The post adjust may overflow, but this can't be avoided in any case - double r = sqrt(fma(ax, ax, ay*ay)) * postadjust; + double r = __spirv_ocl_sqrt(__spirv_ocl_fma(ax, ax, ay * ay)) * postadjust; // If the difference in exponents between x and y is large double s = x + y; - c = abs(xexp - yexp) > MANTLENGTH_DP64 + 1; + c = __spirv_ocl_s_abs(xexp - yexp) > MANTLENGTH_DP64 + 1; r = c ? s : r; // Check for NaN //c = x != x | y != y; - c = isnan(x) | isnan(y); + c = __spirv_IsNan(x) | __spirv_IsNan(y); r = c ? as_double(QNANBITPATT_DP64) : r; // If either is Inf, we must return Inf diff --git a/libclc/generic/libspirv/math/clc_ldexp.cl b/libclc/generic/libspirv/math/clc_ldexp.cl index ae438b951c27f..be582b88445cb 100644 --- a/libclc/generic/libspirv/math/clc_ldexp.cl +++ b/libclc/generic/libspirv/math/clc_ldexp.cl @@ -23,10 +23,10 @@ #include #include -#include "../../lib/clcmacro.h" -#include "../../lib/math/math.h" -#include "config.h" #include "tables.h" +#include +#include +#include _CLC_DEF _CLC_OVERLOAD float __clc_ldexp(float x, int n) { @@ -39,7 +39,7 @@ _CLC_DEF _CLC_OVERLOAD float __clc_ldexp(float x, int n) { int s = i & 0x80000000; int v = __clc_add_sat(e, n); v = __clc_clamp(v, 0, 0xff); - int mr = e == 0 | v == 0 | v == 0xff ? 0 : m; + int mr = e == 0 || v == 0 || v == 0xff ? 0 : m; int c = e == 0xff; mr = c ? m : mr; int er = c ? e : v; @@ -92,7 +92,7 @@ _CLC_DEF _CLC_OVERLOAD float __clc_ldexp(float x, int n) { val_ui = dexp == 0 ? dval_ui : val_ui; val_f = as_float(val_ui); - val_f = __spirv_IsNan(x) | __spirv_IsInf(x) | val_x == 0 ? x : val_f; + val_f = __spirv_IsNan(x) || __spirv_IsInf(x) || val_x == 0 ? x : val_f; return val_f; } diff --git a/libclc/generic/libspirv/math/clc_nextafter.cl b/libclc/generic/libspirv/math/clc_nextafter.cl new file mode 100644 index 0000000000000..f2d4fb83004b4 --- /dev/null +++ b/libclc/generic/libspirv/math/clc_nextafter.cl @@ -0,0 +1,56 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include +#include + +// This file provides OpenCL C implementations of nextafter for +// targets that don't support the clang builtin. + +#define AS_TYPE(x) as_##x + +#define NEXTAFTER(FLOAT_TYPE, UINT_TYPE, INT_TYPE) \ + _CLC_OVERLOAD _CLC_DEF FLOAT_TYPE __clc_nextafter(FLOAT_TYPE x, \ + FLOAT_TYPE y) { \ + const UINT_TYPE sign_bit = (UINT_TYPE)1 << (sizeof(INT_TYPE) * 8 - 1); \ + const UINT_TYPE sign_bit_mask = sign_bit - 1; \ + INT_TYPE ix = AS_TYPE(INT_TYPE)(x); \ + INT_TYPE ax = ix & sign_bit_mask; \ + INT_TYPE mx = sign_bit - ix; \ + mx = ix < 0 ? mx : ix; \ + INT_TYPE iy = AS_TYPE(INT_TYPE)(y); \ + INT_TYPE ay = iy & sign_bit_mask; \ + INT_TYPE my = sign_bit - iy; \ + my = iy < 0 ? my : iy; \ + INT_TYPE t = mx + (mx < my ? 1 : -1); \ + INT_TYPE r = sign_bit - t; \ + r = t < 0 ? r : t; \ + r = __spirv_IsNan(x) ? ix : r; \ + r = __spirv_IsNan(y) ? iy : r; \ + r = ((ax | ay) == 0 | ix == iy) ? iy : r; \ + return AS_TYPE(FLOAT_TYPE)(r); \ + } + +NEXTAFTER(float, uint, int) +_CLC_BINARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, float, __clc_nextafter, float, + float) + +#ifdef cl_khr_fp64 +#pragma OPENCL EXTENSION cl_khr_fp64 : enable + +NEXTAFTER(double, ulong, long) +_CLC_BINARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, double, __clc_nextafter, double, + double) +#endif + +#ifdef cl_khr_fp16 +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +NEXTAFTER(half, ushort, short) +_CLC_BINARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, half, __clc_nextafter, half, half) +#endif diff --git a/libclc/generic/libspirv/math/clc_pow.cl b/libclc/generic/libspirv/math/clc_pow.cl index fd86e948012a6..c21fe6cc618d0 100644 --- a/libclc/generic/libspirv/math/clc_pow.cl +++ b/libclc/generic/libspirv/math/clc_pow.cl @@ -22,10 +22,10 @@ #include -#include "config.h" #include "tables.h" -#include "../../lib/math/math.h" -#include "../../lib/clcmacro.h" +#include +#include +#include /* compute pow using log and exp @@ -199,10 +199,10 @@ _CLC_DEF _CLC_OVERLOAD float __clc_pow(float x, float y) /* Corner case handling */ ret = (!xpos & (inty == 0)) ? QNANBITPATT_SP32 : ret; - ret = ax < 0x3f800000 & iy == NINFBITPATT_SP32 ? PINFBITPATT_SP32 : ret; - ret = ax > 0x3f800000 & iy == NINFBITPATT_SP32 ? 0 : ret; - ret = ax < 0x3f800000 & iy == PINFBITPATT_SP32 ? 0 : ret; - ret = ax > 0x3f800000 & iy == PINFBITPATT_SP32 ? PINFBITPATT_SP32 : ret; + ret = ax < 0x3f800000 && iy == NINFBITPATT_SP32 ? PINFBITPATT_SP32 : ret; + ret = ax > 0x3f800000 && iy == NINFBITPATT_SP32 ? 0 : ret; + ret = ax < 0x3f800000 && iy == PINFBITPATT_SP32 ? 0 : ret; + ret = ax > 0x3f800000 && iy == PINFBITPATT_SP32 ? PINFBITPATT_SP32 : ret; int xinf = xpos ? PINFBITPATT_SP32 : NINFBITPATT_SP32; ret = ((ax == 0) & !ypos & (inty == 1)) ? xinf : ret; ret = ((ax == 0) & !ypos & (inty != 1)) ? PINFBITPATT_SP32 : ret; @@ -360,19 +360,21 @@ _CLC_DEF _CLC_OVERLOAD double __clc_pow(double x, double y) long mask = (1L << (53 - yexp)) - 1L; int inty1 = (((ay & ~mask) >> (53 - yexp)) & 1L) == 1L ? 1 : 2; inty1 = (ay & mask) != 0 ? 0 : inty1; - inty = !(yexp < 1) & !(yexp > 53) ? inty1 : inty; + inty = !(yexp < 1) && !(yexp > 53) ? inty1 : inty; } - expv *= (inty == 1) & !xpos ? -1.0 : 1.0; + expv *= (inty == 1) && !xpos ? -1.0 : 1.0; long ret = as_long(expv); // Now all the edge cases - ret = !xpos & (inty == 0) ? QNANBITPATT_DP64 : ret; - ret = ax < 0x3ff0000000000000L & uy == NINFBITPATT_DP64 ? PINFBITPATT_DP64 : ret; - ret = ax > 0x3ff0000000000000L & uy == NINFBITPATT_DP64 ? 0L : ret; - ret = ax < 0x3ff0000000000000L & uy == PINFBITPATT_DP64 ? 0L : ret; - ret = ax > 0x3ff0000000000000L & uy == PINFBITPATT_DP64 ? PINFBITPATT_DP64 : ret; + ret = !xpos && (inty == 0) ? QNANBITPATT_DP64 : ret; + ret = ax < 0x3ff0000000000000L && uy == NINFBITPATT_DP64 ? PINFBITPATT_DP64 + : ret; + ret = ax > 0x3ff0000000000000L && uy == NINFBITPATT_DP64 ? 0L : ret; + ret = ax < 0x3ff0000000000000L && uy == PINFBITPATT_DP64 ? 0L : ret; + ret = ax > 0x3ff0000000000000L && uy == PINFBITPATT_DP64 ? PINFBITPATT_DP64 + : ret; long xinf = xpos ? PINFBITPATT_DP64 : NINFBITPATT_DP64; ret = ((ax == 0L) & !ypos & (inty == 1)) ? xinf : ret; ret = ((ax == 0L) & !ypos & (inty != 1)) ? PINFBITPATT_DP64 : ret; @@ -385,7 +387,7 @@ _CLC_DEF _CLC_OVERLOAD double __clc_pow(double x, double y) ret = ((ux == NINFBITPATT_DP64) & !ypos & (inty != 1)) ? 0L : ret; ret = ((ux == NINFBITPATT_DP64) & ypos & (inty == 1)) ? NINFBITPATT_DP64 : ret; ret = ((ux == NINFBITPATT_DP64) & ypos & (inty != 1)) ? PINFBITPATT_DP64 : ret; - ret = (ux == PINFBITPATT_DP64) & !ypos ? 0L : ret; + ret = (ux == PINFBITPATT_DP64) && !ypos ? 0L : ret; ret = (ux == PINFBITPATT_DP64) & ypos ? PINFBITPATT_DP64 : ret; ret = ax > PINFBITPATT_DP64 ? ux : ret; ret = ay > PINFBITPATT_DP64 ? uy : ret; @@ -396,3 +398,13 @@ _CLC_DEF _CLC_OVERLOAD double __clc_pow(double x, double y) } _CLC_BINARY_VECTORIZE(_CLC_DEF _CLC_OVERLOAD, double, __clc_pow, double, double) #endif + +#ifdef cl_khr_fp16 +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +_CLC_DEF _CLC_OVERLOAD half __clc_pow(half x, half y) { + return __clc_pow((float)x, (float)y); +} + +_CLC_BINARY_VECTORIZE(_CLC_DEF _CLC_OVERLOAD, half, __clc_pow, half, half) +#endif diff --git a/libclc/generic/libspirv/math/clc_pown.cl b/libclc/generic/libspirv/math/clc_pown.cl new file mode 100644 index 0000000000000..b5b88a3e8a7ac --- /dev/null +++ b/libclc/generic/libspirv/math/clc_pown.cl @@ -0,0 +1,390 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include "tables.h" +#include +#include +#include + +// compute pow using log and exp +// x^y = exp(y * log(x)) +// +// we take care not to lose precision in the intermediate steps +// +// When computing log, calculate it in splits, +// +// r = f * (p_invead + p_inv_tail) +// r = rh + rt +// +// calculate log polynomial using r, in end addition, do +// poly = poly + ((rh-r) + rt) +// +// lth = -r +// ltt = ((xexp * log2_t) - poly) + logT +// lt = lth + ltt +// +// lh = (xexp * log2_h) + logH +// l = lh + lt +// +// Calculate final log answer as gh and gt, +// gh = l & higher-half bits +// gt = (((ltt - (lt - lth)) + ((lh - l) + lt)) + (l - gh)) +// +// yh = y & higher-half bits +// yt = y - yh +// +// Before entering computation of exp, +// vs = ((yt*gt + yt*gh) + yh*gt) +// v = vs + yh*gh +// vt = ((yh*gh - v) + vs) +// +// In calculation of exp, add vt to r that is used for poly +// At the end of exp, do +// ((((expT * poly) + expT) + expH*poly) + expH) + +_CLC_DEF _CLC_OVERLOAD float __clc_pown(float x, int ny) { + float y = (float)ny; + + int ix = as_int(x); + int ax = ix & EXSIGNBIT_SP32; + int xpos = ix == ax; + + int iy = as_int(y); + int ay = iy & EXSIGNBIT_SP32; + int ypos = iy == ay; + + // Extra precise log calculation + // First handle case that x is close to 1 + float r = 1.0f - as_float(ax); + int near1 = __spirv_ocl_fabs(r) < 0x1.0p-4f; + float r2 = r * r; + + // Coefficients are just 1/3, 1/4, 1/5 and 1/6 + float poly = __spirv_ocl_mad( + r, + __spirv_ocl_mad( + r, + __spirv_ocl_mad(r, __spirv_ocl_mad(r, 0x1.24924ap-3f, 0x1.555556p-3f), + 0x1.99999ap-3f), + 0x1.000000p-2f), + 0x1.555556p-2f); + + poly *= r2 * r; + + float lth_near1 = -r2 * 0.5f; + float ltt_near1 = -poly; + float lt_near1 = lth_near1 + ltt_near1; + float lh_near1 = -r; + float l_near1 = lh_near1 + lt_near1; + + // Computations for x not near 1 + int m = (int)(ax >> EXPSHIFTBITS_SP32) - EXPBIAS_SP32; + float mf = (float)m; + int ixs = as_int(as_float(ax | 0x3f800000) - 1.0f); + float mfs = (float)((ixs >> EXPSHIFTBITS_SP32) - 253); + int c = m == -127; + int ixn = c ? ixs : ax; + float mfn = c ? mfs : mf; + + int indx = (ixn & 0x007f0000) + ((ixn & 0x00008000) << 1); + + // F - Y + float f = as_float(0x3f000000 | indx) - + as_float(0x3f000000 | (ixn & MANTBITS_SP32)); + + indx = indx >> 16; + float2 tv = USE_TABLE(log_inv_tbl_ep, indx); + float rh = f * tv.s0; + float rt = f * tv.s1; + r = rh + rt; + + poly = __spirv_ocl_mad(r, __spirv_ocl_mad(r, 0x1.0p-2f, 0x1.555556p-2f), + 0x1.0p-1f) * + (r * r); + poly += (rh - r) + rt; + + const float LOG2_HEAD = 0x1.62e000p-1f; // 0.693115234 + const float LOG2_TAIL = 0x1.0bfbe8p-15f; // 0.0000319461833 + tv = USE_TABLE(loge_tbl, indx); + float lth = -r; + float ltt = __spirv_ocl_mad(mfn, LOG2_TAIL, -poly) + tv.s1; + float lt = lth + ltt; + float lh = __spirv_ocl_mad(mfn, LOG2_HEAD, tv.s0); + float l = lh + lt; + + // Select near 1 or not + lth = near1 ? lth_near1 : lth; + ltt = near1 ? ltt_near1 : ltt; + lt = near1 ? lt_near1 : lt; + lh = near1 ? lh_near1 : lh; + l = near1 ? l_near1 : l; + + float gh = as_float(as_int(l) & 0xfffff000); + float gt = ((ltt - (lt - lth)) + ((lh - l) + lt)) + (l - gh); + + float yh = as_float(iy & 0xfffff000); + + float yt = (float)(ny - (int)yh); + + float ylogx_s = __spirv_ocl_mad(gt, yh, __spirv_ocl_mad(gh, yt, yt * gt)); + float ylogx = __spirv_ocl_mad(yh, gh, ylogx_s); + float ylogx_t = __spirv_ocl_mad(yh, gh, -ylogx) + ylogx_s; + + // Extra precise exp of ylogx + const float R_64_BY_LOG2 = 0x1.715476p+6f; // 64/log2 : 92.332482616893657 + int n = __spirv_ConvertFToS_Rint(ylogx * R_64_BY_LOG2); + float nf = (float)n; + + int j = n & 0x3f; + m = n >> 6; + int m2 = m << EXPSHIFTBITS_SP32; + + const float R_LOG2_BY_64_LD = 0x1.620000p-7f; // log2/64 lead: 0.0108032227 + const float R_LOG2_BY_64_TL = + 0x1.c85fdep-16f; // log2/64 tail: 0.0000272020388 + r = __spirv_ocl_mad(nf, -R_LOG2_BY_64_TL, + __spirv_ocl_mad(nf, -R_LOG2_BY_64_LD, ylogx)) + + ylogx_t; + + // Truncated Taylor series for e^r + poly = __spirv_ocl_mad( + __spirv_ocl_mad(__spirv_ocl_mad(r, 0x1.555556p-5f, 0x1.555556p-3f), r, + 0x1.000000p-1f), + r * r, r); + + tv = USE_TABLE(exp_tbl_ep, j); + + float expylogx = + __spirv_ocl_mad(tv.s0, poly, __spirv_ocl_mad(tv.s1, poly, tv.s1)) + tv.s0; + float sexpylogx = expylogx * as_float(0x1 << (m + 149)); + float texpylogx = as_float(as_int(expylogx) + m2); + expylogx = m < -125 ? sexpylogx : texpylogx; + + // Result is +-Inf if (ylogx + ylogx_t) > 128*log2 + expylogx = ((ylogx > 0x1.62e430p+6f) | + (ylogx == 0x1.62e430p+6f & ylogx_t > -0x1.05c610p-22f)) + ? as_float(PINFBITPATT_SP32) + : expylogx; + + // Result is 0 if ylogx < -149*log2 + expylogx = ylogx < -0x1.9d1da0p+6f ? 0.0f : expylogx; + + // Classify y: + // inty = 0 means not an integer. + // inty = 1 means odd integer. + // inty = 2 means even integer. + + int inty = 2 - (ny & 1); + + float signval = as_float((as_uint(expylogx) ^ SIGNBIT_SP32)); + expylogx = ((inty == 1) & !xpos) ? signval : expylogx; + int ret = as_int(expylogx); + + // Corner case handling + int xinf = xpos ? PINFBITPATT_SP32 : NINFBITPATT_SP32; + ret = ((ax == 0) & !ypos & (inty == 1)) ? xinf : ret; + ret = ((ax == 0) & !ypos & (inty == 2)) ? PINFBITPATT_SP32 : ret; + ret = ((ax == 0) & ypos & (inty == 2)) ? 0 : ret; + int xzero = !xpos ? 0x80000000 : 0L; + ret = ((ax == 0) & ypos & (inty == 1)) ? xzero : ret; + ret = ((ix == NINFBITPATT_SP32) & !ypos & (inty == 1)) ? 0x80000000 : ret; + ret = ((ix == NINFBITPATT_SP32) & !ypos & (inty != 1)) ? 0 : ret; + ret = + ((ix == NINFBITPATT_SP32) & ypos & (inty == 1)) ? NINFBITPATT_SP32 : ret; + ret = + ((ix == NINFBITPATT_SP32) & ypos & (inty != 1)) ? PINFBITPATT_SP32 : ret; + ret = ((ix == PINFBITPATT_SP32) & !ypos) ? 0 : ret; + ret = ((ix == PINFBITPATT_SP32) & ypos) ? PINFBITPATT_SP32 : ret; + ret = ax > PINFBITPATT_SP32 ? ix : ret; + ret = ny == 0 ? 0x3f800000 : ret; + + return as_float(ret); +} +_CLC_BINARY_VECTORIZE(_CLC_DEF _CLC_OVERLOAD, float, __clc_pown, float, int) + +#ifdef cl_khr_fp64 +_CLC_DEF _CLC_OVERLOAD double __clc_pown(double x, int ny) { + const double real_log2_tail = 5.76999904754328540596e-08; + const double real_log2_lead = 6.93147122859954833984e-01; + + double y = (double)ny; + + long ux = as_long(x); + long ax = ux & (~SIGNBIT_DP64); + int xpos = ax == ux; + + long uy = as_long(y); + long ay = uy & (~SIGNBIT_DP64); + int ypos = ay == uy; + + // Extended precision log + double v, vt; + { + int exp = (int)(ax >> 52) - 1023; + int mask_exp_1023 = exp == -1023; + double xexp = (double)exp; + long mantissa = ax & 0x000FFFFFFFFFFFFFL; + + long temp_ux = as_long(as_double(0x3ff0000000000000L | mantissa) - 1.0); + exp = ((temp_ux & 0x7FF0000000000000L) >> 52) - 2045; + double xexp1 = (double)exp; + long mantissa1 = temp_ux & 0x000FFFFFFFFFFFFFL; + + xexp = mask_exp_1023 ? xexp1 : xexp; + mantissa = mask_exp_1023 ? mantissa1 : mantissa; + + long rax = (mantissa & 0x000ff00000000000) + + ((mantissa & 0x0000080000000000) << 1); + int index = rax >> 44; + + double F = as_double(rax | 0x3FE0000000000000L); + double Y = as_double(mantissa | 0x3FE0000000000000L); + double f = F - Y; + double2 tv = USE_TABLE(log_f_inv_tbl, index); + double log_h = tv.s0; + double log_t = tv.s1; + double f_inv = (log_h + log_t) * f; + double r1 = as_double(as_long(f_inv) & 0xfffffffff8000000L); + double r2 = __spirv_ocl_fma(-F, r1, f) * (log_h + log_t); + double r = r1 + r2; + + double poly = __spirv_ocl_fma( + r, + __spirv_ocl_fma( + r, + __spirv_ocl_fma(r, __spirv_ocl_fma(r, 1.0 / 7.0, 1.0 / 6.0), + 1.0 / 5.0), + 1.0 / 4.0), + 1.0 / 3.0); + poly = poly * r * r * r; + + double hr1r1 = 0.5 * r1 * r1; + double poly0h = r1 + hr1r1; + double poly0t = r1 - poly0h + hr1r1; + poly = __spirv_ocl_fma(r1, r2, __spirv_ocl_fma(0.5 * r2, r2, poly)) + r2 + + poly0t; + + tv = USE_TABLE(powlog_tbl, index); + log_h = tv.s0; + log_t = tv.s1; + + double resT_t = __spirv_ocl_fma(xexp, real_log2_tail, +log_t) - poly; + double resT = resT_t - poly0h; + double resH = __spirv_ocl_fma(xexp, real_log2_lead, log_h); + double resT_h = poly0h; + + double H = resT + resH; + double H_h = as_double(as_long(H) & 0xfffffffff8000000L); + double T = (resH - H + resT) + (resT_t - (resT + resT_h)) + (H - H_h); + H = H_h; + + double y_head = as_double(uy & 0xfffffffff8000000L); + double y_tail = y - y_head; + + int mask_2_24 = ay > 0x4170000000000000; // 2^24 + int nyh = __spirv_ConvertFToS_Rint(y_head); + int nyt = ny - nyh; + double y_tail1 = (double)nyt; + y_tail = mask_2_24 ? y_tail1 : y_tail; + + double temp = + __spirv_ocl_fma(y_tail, H, __spirv_ocl_fma(y_head, T, y_tail * T)); + v = __spirv_ocl_fma(y_head, H, temp); + vt = __spirv_ocl_fma(y_head, H, -v) + temp; + } + + // Now calculate exp of (v,vt) + + double expv; + { + const double max_exp_arg = 709.782712893384; + const double min_exp_arg = -745.1332191019411; + const double sixtyfour_by_lnof2 = 92.33248261689366; + const double lnof2_by_64_head = 0.010830424260348081; + const double lnof2_by_64_tail = -4.359010638708991e-10; + + double temp = v * sixtyfour_by_lnof2; + int n = (int)temp; + double dn = (double)n; + int j = n & 0x0000003f; + int m = n >> 6; + + double2 tv = USE_TABLE(two_to_jby64_ep_tbl, j); + double f1 = tv.s0; + double f2 = tv.s1; + double f = f1 + f2; + + double r1 = __spirv_ocl_fma(dn, -lnof2_by_64_head, v); + double r2 = dn * lnof2_by_64_tail; + double r = (r1 + r2) + vt; + + double q = __spirv_ocl_fma( + r, + __spirv_ocl_fma( + r, + __spirv_ocl_fma(r, + __spirv_ocl_fma(r, 1.38889490863777199667e-03, + 8.33336798434219616221e-03), + 4.16666666662260795726e-02), + 1.66666666665260878863e-01), + 5.00000000000000008883e-01); + q = __spirv_ocl_fma(r * r, q, r); + + expv = __spirv_ocl_fma(f, q, f2) + f1; + expv = __spirv_ocl_ldexp(expv, m); + + expv = v > max_exp_arg ? as_double(0x7FF0000000000000L) : expv; + expv = v < min_exp_arg ? 0.0 : expv; + } + + // See whether y is an integer. + // inty = 0 means not an integer. + // inty = 1 means odd integer. + // inty = 2 means even integer. + + int inty = 2 - (ny & 1); + + expv *= ((inty == 1) & !xpos) ? -1.0 : 1.0; + + long ret = as_long(expv); + + // Now all the edge cases + long xinf = xpos ? PINFBITPATT_DP64 : NINFBITPATT_DP64; + ret = ((ax == 0L) & !ypos & (inty == 1)) ? xinf : ret; + ret = ((ax == 0L) & !ypos & (inty == 2)) ? PINFBITPATT_DP64 : ret; + ret = ((ax == 0L) & ypos & (inty == 2)) ? 0L : ret; + long xzero = !xpos ? 0x8000000000000000L : 0L; + ret = ((ax == 0L) & ypos & (inty == 1)) ? xzero : ret; + ret = ((ux == NINFBITPATT_DP64) & !ypos & (inty == 1)) ? 0x8000000000000000L + : ret; + ret = ((ux == NINFBITPATT_DP64) & !ypos & (inty != 1)) ? 0L : ret; + ret = + ((ux == NINFBITPATT_DP64) & ypos & (inty == 1)) ? NINFBITPATT_DP64 : ret; + ret = + ((ux == NINFBITPATT_DP64) & ypos & (inty != 1)) ? PINFBITPATT_DP64 : ret; + ret = ((ux == PINFBITPATT_DP64) & !ypos) ? 0L : ret; + ret = ((ux == PINFBITPATT_DP64) & ypos) ? PINFBITPATT_DP64 : ret; + ret = ax > PINFBITPATT_DP64 ? ux : ret; + ret = ny == 0 ? 0x3ff0000000000000L : ret; + + return as_double(ret); +} +_CLC_BINARY_VECTORIZE(_CLC_DEF _CLC_OVERLOAD, double, __clc_pown, double, int) +#endif + +#ifdef cl_khr_fp16 +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +_CLC_DEF _CLC_OVERLOAD half __clc_pown(half x, int ny) { + return __clc_pown((float)x, ny); +} + +_CLC_BINARY_VECTORIZE(_CLC_DEF _CLC_OVERLOAD, half, __clc_pown, half, int) +#endif diff --git a/libclc/generic/libspirv/math/clc_powr.cl b/libclc/generic/libspirv/math/clc_powr.cl new file mode 100644 index 0000000000000..33b18a805d151 --- /dev/null +++ b/libclc/generic/libspirv/math/clc_powr.cl @@ -0,0 +1,403 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include "tables.h" +#include +#include +#include + +// compute pow using log and exp +// x^y = exp(y * log(x)) +// +// we take care not to lose precision in the intermediate steps +// +// When computing log, calculate it in splits, +// +// r = f * (p_invead + p_inv_tail) +// r = rh + rt +// +// calculate log polynomial using r, in end addition, do +// poly = poly + ((rh-r) + rt) +// +// lth = -r +// ltt = ((xexp * log2_t) - poly) + logT +// lt = lth + ltt +// +// lh = (xexp * log2_h) + logH +// l = lh + lt +// +// Calculate final log answer as gh and gt, +// gh = l & higher-half bits +// gt = (((ltt - (lt - lth)) + ((lh - l) + lt)) + (l - gh)) +// +// yh = y & higher-half bits +// yt = y - yh +// +// Before entering computation of exp, +// vs = ((yt*gt + yt*gh) + yh*gt) +// v = vs + yh*gh +// vt = ((yh*gh - v) + vs) +// +// In calculation of exp, add vt to r that is used for poly +// At the end of exp, do +// ((((expT * poly) + expT) + expH*poly) + expH) + +_CLC_DEF _CLC_OVERLOAD float __clc_powr(float x, float y) { + int ix = as_int(x); + int ax = ix & EXSIGNBIT_SP32; + int xpos = ix == ax; + + int iy = as_int(y); + int ay = iy & EXSIGNBIT_SP32; + int ypos = iy == ay; + + // Extra precise log calculation + // First handle case that x is close to 1 + float r = 1.0f - as_float(ax); + int near1 = __spirv_ocl_fabs(r) < 0x1.0p-4f; + float r2 = r * r; + + // Coefficients are just 1/3, 1/4, 1/5 and 1/6 + float poly = __spirv_ocl_mad( + r, + __spirv_ocl_mad( + r, + __spirv_ocl_mad(r, __spirv_ocl_mad(r, 0x1.24924ap-3f, 0x1.555556p-3f), + 0x1.99999ap-3f), + 0x1.000000p-2f), + 0x1.555556p-2f); + + poly *= r2 * r; + + float lth_near1 = -r2 * 0.5f; + float ltt_near1 = -poly; + float lt_near1 = lth_near1 + ltt_near1; + float lh_near1 = -r; + float l_near1 = lh_near1 + lt_near1; + + // Computations for x not near 1 + int m = (int)(ax >> EXPSHIFTBITS_SP32) - EXPBIAS_SP32; + float mf = (float)m; + int ixs = as_int(as_float(ax | 0x3f800000) - 1.0f); + float mfs = (float)((ixs >> EXPSHIFTBITS_SP32) - 253); + int c = m == -127; + int ixn = c ? ixs : ax; + float mfn = c ? mfs : mf; + + int indx = (ixn & 0x007f0000) + ((ixn & 0x00008000) << 1); + + // F - Y + float f = as_float(0x3f000000 | indx) - + as_float(0x3f000000 | (ixn & MANTBITS_SP32)); + + indx = indx >> 16; + float2 tv = USE_TABLE(log_inv_tbl_ep, indx); + float rh = f * tv.s0; + float rt = f * tv.s1; + r = rh + rt; + + poly = __spirv_ocl_mad(r, __spirv_ocl_mad(r, 0x1.0p-2f, 0x1.555556p-2f), + 0x1.0p-1f) * + (r * r); + poly += (rh - r) + rt; + + const float LOG2_HEAD = 0x1.62e000p-1f; // 0.693115234 + const float LOG2_TAIL = 0x1.0bfbe8p-15f; // 0.0000319461833 + tv = USE_TABLE(loge_tbl, indx); + float lth = -r; + float ltt = __spirv_ocl_mad(mfn, LOG2_TAIL, -poly) + tv.s1; + float lt = lth + ltt; + float lh = __spirv_ocl_mad(mfn, LOG2_HEAD, tv.s0); + float l = lh + lt; + + // Select near 1 or not + lth = near1 ? lth_near1 : lth; + ltt = near1 ? ltt_near1 : ltt; + lt = near1 ? lt_near1 : lt; + lh = near1 ? lh_near1 : lh; + l = near1 ? l_near1 : l; + + float gh = as_float(as_int(l) & 0xfffff000); + float gt = ((ltt - (lt - lth)) + ((lh - l) + lt)) + (l - gh); + + float yh = as_float(iy & 0xfffff000); + + float yt = y - yh; + + float ylogx_s = __spirv_ocl_mad(gt, yh, __spirv_ocl_mad(gh, yt, yt * gt)); + float ylogx = __spirv_ocl_mad(yh, gh, ylogx_s); + float ylogx_t = __spirv_ocl_mad(yh, gh, -ylogx) + ylogx_s; + + // Extra precise exp of ylogx + const float R_64_BY_LOG2 = 0x1.715476p+6f; // 64/log2 : 92.332482616893657 + int n = __spirv_ConvertFToS_Rint(ylogx * R_64_BY_LOG2); + float nf = (float)n; + + int j = n & 0x3f; + m = n >> 6; + int m2 = m << EXPSHIFTBITS_SP32; + + const float R_LOG2_BY_64_LD = 0x1.620000p-7f; // log2/64 lead: 0.0108032227 + const float R_LOG2_BY_64_TL = + 0x1.c85fdep-16f; // log2/64 tail: 0.0000272020388 + r = __spirv_ocl_mad(nf, -R_LOG2_BY_64_TL, + __spirv_ocl_mad(nf, -R_LOG2_BY_64_LD, ylogx)) + + ylogx_t; + + // Truncated Taylor series for e^r + poly = __spirv_ocl_mad( + __spirv_ocl_mad(__spirv_ocl_mad(r, 0x1.555556p-5f, 0x1.555556p-3f), r, + 0x1.000000p-1f), + r * r, r); + + tv = USE_TABLE(exp_tbl_ep, j); + + float expylogx = + __spirv_ocl_mad(tv.s0, poly, __spirv_ocl_mad(tv.s1, poly, tv.s1)) + tv.s0; + float sexpylogx = expylogx * as_float(0x1 << (m + 149)); + float texpylogx = as_float(as_int(expylogx) + m2); + expylogx = m < -125 ? sexpylogx : texpylogx; + + // Result is +-Inf if (ylogx + ylogx_t) > 128*log2 + expylogx = ((ylogx > 0x1.62e430p+6f) | + (ylogx == 0x1.62e430p+6f & ylogx_t > -0x1.05c610p-22f)) + ? as_float(PINFBITPATT_SP32) + : expylogx; + + // Result is 0 if ylogx < -149*log2 + expylogx = ylogx < -0x1.9d1da0p+6f ? 0.0f : expylogx; + + // Classify y: + // inty = 0 means not an integer. + // inty = 1 means odd integer. + // inty = 2 means even integer. + + int yexp = (int)(ay >> EXPSHIFTBITS_SP32) - EXPBIAS_SP32 + 1; + int mask = (1 << (24 - yexp)) - 1; + int yodd = ((iy >> (24 - yexp)) & 0x1) != 0; + int inty = yodd ? 1 : 2; + inty = (iy & mask) != 0 ? 0 : inty; + inty = yexp < 1 ? 0 : inty; + inty = yexp > 24 ? 2 : inty; + + float signval = as_float((as_uint(expylogx) ^ SIGNBIT_SP32)); + expylogx = ((inty == 1) & !xpos) ? signval : expylogx; + int ret = as_int(expylogx); + + // Corner case handling + ret = ax < 0x3f800000 && iy == NINFBITPATT_SP32 ? PINFBITPATT_SP32 : ret; + ret = ax < 0x3f800000 && iy == PINFBITPATT_SP32 ? 0 : ret; + ret = ax == 0x3f800000 && ay < PINFBITPATT_SP32 ? 0x3f800000 : ret; + ret = ax == 0x3f800000 && ay == PINFBITPATT_SP32 ? QNANBITPATT_SP32 : ret; + ret = ax > 0x3f800000 && iy == NINFBITPATT_SP32 ? 0 : ret; + ret = ax > 0x3f800000 && iy == PINFBITPATT_SP32 ? PINFBITPATT_SP32 : ret; + ret = ((ix < PINFBITPATT_SP32) & (ay == 0)) ? 0x3f800000 : ret; + ret = ((ax == PINFBITPATT_SP32) & !ypos) ? 0 : ret; + ret = ((ax == PINFBITPATT_SP32) & ypos) ? PINFBITPATT_SP32 : ret; + ret = ((ax == PINFBITPATT_SP32) & (iy == PINFBITPATT_SP32)) ? PINFBITPATT_SP32 + : ret; + ret = ((ax == PINFBITPATT_SP32) & (ay == 0)) ? QNANBITPATT_SP32 : ret; + ret = ((ax == 0) & !ypos) ? PINFBITPATT_SP32 : ret; + ret = ((ax == 0) & ypos) ? 0 : ret; + ret = ((ax == 0) & (ay == 0)) ? QNANBITPATT_SP32 : ret; + ret = ((ax != 0) & !xpos) ? QNANBITPATT_SP32 : ret; + ret = ax > PINFBITPATT_SP32 ? ix : ret; + ret = ay > PINFBITPATT_SP32 ? iy : ret; + + return as_float(ret); +} +_CLC_BINARY_VECTORIZE(_CLC_DEF _CLC_OVERLOAD, float, __clc_powr, float, float) + +#ifdef cl_khr_fp64 +_CLC_DEF _CLC_OVERLOAD double __clc_powr(double x, double y) { + const double real_log2_tail = 5.76999904754328540596e-08; + const double real_log2_lead = 6.93147122859954833984e-01; + + long ux = as_long(x); + long ax = ux & (~SIGNBIT_DP64); + int xpos = ax == ux; + + long uy = as_long(y); + long ay = uy & (~SIGNBIT_DP64); + int ypos = ay == uy; + + // Extended precision log + double v, vt; + { + int exp = (int)(ax >> 52) - 1023; + int mask_exp_1023 = exp == -1023; + double xexp = (double)exp; + long mantissa = ax & 0x000FFFFFFFFFFFFFL; + + long temp_ux = as_long(as_double(0x3ff0000000000000L | mantissa) - 1.0); + exp = ((temp_ux & 0x7FF0000000000000L) >> 52) - 2045; + double xexp1 = (double)exp; + long mantissa1 = temp_ux & 0x000FFFFFFFFFFFFFL; + + xexp = mask_exp_1023 ? xexp1 : xexp; + mantissa = mask_exp_1023 ? mantissa1 : mantissa; + + long rax = (mantissa & 0x000ff00000000000) + + ((mantissa & 0x0000080000000000) << 1); + int index = rax >> 44; + + double F = as_double(rax | 0x3FE0000000000000L); + double Y = as_double(mantissa | 0x3FE0000000000000L); + double f = F - Y; + double2 tv = USE_TABLE(log_f_inv_tbl, index); + double log_h = tv.s0; + double log_t = tv.s1; + double f_inv = (log_h + log_t) * f; + double r1 = as_double(as_long(f_inv) & 0xfffffffff8000000L); + double r2 = __spirv_ocl_fma(-F, r1, f) * (log_h + log_t); + double r = r1 + r2; + + double poly = __spirv_ocl_fma( + r, + __spirv_ocl_fma( + r, + __spirv_ocl_fma(r, __spirv_ocl_fma(r, 1.0 / 7.0, 1.0 / 6.0), + 1.0 / 5.0), + 1.0 / 4.0), + 1.0 / 3.0); + poly = poly * r * r * r; + + double hr1r1 = 0.5 * r1 * r1; + double poly0h = r1 + hr1r1; + double poly0t = r1 - poly0h + hr1r1; + poly = __spirv_ocl_fma(r1, r2, __spirv_ocl_fma(0.5 * r2, r2, poly)) + r2 + + poly0t; + + tv = USE_TABLE(powlog_tbl, index); + log_h = tv.s0; + log_t = tv.s1; + + double resT_t = __spirv_ocl_fma(xexp, real_log2_tail, +log_t) - poly; + double resT = resT_t - poly0h; + double resH = __spirv_ocl_fma(xexp, real_log2_lead, log_h); + double resT_h = poly0h; + + double H = resT + resH; + double H_h = as_double(as_long(H) & 0xfffffffff8000000L); + double T = (resH - H + resT) + (resT_t - (resT + resT_h)) + (H - H_h); + H = H_h; + + double y_head = as_double(uy & 0xfffffffff8000000L); + double y_tail = y - y_head; + + double temp = + __spirv_ocl_fma(y_tail, H, __spirv_ocl_fma(y_head, T, y_tail * T)); + v = __spirv_ocl_fma(y_head, H, temp); + vt = __spirv_ocl_fma(y_head, H, -v) + temp; + } + + // Now calculate exp of (v,vt) + + double expv; + { + const double max_exp_arg = 709.782712893384; + const double min_exp_arg = -745.1332191019411; + const double sixtyfour_by_lnof2 = 92.33248261689366; + const double lnof2_by_64_head = 0.010830424260348081; + const double lnof2_by_64_tail = -4.359010638708991e-10; + + double temp = v * sixtyfour_by_lnof2; + int n = (int)temp; + double dn = (double)n; + int j = n & 0x0000003f; + int m = n >> 6; + + double2 tv = USE_TABLE(two_to_jby64_ep_tbl, j); + double f1 = tv.s0; + double f2 = tv.s1; + double f = f1 + f2; + + double r1 = __spirv_ocl_fma(dn, -lnof2_by_64_head, v); + double r2 = dn * lnof2_by_64_tail; + double r = (r1 + r2) + vt; + + double q = __spirv_ocl_fma( + r, + __spirv_ocl_fma( + r, + __spirv_ocl_fma(r, + __spirv_ocl_fma(r, 1.38889490863777199667e-03, + 8.33336798434219616221e-03), + 4.16666666662260795726e-02), + 1.66666666665260878863e-01), + 5.00000000000000008883e-01); + q = __spirv_ocl_fma(r * r, q, r); + + expv = __spirv_ocl_fma(f, q, f2) + f1; + expv = __spirv_ocl_ldexp(expv, m); + + expv = v > max_exp_arg ? as_double(0x7FF0000000000000L) : expv; + expv = v < min_exp_arg ? 0.0 : expv; + } + + // See whether y is an integer. + // inty = 0 means not an integer. + // inty = 1 means odd integer. + // inty = 2 means even integer. + + int inty; + { + int yexp = (int)(ay >> EXPSHIFTBITS_DP64) - EXPBIAS_DP64 + 1; + inty = yexp < 1 ? 0 : 2; + inty = yexp > 53 ? 2 : inty; + long mask = (1L << (53 - yexp)) - 1L; + int inty1 = (((ay & ~mask) >> (53 - yexp)) & 1L) == 1L ? 1 : 2; + inty1 = (ay & mask) != 0 ? 0 : inty1; + inty = !(yexp < 1) && !(yexp > 53) ? inty1 : inty; + } + + expv *= ((inty == 1) & !xpos) ? -1.0 : 1.0; + + long ret = as_long(expv); + + // Now all the edge cases + ret = ax < 0x3ff0000000000000L && uy == NINFBITPATT_DP64 ? PINFBITPATT_DP64 + : ret; + ret = ax < 0x3ff0000000000000L && uy == PINFBITPATT_DP64 ? 0L : ret; + ret = ax == 0x3ff0000000000000L && ay < PINFBITPATT_DP64 ? 0x3ff0000000000000L + : ret; + ret = ax == 0x3ff0000000000000L && ay == PINFBITPATT_DP64 ? QNANBITPATT_DP64 + : ret; + ret = ax > 0x3ff0000000000000L && uy == NINFBITPATT_DP64 ? 0L : ret; + ret = ax > 0x3ff0000000000000L && uy == PINFBITPATT_DP64 ? PINFBITPATT_DP64 + : ret; + ret = ux < PINFBITPATT_DP64 && ay == 0L ? 0x3ff0000000000000L : ret; + ret = ((ax == PINFBITPATT_DP64) & !ypos) ? 0L : ret; + ret = ((ax == PINFBITPATT_DP64) & ypos) ? PINFBITPATT_DP64 : ret; + ret = ((ax == PINFBITPATT_DP64) & (uy == PINFBITPATT_DP64)) ? PINFBITPATT_DP64 + : ret; + ret = ((ax == PINFBITPATT_DP64) & (ay == 0L)) ? QNANBITPATT_DP64 : ret; + ret = ((ax == 0L) & !ypos) ? PINFBITPATT_DP64 : ret; + ret = ((ax == 0L) & ypos) ? 0L : ret; + ret = ((ax == 0L) & (ay == 0L)) ? QNANBITPATT_DP64 : ret; + ret = ((ax != 0L) & !xpos) ? QNANBITPATT_DP64 : ret; + ret = ax > PINFBITPATT_DP64 ? ux : ret; + ret = ay > PINFBITPATT_DP64 ? uy : ret; + + return as_double(ret); +} +_CLC_BINARY_VECTORIZE(_CLC_DEF _CLC_OVERLOAD, double, __clc_powr, double, + double) +#endif + +#ifdef cl_khr_fp16 +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +_CLC_DEF _CLC_OVERLOAD half __clc_powr(half x, half y) { + return __clc_powr((float)x, (float)y); +} + +_CLC_BINARY_VECTORIZE(_CLC_DEF _CLC_OVERLOAD, half, __clc_powr, half, half) +#endif diff --git a/libclc/generic/libspirv/math/clc_remainder.cl b/libclc/generic/libspirv/math/clc_remainder.cl new file mode 100644 index 0000000000000..ccef76690571a --- /dev/null +++ b/libclc/generic/libspirv/math/clc_remainder.cl @@ -0,0 +1,204 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include +#include +#include +#include + +_CLC_DEF _CLC_OVERLOAD float __clc_remainder(float x, float y) { + int ux = as_int(x); + int ax = ux & EXSIGNBIT_SP32; + float xa = as_float(ax); + int sx = ux ^ ax; + int ex = ax >> EXPSHIFTBITS_SP32; + + int uy = as_int(y); + int ay = uy & EXSIGNBIT_SP32; + float ya = as_float(ay); + int ey = ay >> EXPSHIFTBITS_SP32; + + float xr = as_float(0x3f800000 | (ax & 0x007fffff)); + float yr = as_float(0x3f800000 | (ay & 0x007fffff)); + int c; + int k = ex - ey; + + uint q = 0; + + while (k > 0) { + c = xr >= yr; + q = (q << 1) | c; + xr -= c ? yr : 0.0f; + xr += xr; + --k; + } + + c = xr > yr; + q = (q << 1) | c; + xr -= c ? yr : 0.0f; + + int lt = ex < ey; + + q = lt ? 0 : q; + xr = lt ? xa : xr; + yr = lt ? ya : yr; + + c = (yr < 2.0f * xr) | ((yr == 2.0f * xr) & ((q & 0x1) == 0x1)); + xr -= c ? yr : 0.0f; + q += c; + + float s = as_float(ey << EXPSHIFTBITS_SP32); + xr *= lt ? 1.0f : s; + + c = ax == ay; + xr = c ? 0.0f : xr; + + xr = as_float(sx ^ as_int(xr)); + + c = ax > PINFBITPATT_SP32 | ay > PINFBITPATT_SP32 | ax == PINFBITPATT_SP32 | + ay == 0; + xr = c ? as_float(QNANBITPATT_SP32) : xr; + + return xr; +} +_CLC_BINARY_VECTORIZE(_CLC_DEF _CLC_OVERLOAD, float, __clc_remainder, float, + float); + +#ifdef cl_khr_fp64 +_CLC_DEF _CLC_OVERLOAD double __clc_remainder(double x, double y) { + ulong ux = as_ulong(x); + ulong ax = ux & ~SIGNBIT_DP64; + ulong xsgn = ux ^ ax; + double dx = as_double(ax); + int xexp = __spirv_SatConvertUToS_Rint(ax >> EXPSHIFTBITS_DP64); + int xexp1 = 11 - (int)__spirv_ocl_clz(ax & MANTBITS_DP64); + xexp1 = xexp < 1 ? xexp1 : xexp; + + ulong uy = as_ulong(y); + ulong ay = uy & ~SIGNBIT_DP64; + double dy = as_double(ay); + int yexp = __spirv_SatConvertUToS_Rint(ay >> EXPSHIFTBITS_DP64); + int yexp1 = 11 - (int)__spirv_ocl_clz(ay & MANTBITS_DP64); + yexp1 = yexp < 1 ? yexp1 : yexp; + + int qsgn = ((ux ^ uy) & SIGNBIT_DP64) == 0UL ? 1 : -1; + + // First assume |x| > |y| + + // Set ntimes to the number of times we need to do a + // partial remainder. If the exponent of x is an exact multiple + // of 53 larger than the exponent of y, and the mantissa of x is + // less than the mantissa of y, ntimes will be one too large + // but it doesn't matter - it just means that we'll go round + // the loop below one extra time. + int ntimes = __spirv_ocl_s_max(0, (xexp1 - yexp1) / 53); + double w = __spirv_ocl_ldexp(dy, ntimes * 53); + w = ntimes == 0 ? dy : w; + double scale = ntimes == 0 ? 1.0 : 0x1.0p-53; + + // Each time round the loop we compute a partial remainder. + // This is done by subtracting a large multiple of w + // from x each time, where w is a scaled up version of y. + // The subtraction must be performed exactly in quad + // precision, though the result at each stage can + // fit exactly in a double precision number. + int i; + double t, v, p, pp; + + for (i = 0; i < ntimes; i++) { + // Compute integral multiplier + t = __spirv_ocl_trunc(dx / w); + + // Compute w * t in quad precision + p = w * t; + pp = __spirv_ocl_fma(w, t, -p); + + // Subtract w * t from dx + v = dx - p; + dx = v + (((dx - v) - p) - pp); + + // If t was one too large, dx will be negative. Add back one w. + dx += dx < 0.0 ? w : 0.0; + + // Scale w down by 2^(-53) for the next iteration + w *= scale; + } + + // One more time + // Variable todd says whether the integer t is odd or not + t = __spirv_ocl_floor(dx / w); + long lt = (long)t; + int todd = lt & 1; + + p = w * t; + pp = __spirv_ocl_fma(w, t, -p); + v = dx - p; + dx = v + (((dx - v) - p) - pp); + i = dx < 0.0; + todd ^= i; + dx += i ? w : 0.0; + + // At this point, dx lies in the range [0,dy) + + // For the fmod function, we're done apart from setting the correct sign. + // + // For the remainder function, we need to adjust dx + // so that it lies in the range (-y/2, y/2] by carefully + // subtracting w (== dy == y) if necessary. The rigmarole + // with todd is to get the correct sign of the result + // when x/y lies exactly half way between two integers, + // when we need to choose the even integer. + + int al = (2.0 * dx > w) | (todd & (2.0 * dx == w)); + double dxl = dx - (al ? w : 0.0); + + int ag = (dx > 0.5 * w) | (todd & (dx == 0.5 * w)); + double dxg = dx - (ag ? w : 0.0); + + dx = dy < 0x1.0p+1022 ? dxl : dxg; + + double ret = as_double(xsgn ^ as_ulong(dx)); + dx = as_double(ax); + + // Now handle |x| == |y| + int c = dx == dy; + t = as_double(xsgn); + ret = c ? t : ret; + + // Next, handle |x| < |y| + c = dx < dy; + ret = c ? x : ret; + + c &= (yexp<1023 & 2.0 * dx> dy) | (dx > 0.5 * dy); + // we could use a conversion here instead since qsgn = +-1 + p = qsgn == 1 ? -1.0 : 1.0; + t = __spirv_ocl_fma(y, p, x); + ret = c ? t : ret; + + // We don't need anything special for |x| == 0 + + // |y| is 0 + c = dy == 0.0; + ret = c ? as_double(QNANBITPATT_DP64) : ret; + + // y is +-Inf, NaN + c = yexp > BIASEDEMAX_DP64; + t = y == y ? x : y; + ret = c ? t : ret; + + // x is +=Inf, NaN + c = xexp > BIASEDEMAX_DP64; + ret = c ? as_double(QNANBITPATT_DP64) : ret; + + return ret; +} +_CLC_BINARY_VECTORIZE(_CLC_DEF _CLC_OVERLOAD, double, __clc_remainder, double, + double); +#endif diff --git a/libclc/generic/libspirv/math/clc_remquo.cl b/libclc/generic/libspirv/math/clc_remquo.cl new file mode 100644 index 0000000000000..3db7ffb16b6fa --- /dev/null +++ b/libclc/generic/libspirv/math/clc_remquo.cl @@ -0,0 +1,257 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include +#include +#include +#include + +_CLC_DEF _CLC_OVERLOAD float __clc_remquo(float x, float y, + __private int *quo) { + x = __clc_flush_denormal_if_not_supported(x); + y = __clc_flush_denormal_if_not_supported(y); + int ux = as_int(x); + int ax = ux & EXSIGNBIT_SP32; + float xa = as_float(ax); + int sx = ux ^ ax; + int ex = ax >> EXPSHIFTBITS_SP32; + + int uy = as_int(y); + int ay = uy & EXSIGNBIT_SP32; + float ya = as_float(ay); + int sy = uy ^ ay; + int ey = ay >> EXPSHIFTBITS_SP32; + + float xr = as_float(0x3f800000 | (ax & 0x007fffff)); + float yr = as_float(0x3f800000 | (ay & 0x007fffff)); + int c; + int k = ex - ey; + + uint q = 0; + + while (k > 0) { + c = xr >= yr; + q = (q << 1) | c; + xr -= c ? yr : 0.0f; + xr += xr; + --k; + } + + c = xr > yr; + q = (q << 1) | c; + xr -= c ? yr : 0.0f; + + int lt = ex < ey; + + q = lt ? 0 : q; + xr = lt ? xa : xr; + yr = lt ? ya : yr; + + c = (yr < 2.0f * xr) | ((yr == 2.0f * xr) & ((q & 0x1) == 0x1)); + xr -= c ? yr : 0.0f; + q += c; + + float s = as_float(ey << EXPSHIFTBITS_SP32); + xr *= lt ? 1.0f : s; + + int qsgn = sx == sy ? 1 : -1; + int quot = (q & 0x7f) * qsgn; + + c = ax == ay; + quot = c ? qsgn : quot; + xr = c ? 0.0f : xr; + + xr = as_float(sx ^ as_int(xr)); + + c = ax > PINFBITPATT_SP32 | ay > PINFBITPATT_SP32 | ax == PINFBITPATT_SP32 | + ay == 0; + quot = c ? 0 : quot; + xr = c ? as_float(QNANBITPATT_SP32) : xr; + + *quo = quot; + + return xr; +} +// remquo singature is special, we don't have macro for this +#define __VEC_REMQUO(TYPE, VEC_SIZE, HALF_VEC_SIZE) \ + _CLC_DEF _CLC_OVERLOAD TYPE##VEC_SIZE __clc_remquo( \ + TYPE##VEC_SIZE x, TYPE##VEC_SIZE y, __private int##VEC_SIZE *quo) { \ + int##HALF_VEC_SIZE lo, hi; \ + TYPE##VEC_SIZE ret; \ + ret.lo = __clc_remquo(x.lo, y.lo, &lo); \ + ret.hi = __clc_remquo(x.hi, y.hi, &hi); \ + (*quo).lo = lo; \ + (*quo).hi = hi; \ + return ret; \ + } +__VEC_REMQUO(float, 2, ) +__VEC_REMQUO(float, 3, 2) +__VEC_REMQUO(float, 4, 2) +__VEC_REMQUO(float, 8, 4) +__VEC_REMQUO(float, 16, 8) + +#ifdef cl_khr_fp64 +_CLC_DEF _CLC_OVERLOAD double __clc_remquo(double x, double y, + __private int *pquo) { + ulong ux = as_ulong(x); + ulong ax = ux & ~SIGNBIT_DP64; + ulong xsgn = ux ^ ax; + double dx = as_double(ax); + int xexp = __spirv_SatConvertUToS_Rint(ax >> EXPSHIFTBITS_DP64); + int xexp1 = 11 - (int)__spirv_ocl_clz(ax & MANTBITS_DP64); + xexp1 = xexp < 1 ? xexp1 : xexp; + + ulong uy = as_ulong(y); + ulong ay = uy & ~SIGNBIT_DP64; + double dy = as_double(ay); + int yexp = __spirv_SatConvertUToS_Rint(ay >> EXPSHIFTBITS_DP64); + int yexp1 = 11 - (int)__spirv_ocl_clz(ay & MANTBITS_DP64); + yexp1 = yexp < 1 ? yexp1 : yexp; + + int qsgn = ((ux ^ uy) & SIGNBIT_DP64) == 0UL ? 1 : -1; + + // First assume |x| > |y| + + // Set ntimes to the number of times we need to do a + // partial remainder. If the exponent of x is an exact multiple + // of 53 larger than the exponent of y, and the mantissa of x is + // less than the mantissa of y, ntimes will be one too large + // but it doesn't matter - it just means that we'll go round + // the loop below one extra time. + int ntimes = __spirv_ocl_s_max(0, (xexp1 - yexp1) / 53); + double w = __spirv_ocl_ldexp(dy, ntimes * 53); + w = ntimes == 0 ? dy : w; + double scale = ntimes == 0 ? 1.0 : 0x1.0p-53; + + // Each time round the loop we compute a partial remainder. + // This is done by subtracting a large multiple of w + // from x each time, where w is a scaled up version of y. + // The subtraction must be performed exactly in quad + // precision, though the result at each stage can + // fit exactly in a double precision number. + int i; + double t, v, p, pp; + + for (i = 0; i < ntimes; i++) { + // Compute integral multiplier + t = __spirv_ocl_trunc(dx / w); + + // Compute w * t in quad precision + p = w * t; + pp = __spirv_ocl_fma(w, t, -p); + + // Subtract w * t from dx + v = dx - p; + dx = v + (((dx - v) - p) - pp); + + // If t was one too large, dx will be negative. Add back one w. + dx += dx < 0.0 ? w : 0.0; + + // Scale w down by 2^(-53) for the next iteration + w *= scale; + } + + // One more time + // Variable todd says whether the integer t is odd or not + t = __spirv_ocl_floor(dx / w); + long lt = (long)t; + int todd = lt & 1; + + p = w * t; + pp = __spirv_ocl_fma(w, t, -p); + v = dx - p; + dx = v + (((dx - v) - p) - pp); + i = dx < 0.0; + todd ^= i; + dx += i ? w : 0.0; + + lt -= i; + + // At this point, dx lies in the range [0,dy) + + // For the remainder function, we need to adjust dx + // so that it lies in the range (-y/2, y/2] by carefully + // subtracting w (== dy == y) if necessary. The rigmarole + // with todd is to get the correct sign of the result + // when x/y lies exactly half way between two integers, + // when we need to choose the even integer. + + int al = (2.0 * dx > w) | (todd & (2.0 * dx == w)); + double dxl = dx - (al ? w : 0.0); + + int ag = (dx > 0.5 * w) | (todd & (dx == 0.5 * w)); + double dxg = dx - (ag ? w : 0.0); + + dx = dy < 0x1.0p+1022 ? dxl : dxg; + lt += dy < 0x1.0p+1022 ? al : ag; + int quo = ((int)lt & 0x7f) * qsgn; + + double ret = as_double(xsgn ^ as_ulong(dx)); + dx = as_double(ax); + + // Now handle |x| == |y| + int c = dx == dy; + t = as_double(xsgn); + quo = c ? qsgn : quo; + ret = c ? t : ret; + + // Next, handle |x| < |y| + c = dx < dy; + quo = c ? 0 : quo; + ret = c ? x : ret; + + c &= (yexp<1023 & 2.0 * dx> dy) | (dx > 0.5 * dy); + quo = c ? qsgn : quo; + // we could use a conversion here instead since qsgn = +-1 + p = qsgn == 1 ? -1.0 : 1.0; + t = __spirv_ocl_fma(y, p, x); + ret = c ? t : ret; + + // We don't need anything special for |x| == 0 + + // |y| is 0 + c = dy == 0.0; + quo = c ? 0 : quo; + ret = c ? as_double(QNANBITPATT_DP64) : ret; + + // y is +-Inf, NaN + c = yexp > BIASEDEMAX_DP64; + quo = c ? 0 : quo; + t = y == y ? x : y; + ret = c ? t : ret; + + // x is +=Inf, NaN + c = xexp > BIASEDEMAX_DP64; + quo = c ? 0 : quo; + ret = c ? as_double(QNANBITPATT_DP64) : ret; + + *pquo = quo; + return ret; +} +__VEC_REMQUO(double, 2, ) +__VEC_REMQUO(double, 3, 2) +__VEC_REMQUO(double, 4, 2) +__VEC_REMQUO(double, 8, 4) +__VEC_REMQUO(double, 16, 8) +#endif + +#ifdef cl_khr_fp16 +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +_CLC_DEF _CLC_OVERLOAD half __clc_remquo(half x, half y, __private int *pquo) { + return __clc_remquo((float)x, (float)y, pquo); +} + +__VEC_REMQUO(half, 2, ) +__VEC_REMQUO(half, 3, 2) +__VEC_REMQUO(half, 4, 2) +__VEC_REMQUO(half, 8, 4) +__VEC_REMQUO(half, 16, 8) +#endif diff --git a/libclc/generic/libspirv/math/clc_rootn.cl b/libclc/generic/libspirv/math/clc_rootn.cl new file mode 100644 index 0000000000000..f5a35d106a8c3 --- /dev/null +++ b/libclc/generic/libspirv/math/clc_rootn.cl @@ -0,0 +1,393 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include "tables.h" +#include +#include +#include + +// compute pow using log and exp +// x^y = exp(y * log(x)) +// +// we take care not to lose precision in the intermediate steps +// +// When computing log, calculate it in splits, +// +// r = f * (p_invead + p_inv_tail) +// r = rh + rt +// +// calculate log polynomial using r, in end addition, do +// poly = poly + ((rh-r) + rt) +// +// lth = -r +// ltt = ((xexp * log2_t) - poly) + logT +// lt = lth + ltt +// +// lh = (xexp * log2_h) + logH +// l = lh + lt +// +// Calculate final log answer as gh and gt, +// gh = l & higher-half bits +// gt = (((ltt - (lt - lth)) + ((lh - l) + lt)) + (l - gh)) +// +// yh = y & higher-half bits +// yt = y - yh +// +// Before entering computation of exp, +// vs = ((yt*gt + yt*gh) + yh*gt) +// v = vs + yh*gh +// vt = ((yh*gh - v) + vs) +// +// In calculation of exp, add vt to r that is used for poly +// At the end of exp, do +// ((((expT * poly) + expT) + expH*poly) + expH) + +_CLC_DEF _CLC_OVERLOAD float __clc_rootn(float x, int ny) { + float y = MATH_RECIP((float)ny); + + int ix = as_int(x); + int ax = ix & EXSIGNBIT_SP32; + int xpos = ix == ax; + + int iy = as_int(y); + int ay = iy & EXSIGNBIT_SP32; + int ypos = iy == ay; + + // Extra precise log calculation + // First handle case that x is close to 1 + float r = 1.0f - as_float(ax); + int near1 = __spirv_ocl_fabs(r) < 0x1.0p-4f; + float r2 = r * r; + + // Coefficients are just 1/3, 1/4, 1/5 and 1/6 + float poly = __spirv_ocl_mad( + r, + __spirv_ocl_mad( + r, + __spirv_ocl_mad(r, __spirv_ocl_mad(r, 0x1.24924ap-3f, 0x1.555556p-3f), + 0x1.99999ap-3f), + 0x1.000000p-2f), + 0x1.555556p-2f); + + poly *= r2 * r; + + float lth_near1 = -r2 * 0.5f; + float ltt_near1 = -poly; + float lt_near1 = lth_near1 + ltt_near1; + float lh_near1 = -r; + float l_near1 = lh_near1 + lt_near1; + + // Computations for x not near 1 + int m = (int)(ax >> EXPSHIFTBITS_SP32) - EXPBIAS_SP32; + float mf = (float)m; + int ixs = as_int(as_float(ax | 0x3f800000) - 1.0f); + float mfs = (float)((ixs >> EXPSHIFTBITS_SP32) - 253); + int c = m == -127; + int ixn = c ? ixs : ax; + float mfn = c ? mfs : mf; + + int indx = (ixn & 0x007f0000) + ((ixn & 0x00008000) << 1); + + // F - Y + float f = as_float(0x3f000000 | indx) - + as_float(0x3f000000 | (ixn & MANTBITS_SP32)); + + indx = indx >> 16; + float2 tv = USE_TABLE(log_inv_tbl_ep, indx); + float rh = f * tv.s0; + float rt = f * tv.s1; + r = rh + rt; + + poly = __spirv_ocl_mad(r, __spirv_ocl_mad(r, 0x1.0p-2f, 0x1.555556p-2f), + 0x1.0p-1f) * + (r * r); + poly += (rh - r) + rt; + + const float LOG2_HEAD = 0x1.62e000p-1f; // 0.693115234 + const float LOG2_TAIL = 0x1.0bfbe8p-15f; // 0.0000319461833 + tv = USE_TABLE(loge_tbl, indx); + float lth = -r; + float ltt = __spirv_ocl_mad(mfn, LOG2_TAIL, -poly) + tv.s1; + float lt = lth + ltt; + float lh = __spirv_ocl_mad(mfn, LOG2_HEAD, tv.s0); + float l = lh + lt; + + // Select near 1 or not + lth = near1 ? lth_near1 : lth; + ltt = near1 ? ltt_near1 : ltt; + lt = near1 ? lt_near1 : lt; + lh = near1 ? lh_near1 : lh; + l = near1 ? l_near1 : l; + + float gh = as_float(as_int(l) & 0xfffff000); + float gt = ((ltt - (lt - lth)) + ((lh - l) + lt)) + (l - gh); + + float yh = as_float(iy & 0xfffff000); + + float fny = (float)ny; + float fnyh = as_float(as_int(fny) & 0xfffff000); + float fnyt = (float)(ny - (int)fnyh); + float yt = MATH_DIVIDE( + __spirv_ocl_mad(-fnyt, yh, __spirv_ocl_mad(-fnyh, yh, 1.0f)), fny); + + float ylogx_s = __spirv_ocl_mad(gt, yh, __spirv_ocl_mad(gh, yt, yt * gt)); + float ylogx = __spirv_ocl_mad(yh, gh, ylogx_s); + float ylogx_t = __spirv_ocl_mad(yh, gh, -ylogx) + ylogx_s; + + // Extra precise exp of ylogx + const float R_64_BY_LOG2 = 0x1.715476p+6f; // 64/log2 : 92.332482616893657 + int n = __spirv_ConvertFToS_Rint(ylogx * R_64_BY_LOG2); + float nf = (float)n; + + int j = n & 0x3f; + m = n >> 6; + int m2 = m << EXPSHIFTBITS_SP32; + + const float R_LOG2_BY_64_LD = 0x1.620000p-7f; // log2/64 lead: 0.0108032227 + const float R_LOG2_BY_64_TL = + 0x1.c85fdep-16f; // log2/64 tail: 0.0000272020388 + r = __spirv_ocl_mad(nf, -R_LOG2_BY_64_TL, + __spirv_ocl_mad(nf, -R_LOG2_BY_64_LD, ylogx)) + + ylogx_t; + + // Truncated Taylor series for e^r + poly = __spirv_ocl_mad( + __spirv_ocl_mad(__spirv_ocl_mad(r, 0x1.555556p-5f, 0x1.555556p-3f), r, + 0x1.000000p-1f), + r * r, r); + + tv = USE_TABLE(exp_tbl_ep, j); + + float expylogx = + __spirv_ocl_mad(tv.s0, poly, __spirv_ocl_mad(tv.s1, poly, tv.s1)) + tv.s0; + float sexpylogx = __clc_fp32_subnormals_supported() + ? expylogx * as_float(0x1 << (m + 149)) + : 0.0f; + + float texpylogx = as_float(as_int(expylogx) + m2); + expylogx = m < -125 ? sexpylogx : texpylogx; + + // Result is +-Inf if (ylogx + ylogx_t) > 128*log2 + expylogx = ((ylogx > 0x1.62e430p+6f) | + (ylogx == 0x1.62e430p+6f & ylogx_t > -0x1.05c610p-22f)) + ? as_float(PINFBITPATT_SP32) + : expylogx; + + // Result is 0 if ylogx < -149*log2 + expylogx = ylogx < -0x1.9d1da0p+6f ? 0.0f : expylogx; + + // Classify y: + // inty = 0 means not an integer. + // inty = 1 means odd integer. + // inty = 2 means even integer. + + int inty = 2 - (ny & 1); + + float signval = as_float((as_uint(expylogx) ^ SIGNBIT_SP32)); + expylogx = ((inty == 1) & !xpos) ? signval : expylogx; + int ret = as_int(expylogx); + + // Corner case handling + ret = (!xpos & (inty == 2)) ? QNANBITPATT_SP32 : ret; + int xinf = xpos ? PINFBITPATT_SP32 : NINFBITPATT_SP32; + ret = ((ax == 0) & !ypos & (inty == 1)) ? xinf : ret; + ret = ((ax == 0) & !ypos & (inty == 2)) ? PINFBITPATT_SP32 : ret; + ret = ((ax == 0) & ypos & (inty == 2)) ? 0 : ret; + int xzero = xpos ? 0 : 0x80000000; + ret = ((ax == 0) & ypos & (inty == 1)) ? xzero : ret; + ret = + ((ix == NINFBITPATT_SP32) & ypos & (inty == 1)) ? NINFBITPATT_SP32 : ret; + ret = ((ix == NINFBITPATT_SP32) & !ypos & (inty == 1)) ? 0x80000000 : ret; + ret = ((ix == PINFBITPATT_SP32) & !ypos) ? 0 : ret; + ret = ((ix == PINFBITPATT_SP32) & ypos) ? PINFBITPATT_SP32 : ret; + ret = ax > PINFBITPATT_SP32 ? ix : ret; + ret = ny == 0 ? QNANBITPATT_SP32 : ret; + + return as_float(ret); +} +_CLC_BINARY_VECTORIZE(_CLC_DEF _CLC_OVERLOAD, float, __clc_rootn, float, int) + +#ifdef cl_khr_fp64 +_CLC_DEF _CLC_OVERLOAD double __clc_rootn(double x, int ny) { + const double real_log2_tail = 5.76999904754328540596e-08; + const double real_log2_lead = 6.93147122859954833984e-01; + + double dny = (double)ny; + double y = 1.0 / dny; + + long ux = as_long(x); + long ax = ux & (~SIGNBIT_DP64); + int xpos = ax == ux; + + long uy = as_long(y); + long ay = uy & (~SIGNBIT_DP64); + int ypos = ay == uy; + + // Extended precision log + double v, vt; + { + int exp = (int)(ax >> 52) - 1023; + int mask_exp_1023 = exp == -1023; + double xexp = (double)exp; + long mantissa = ax & 0x000FFFFFFFFFFFFFL; + + long temp_ux = as_long(as_double(0x3ff0000000000000L | mantissa) - 1.0); + exp = ((temp_ux & 0x7FF0000000000000L) >> 52) - 2045; + double xexp1 = (double)exp; + long mantissa1 = temp_ux & 0x000FFFFFFFFFFFFFL; + + xexp = mask_exp_1023 ? xexp1 : xexp; + mantissa = mask_exp_1023 ? mantissa1 : mantissa; + + long rax = (mantissa & 0x000ff00000000000) + + ((mantissa & 0x0000080000000000) << 1); + int index = rax >> 44; + + double F = as_double(rax | 0x3FE0000000000000L); + double Y = as_double(mantissa | 0x3FE0000000000000L); + double f = F - Y; + double2 tv = USE_TABLE(log_f_inv_tbl, index); + double log_h = tv.s0; + double log_t = tv.s1; + double f_inv = (log_h + log_t) * f; + double r1 = as_double(as_long(f_inv) & 0xfffffffff8000000L); + double r2 = __spirv_ocl_fma(-F, r1, f) * (log_h + log_t); + double r = r1 + r2; + + double poly = __spirv_ocl_fma( + r, + __spirv_ocl_fma( + r, + __spirv_ocl_fma(r, __spirv_ocl_fma(r, 1.0 / 7.0, 1.0 / 6.0), + 1.0 / 5.0), + 1.0 / 4.0), + 1.0 / 3.0); + poly = poly * r * r * r; + + double hr1r1 = 0.5 * r1 * r1; + double poly0h = r1 + hr1r1; + double poly0t = r1 - poly0h + hr1r1; + poly = __spirv_ocl_fma(r1, r2, __spirv_ocl_fma(0.5 * r2, r2, poly)) + r2 + + poly0t; + + tv = USE_TABLE(powlog_tbl, index); + log_h = tv.s0; + log_t = tv.s1; + + double resT_t = __spirv_ocl_fma(xexp, real_log2_tail, +log_t) - poly; + double resT = resT_t - poly0h; + double resH = __spirv_ocl_fma(xexp, real_log2_lead, log_h); + double resT_h = poly0h; + + double H = resT + resH; + double H_h = as_double(as_long(H) & 0xfffffffff8000000L); + double T = (resH - H + resT) + (resT_t - (resT + resT_h)) + (H - H_h); + H = H_h; + + double y_head = as_double(uy & 0xfffffffff8000000L); + double y_tail = y - y_head; + + double fnyh = as_double(as_long(dny) & 0xfffffffffff00000); + double fnyt = (double)(ny - (int)fnyh); + y_tail = + __spirv_ocl_fma(-fnyt, y_head, __spirv_ocl_fma(-fnyh, y_head, 1.0)) / + dny; + + double temp = + __spirv_ocl_fma(y_tail, H, __spirv_ocl_fma(y_head, T, y_tail * T)); + v = __spirv_ocl_fma(y_head, H, temp); + vt = __spirv_ocl_fma(y_head, H, -v) + temp; + } + + // Now calculate exp of (v,vt) + + double expv; + { + const double max_exp_arg = 709.782712893384; + const double min_exp_arg = -745.1332191019411; + const double sixtyfour_by_lnof2 = 92.33248261689366; + const double lnof2_by_64_head = 0.010830424260348081; + const double lnof2_by_64_tail = -4.359010638708991e-10; + + double temp = v * sixtyfour_by_lnof2; + int n = (int)temp; + double dn = (double)n; + int j = n & 0x0000003f; + int m = n >> 6; + + double2 tv = USE_TABLE(two_to_jby64_ep_tbl, j); + double f1 = tv.s0; + double f2 = tv.s1; + double f = f1 + f2; + + double r1 = __spirv_ocl_fma(dn, -lnof2_by_64_head, v); + double r2 = dn * lnof2_by_64_tail; + double r = (r1 + r2) + vt; + + double q = __spirv_ocl_fma( + r, + __spirv_ocl_fma( + r, + __spirv_ocl_fma(r, + __spirv_ocl_fma(r, 1.38889490863777199667e-03, + 8.33336798434219616221e-03), + 4.16666666662260795726e-02), + 1.66666666665260878863e-01), + 5.00000000000000008883e-01); + q = __spirv_ocl_fma(r * r, q, r); + + expv = __spirv_ocl_fma(f, q, f2) + f1; + expv = __spirv_ocl_ldexp(expv, m); + + expv = v > max_exp_arg ? as_double(0x7FF0000000000000L) : expv; + expv = v < min_exp_arg ? 0.0 : expv; + } + + // See whether y is an integer. + // inty = 0 means not an integer. + // inty = 1 means odd integer. + // inty = 2 means even integer. + + int inty = 2 - (ny & 1); + + expv *= ((inty == 1) & !xpos) ? -1.0 : 1.0; + + long ret = as_long(expv); + + // Now all the edge cases + ret = (!xpos & (inty == 2)) ? QNANBITPATT_DP64 : ret; + long xinf = xpos ? PINFBITPATT_DP64 : NINFBITPATT_DP64; + ret = ((ax == 0L) & !ypos & (inty == 1)) ? xinf : ret; + ret = ((ax == 0L) & !ypos & (inty == 2)) ? PINFBITPATT_DP64 : ret; + ret = ((ax == 0L) & ypos & (inty == 2)) ? 0L : ret; + long xzero = xpos ? 0L : 0x8000000000000000L; + ret = ((ax == 0L) & ypos & (inty == 1)) ? xzero : ret; + ret = + ((ux == NINFBITPATT_DP64) & ypos & (inty == 1)) ? NINFBITPATT_DP64 : ret; + ret = ((ux == NINFBITPATT_DP64) & !ypos & (inty == 1)) ? 0x8000000000000000L + : ret; + ret = ((ux == PINFBITPATT_DP64) & !ypos) ? 0L : ret; + ret = ((ux == PINFBITPATT_DP64) & ypos) ? PINFBITPATT_DP64 : ret; + ret = ax > PINFBITPATT_DP64 ? ux : ret; + ret = ny == 0 ? QNANBITPATT_DP64 : ret; + return as_double(ret); +} +_CLC_BINARY_VECTORIZE(_CLC_DEF _CLC_OVERLOAD, double, __clc_rootn, double, int) +#endif + +#ifdef cl_khr_fp16 +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +_CLC_DEF _CLC_OVERLOAD half __clc_rootn(half x, int ny) { + return __clc_rootn((float)x, ny); +} + +_CLC_BINARY_VECTORIZE(_CLC_DEF _CLC_OVERLOAD, half, __clc_rootn, half, int) +#endif diff --git a/libclc/generic/libspirv/math/clc_sw_binary.inc b/libclc/generic/libspirv/math/clc_sw_binary.inc index f39f5d80010c7..27757db2a338d 100644 --- a/libclc/generic/libspirv/math/clc_sw_binary.inc +++ b/libclc/generic/libspirv/math/clc_sw_binary.inc @@ -1,9 +1,13 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// #include -// TODO: Enable half precision when the sw routine is implemented -#if __CLC_FPSIZE > 16 _CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE __CLC_FUNC(__CLC_GENTYPE x, __CLC_GENTYPE y) { return __CLC_SW_FUNC(x, y); } -#endif diff --git a/libclc/generic/libspirv/math/clc_sw_unary.inc b/libclc/generic/libspirv/math/clc_sw_unary.inc new file mode 100644 index 0000000000000..eebf8f5fc9d9e --- /dev/null +++ b/libclc/generic/libspirv/math/clc_sw_unary.inc @@ -0,0 +1,16 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +#include + +#ifndef __CLC_SW_FUNC +#define __CLC_SW_FUNC __CLC_XCONCAT(__clc_, __CLC_FUNC) +#endif + +_CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE __CLC_FUNC(__CLC_GENTYPE x) { + return __CLC_SW_FUNC(x); +} diff --git a/libclc/generic/libspirv/math/clc_tan.cl b/libclc/generic/libspirv/math/clc_tan.cl index 7d8011bc147f4..2f0c8bea2d6ac 100644 --- a/libclc/generic/libspirv/math/clc_tan.cl +++ b/libclc/generic/libspirv/math/clc_tan.cl @@ -22,9 +22,9 @@ #include #include "sincos_helpers.h" -#include "../../lib/math/math.h" #include "tables.h" -#include "../../lib/clcmacro.h" +#include +#include _CLC_DEF _CLC_OVERLOAD float __clc_tan(float x) { @@ -69,3 +69,12 @@ _CLC_DEF _CLC_OVERLOAD double __clc_tan(double x) } _CLC_UNARY_VECTORIZE(_CLC_DEF _CLC_OVERLOAD, double, __clc_tan, double); #endif + +#ifdef cl_khr_fp16 +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +_CLC_DEF _CLC_OVERLOAD half __clc_tan(half x) { return __clc_tan((float)x); } + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, half, __clc_tan, half) + +#endif diff --git a/libclc/generic/libspirv/math/clc_tanpi.cl b/libclc/generic/libspirv/math/clc_tanpi.cl index fe8f9ebaf7c9b..f6487e7bbd89c 100644 --- a/libclc/generic/libspirv/math/clc_tanpi.cl +++ b/libclc/generic/libspirv/math/clc_tanpi.cl @@ -22,9 +22,9 @@ #include #include "sincos_helpers.h" -#include "../../lib/math/math.h" #include "tables.h" -#include "../../lib/clcmacro.h" +#include +#include _CLC_DEF _CLC_OVERLOAD float __clc_tanpi(float x) { @@ -144,3 +144,14 @@ _CLC_DEF _CLC_OVERLOAD double __clc_tanpi(double x) } _CLC_UNARY_VECTORIZE(_CLC_DEF _CLC_OVERLOAD, double, __clc_tanpi, double); #endif + +#ifdef cl_khr_fp16 +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +_CLC_DEF _CLC_OVERLOAD half __clc_tanpi(half x) { + return __clc_tanpi((float)x); +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, half, __clc_tanpi, half) + +#endif diff --git a/libclc/generic/libspirv/math/cos.cl b/libclc/generic/libspirv/math/cos.cl index bdb3b2bceae33..0a47bf9956af3 100644 --- a/libclc/generic/libspirv/math/cos.cl +++ b/libclc/generic/libspirv/math/cos.cl @@ -9,8 +9,8 @@ #include #include "sincos_helpers.h" -#include "../../lib/math/math.h" -#include "../../lib/clcmacro.h" +#include +#include _CLC_OVERLOAD _CLC_DEF float __spirv_ocl_cos(float x) { @@ -55,7 +55,8 @@ _CLC_OVERLOAD _CLC_DEF double __spirv_ocl_cos(double x) { int2 c = as_int2(regn & 1 ? sc.lo : sc.hi); c.hi ^= (regn > 1) << 31; - return __spirv_IsNan(x) | __spirv_IsInf(x) ? as_double(QNANBITPATT_DP64) : as_double(c); + return __spirv_IsNan(x) || __spirv_IsInf(x) ? as_double(QNANBITPATT_DP64) + : as_double(c); } _CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, double, __spirv_ocl_cos, double); diff --git a/libclc/generic/libspirv/math/cosh.cl b/libclc/generic/libspirv/math/cosh.cl new file mode 100644 index 0000000000000..0c737d091a0cc --- /dev/null +++ b/libclc/generic/libspirv/math/cosh.cl @@ -0,0 +1,211 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include "tables.h" +#include +#include + +_CLC_OVERLOAD _CLC_DEF float __spirv_ocl_cosh(float x) { + + // After dealing with special cases the computation is split into regions as + // follows. abs(x) >= max_cosh_arg: cosh(x) = sign(x)*Inf abs(x) >= + // small_threshold: cosh(x) = sign(x)*exp(abs(x))/2 computed using the + // splitexp and scaleDouble functions as for exp_amd(). + // abs(x) < small_threshold: + // compute p = exp(y) - 1 and then z = 0.5*(p+(p/(p+1.0))) + // cosh(x) is then z. + + const float max_cosh_arg = 0x1.65a9fap+6f; + const float small_threshold = 0x1.0a2b24p+3f; + + uint ux = as_uint(x); + uint aux = ux & EXSIGNBIT_SP32; + float y = as_float(aux); + + // Find the integer part y0 of y and the increment dy = y - y0. We then + // compute z = sinh(y) = sinh(y0)cosh(dy) + cosh(y0)sinh(dy) z = cosh(y) = + // cosh(y0)cosh(dy) + sinh(y0)sinh(dy) where sinh(y0) and cosh(y0) are + // tabulated above. + + int ind = (int)y; + ind = (uint)ind > 36U ? 0 : ind; + + float dy = y - ind; + float dy2 = dy * dy; + + float sdy = __spirv_ocl_mad( + dy2, + __spirv_ocl_mad( + dy2, + __spirv_ocl_mad( + dy2, + __spirv_ocl_mad( + dy2, + __spirv_ocl_mad( + dy2, + __spirv_ocl_mad(dy2, 0.7746188980094184251527126e-12f, + 0.160576793121939886190847e-9f), + 0.250521176994133472333666e-7f), + 0.275573191913636406057211e-5f), + 0.198412698413242405162014e-3f), + 0.833333333333329931873097e-2f), + 0.166666666666666667013899e0f); + sdy = __spirv_ocl_mad(sdy, dy * dy2, dy); + + float cdy = __spirv_ocl_mad( + dy2, + __spirv_ocl_mad( + dy2, + __spirv_ocl_mad( + dy2, + __spirv_ocl_mad( + dy2, + __spirv_ocl_mad( + dy2, + __spirv_ocl_mad(dy2, 0.1163921388172173692062032e-10f, + 0.208744349831471353536305e-8f), + 0.275573350756016588011357e-6f), + 0.248015872460622433115785e-4f), + 0.138888888889814854814536e-2f), + 0.416666666666660876512776e-1f), + 0.500000000000000005911074e0f); + cdy = __spirv_ocl_mad(cdy, dy2, 1.0f); + + float2 tv = USE_TABLE(sinhcosh_tbl, ind); + float z = __spirv_ocl_mad(tv.s0, sdy, tv.s1 * cdy); + + // When exp(-x) is insignificant compared to exp(x), return exp(x)/2 + float t = __spirv_ocl_exp(y - 0x1.62e500p-1f); + float zsmall = __spirv_ocl_mad(0x1.a0210ep-18f, t, t); + z = y >= small_threshold ? zsmall : z; + + // Corner cases + z = y >= max_cosh_arg ? as_float(PINFBITPATT_SP32) : z; + z = aux > PINFBITPATT_SP32 ? as_float(QNANBITPATT_SP32) : z; + z = aux < 0x38800000 ? 1.0f : z; + + return z; +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, float, __spirv_ocl_cosh, float); + +#ifdef cl_khr_fp64 +#pragma OPENCL EXTENSION cl_khr_fp64 : enable + +_CLC_OVERLOAD _CLC_DEF double __spirv_ocl_cosh(double x) { + + // After dealing with special cases the computation is split into + // regions as follows: + // + // abs(x) >= max_cosh_arg: + // cosh(x) = sign(x)*Inf + // + // abs(x) >= small_threshold: + // cosh(x) = sign(x)*exp(abs(x))/2 computed using the + // splitexp and scaleDouble functions as for exp_amd(). + // + // abs(x) < small_threshold: + // compute p = exp(y) - 1 and then z = 0.5*(p+(p/(p+1.0))) + // cosh(x) is then sign(x)*z. + + // This is ln(2^1025) + const double max_cosh_arg = 7.10475860073943977113e+02; // 0x408633ce8fb9f87e + + // This is where exp(-x) is insignificant compared to exp(x) = ln(2^27) + const double small_threshold = 0x1.2b708872320e2p+4; + + double y = __spirv_ocl_fabs(x); + + // In this range we find the integer part y0 of y + // and the increment dy = y - y0. We then compute + // z = cosh(y) = cosh(y0)cosh(dy) + sinh(y0)sinh(dy) + // where sinh(y0) and cosh(y0) are tabulated above. + + int ind = __spirv_ocl_s_min((int)y, 36); + double dy = y - ind; + double dy2 = dy * dy; + + double sdy = + dy * dy2 * + __spirv_ocl_fma( + dy2, + __spirv_ocl_fma( + dy2, + __spirv_ocl_fma( + dy2, + __spirv_ocl_fma( + dy2, + __spirv_ocl_fma( + dy2, + __spirv_ocl_fma(dy2, 0.7746188980094184251527126e-12, + 0.160576793121939886190847e-9), + 0.250521176994133472333666e-7), + 0.275573191913636406057211e-5), + 0.198412698413242405162014e-3), + 0.833333333333329931873097e-2), + 0.166666666666666667013899e0); + + double cdy = + dy2 * + __spirv_ocl_fma( + dy2, + __spirv_ocl_fma( + dy2, + __spirv_ocl_fma( + dy2, + __spirv_ocl_fma( + dy2, + __spirv_ocl_fma( + dy2, + __spirv_ocl_fma(dy2, 0.1163921388172173692062032e-10, + 0.208744349831471353536305e-8), + 0.275573350756016588011357e-6), + 0.248015872460622433115785e-4), + 0.138888888889814854814536e-2), + 0.416666666666660876512776e-1), + 0.500000000000000005911074e0); + + // At this point sinh(dy) is approximated by dy + sdy, + // and cosh(dy) is approximated by 1 + cdy. + double2 tv = USE_TABLE(cosh_tbl, ind); + double cl = tv.s0; + double ct = tv.s1; + tv = USE_TABLE(sinh_tbl, ind); + double sl = tv.s0; + double st = tv.s1; + + double z = + __spirv_ocl_fma( + sl, dy, + __spirv_ocl_fma( + sl, sdy, + __spirv_ocl_fma( + cl, cdy, + __spirv_ocl_fma(st, dy, __spirv_ocl_fma(st, sdy, ct * cdy)) + + ct))) + + cl; + + // Other cases + z = y < 0x1.0p-28 ? 1.0 : z; + + double t = __spirv_ocl_exp(y - 0x1.62e42fefa3800p-1); + t = __spirv_ocl_fma(t, -0x1.ef35793c76641p-45, t); + z = y >= small_threshold ? t : z; + + z = y >= max_cosh_arg ? as_double(PINFBITPATT_DP64) : z; + + z = __spirv_IsInf(x) || __spirv_IsNan(x) ? y : z; + + return z; +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, double, __spirv_ocl_cosh, double) + +#endif diff --git a/libclc/generic/libspirv/math/cospi.cl b/libclc/generic/libspirv/math/cospi.cl index 50d5da82d4fbb..ec02fee7daae7 100644 --- a/libclc/generic/libspirv/math/cospi.cl +++ b/libclc/generic/libspirv/math/cospi.cl @@ -8,10 +8,10 @@ #include -#include "../../lib/math/math.h" -#include "../../lib/clcmacro.h" #include "sincos_helpers.h" #include "sincospiF_piby4.h" +#include +#include #ifdef cl_khr_fp64 #include "sincosD_piby4.h" #endif diff --git a/libclc/generic/libspirv/math/ep_log.cl b/libclc/generic/libspirv/math/ep_log.cl new file mode 100644 index 0000000000000..e91a971a648b5 --- /dev/null +++ b/libclc/generic/libspirv/math/ep_log.cl @@ -0,0 +1,81 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifdef cl_khr_fp64 + +#include + +#include "ep_log.h" +#include "tables.h" +#include + +#pragma OPENCL EXTENSION cl_khr_fp64 : enable + +#define LN0 8.33333333333317923934e-02 +#define LN1 1.25000000037717509602e-02 +#define LN2 2.23213998791944806202e-03 +#define LN3 4.34887777707614552256e-04 + +#define LF0 8.33333333333333593622e-02 +#define LF1 1.24999999978138668903e-02 +#define LF2 2.23219810758559851206e-03 + +_CLC_DEF void __clc_ep_log(double x, int *xexp, double *r1, double *r2) { + // Computes natural log(x). Algorithm based on: + // Ping-Tak Peter Tang + // "Table-driven implementation of the logarithm function in IEEE + // floating-point arithmetic" + // ACM Transactions on Mathematical Software (TOMS) + // Volume 16, Issue 4 (December 1990) + int near_one = x >= 0x1.e0faap-1 & x <= 0x1.1082cp+0; + + ulong ux = as_ulong(x); + ulong uxs = as_ulong(as_double(0x03d0000000000000UL | ux) - 0x1.0p-962); + int c = ux < IMPBIT_DP64; + ux = c ? uxs : ux; + int expadjust = c ? 60 : 0; + + // Store the exponent of x in xexp and put f into the range [0.5,1) + int xexp1 = ((as_int2(ux).hi >> 20) & 0x7ff) - EXPBIAS_DP64 - expadjust; + double f = as_double(HALFEXPBITS_DP64 | (ux & MANTBITS_DP64)); + *xexp = near_one ? 0 : xexp1; + + double r = x - 1.0; + double u1 = MATH_DIVIDE(r, 2.0 + r); + double ru1 = -r * u1; + u1 = u1 + u1; + + int index = as_int2(ux).hi >> 13; + index = ((0x80 | (index & 0x7e)) >> 1) + (index & 0x1); + + double f1 = index * 0x1.0p-7; + double f2 = f - f1; + double u2 = MATH_DIVIDE(f2, __spirv_ocl_fma(0.5, f2, f1)); + + double2 tv = USE_TABLE(ln_tbl, (index - 64)); + double z1 = tv.s0; + double q = tv.s1; + + z1 = near_one ? r : z1; + q = near_one ? 0.0 : q; + double u = near_one ? u1 : u2; + double v = u * u; + + double cc = near_one ? ru1 : u2; + + double z21 = __spirv_ocl_fma( + v, __spirv_ocl_fma(v, __spirv_ocl_fma(v, LN3, LN2), LN1), LN0); + double z22 = __spirv_ocl_fma(v, __spirv_ocl_fma(v, LF2, LF1), LF0); + double z2 = near_one ? z21 : z22; + z2 = __spirv_ocl_fma(u * v, z2, cc) + q; + + *r1 = z1; + *r2 = z2; +} + +#endif diff --git a/libclc/generic/libspirv/math/ep_log.h b/libclc/generic/libspirv/math/ep_log.h new file mode 100644 index 0000000000000..f5eee58e86445 --- /dev/null +++ b/libclc/generic/libspirv/math/ep_log.h @@ -0,0 +1,15 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifdef cl_khr_fp64 + +#pragma OPENCL EXTENSION cl_khr_fp64 : enable + +_CLC_DECL void __clc_ep_log(double x, int *xexp, double *r1, double *r2); + +#endif diff --git a/libclc/generic/libspirv/math/erf.cl b/libclc/generic/libspirv/math/erf.cl new file mode 100644 index 0000000000000..f50358917caa3 --- /dev/null +++ b/libclc/generic/libspirv/math/erf.cl @@ -0,0 +1,542 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include +#include + +/* + * ==================================================== + * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved. + * + * Developed at SunPro, a Sun Microsystems, Inc. business. + * Permission to use, copy, modify, and distribute this + * software is freely granted, provided that this notice + * is preserved. + * ==================================================== + */ + +#define erx 8.4506291151e-01f /* 0x3f58560b */ + +// Coefficients for approximation to erf on [00.84375] + +#define efx 1.2837916613e-01f /* 0x3e0375d4 */ +#define efx8 1.0270333290e+00f /* 0x3f8375d4 */ + +#define pp0 1.2837916613e-01f /* 0x3e0375d4 */ +#define pp1 -3.2504209876e-01f /* 0xbea66beb */ +#define pp2 -2.8481749818e-02f /* 0xbce9528f */ +#define pp3 -5.7702702470e-03f /* 0xbbbd1489 */ +#define pp4 -2.3763017452e-05f /* 0xb7c756b1 */ +#define qq1 3.9791721106e-01f /* 0x3ecbbbce */ +#define qq2 6.5022252500e-02f /* 0x3d852a63 */ +#define qq3 5.0813062117e-03f /* 0x3ba68116 */ +#define qq4 1.3249473704e-04f /* 0x390aee49 */ +#define qq5 -3.9602282413e-06f /* 0xb684e21a */ + +// Coefficients for approximation to erf in [0.843751.25] + +#define pa0 -2.3621185683e-03f /* 0xbb1acdc6 */ +#define pa1 4.1485610604e-01f /* 0x3ed46805 */ +#define pa2 -3.7220788002e-01f /* 0xbebe9208 */ +#define pa3 3.1834661961e-01f /* 0x3ea2fe54 */ +#define pa4 -1.1089469492e-01f /* 0xbde31cc2 */ +#define pa5 3.5478305072e-02f /* 0x3d1151b3 */ +#define pa6 -2.1663755178e-03f /* 0xbb0df9c0 */ +#define qa1 1.0642088205e-01f /* 0x3dd9f331 */ +#define qa2 5.4039794207e-01f /* 0x3f0a5785 */ +#define qa3 7.1828655899e-02f /* 0x3d931ae7 */ +#define qa4 1.2617121637e-01f /* 0x3e013307 */ +#define qa5 1.3637083583e-02f /* 0x3c5f6e13 */ +#define qa6 1.1984500103e-02f /* 0x3c445aa3 */ + +// Coefficients for approximation to erfc in [1.251/0.35] + +#define ra0 -9.8649440333e-03f /* 0xbc21a093 */ +#define ra1 -6.9385856390e-01f /* 0xbf31a0b7 */ +#define ra2 -1.0558626175e+01f /* 0xc128f022 */ +#define ra3 -6.2375331879e+01f /* 0xc2798057 */ +#define ra4 -1.6239666748e+02f /* 0xc322658c */ +#define ra5 -1.8460508728e+02f /* 0xc3389ae7 */ +#define ra6 -8.1287437439e+01f /* 0xc2a2932b */ +#define ra7 -9.8143291473e+00f /* 0xc11d077e */ +#define sa1 1.9651271820e+01f /* 0x419d35ce */ +#define sa2 1.3765776062e+02f /* 0x4309a863 */ +#define sa3 4.3456588745e+02f /* 0x43d9486f */ +#define sa4 6.4538726807e+02f /* 0x442158c9 */ +#define sa5 4.2900814819e+02f /* 0x43d6810b */ +#define sa6 1.0863500214e+02f /* 0x42d9451f */ +#define sa7 6.5702495575e+00f /* 0x40d23f7c */ +#define sa8 -6.0424413532e-02f /* 0xbd777f97 */ + +// Coefficients for approximation to erfc in [1/.3528] + +#define rb0 -9.8649431020e-03f /* 0xbc21a092 */ +#define rb1 -7.9928326607e-01f /* 0xbf4c9dd4 */ +#define rb2 -1.7757955551e+01f /* 0xc18e104b */ +#define rb3 -1.6063638306e+02f /* 0xc320a2ea */ +#define rb4 -6.3756646729e+02f /* 0xc41f6441 */ +#define rb5 -1.0250950928e+03f /* 0xc480230b */ +#define rb6 -4.8351919556e+02f /* 0xc3f1c275 */ +#define sb1 3.0338060379e+01f /* 0x41f2b459 */ +#define sb2 3.2579251099e+02f /* 0x43a2e571 */ +#define sb3 1.5367296143e+03f /* 0x44c01759 */ +#define sb4 3.1998581543e+03f /* 0x4547fdbb */ +#define sb5 2.5530502930e+03f /* 0x451f90ce */ +#define sb6 4.7452853394e+02f /* 0x43ed43a7 */ +#define sb7 -2.2440952301e+01f /* 0xc1b38712 */ + +_CLC_OVERLOAD _CLC_DEF float __spirv_ocl_erf(float x) { + int hx = as_uint(x); + int ix = hx & 0x7fffffff; + float absx = as_float(ix); + + float x2 = absx * absx; + float t = 1.0f / x2; + float tt = absx - 1.0f; + t = absx < 1.25f ? tt : t; + t = absx < 0.84375f ? x2 : t; + + float u, v, tu, tv; + + // |x| < 6 + u = __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, __spirv_ocl_mad(t, __spirv_ocl_mad(t, rb6, rb5), rb4), + rb3), + rb2), + rb1), + rb0); + v = __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, __spirv_ocl_mad(t, __spirv_ocl_mad(t, sb7, sb6), sb5), + sb4), + sb3), + sb2), + sb1); + + tu = __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, __spirv_ocl_mad(t, __spirv_ocl_mad(t, ra7, ra6), ra5), + ra4), + ra3), + ra2), + ra1), + ra0); + tv = __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, __spirv_ocl_mad(t, __spirv_ocl_mad(t, sa8, sa7), sa6), + sa5), + sa4), + sa3), + sa2), + sa1); + u = absx < 0x1.6db6dcp+1f ? tu : u; + v = absx < 0x1.6db6dcp+1f ? tv : v; + + tu = __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, __spirv_ocl_mad(t, __spirv_ocl_mad(t, pa6, pa5), pa4), + pa3), + pa2), + pa1), + pa0); + tv = __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, __spirv_ocl_mad(t, __spirv_ocl_mad(t, qa6, qa5), qa4), qa3), + qa2), + qa1); + u = absx < 1.25f ? tu : u; + v = absx < 1.25f ? tv : v; + + tu = __spirv_ocl_mad( + t, + __spirv_ocl_mad(t, __spirv_ocl_mad(t, __spirv_ocl_mad(t, pp4, pp3), pp2), + pp1), + pp0); + tv = __spirv_ocl_mad( + t, + __spirv_ocl_mad(t, __spirv_ocl_mad(t, __spirv_ocl_mad(t, qq5, qq4), qq3), + qq2), + qq1); + u = absx < 0.84375f ? tu : u; + v = absx < 0.84375f ? tv : v; + + v = __spirv_ocl_mad(t, v, 1.0f); + float q = MATH_DIVIDE(u, v); + + float ret = 1.0f; + + // |x| < 6 + float z = as_float(ix & 0xfffff000); + float r = __spirv_ocl_exp(__spirv_ocl_mad(-z, z, -0.5625f)) * + __spirv_ocl_exp(__spirv_ocl_mad(z - absx, z + absx, q)); + r = 1.0f - MATH_DIVIDE(r, absx); + ret = absx < 6.0f ? r : ret; + + r = erx + q; + ret = absx < 1.25f ? r : ret; + + ret = as_float((hx & 0x80000000) | as_int(ret)); + + r = __spirv_ocl_mad(x, q, x); + ret = absx < 0.84375f ? r : ret; + + // Prevent underflow + r = 0.125f * __spirv_ocl_mad(8.0f, x, efx8 * x); + ret = absx < 0x1.0p-28f ? r : ret; + + ret = __spirv_IsNan(x) ? x : ret; + + return ret; +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, float, __spirv_ocl_erf, float); + +#ifdef cl_khr_fp64 + +#pragma OPENCL EXTENSION cl_khr_fp64 : enable + +/* + * ==================================================== + * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved. + * + * Developed at SunPro, a Sun Microsystems, Inc. business. + * Permission to use, copy, modify, and distribute this + * software is freely granted, provided that this notice + * is preserved. + * ==================================================== + */ + +/* double erf(double x) + * double erfc(double x) + * x + * 2 |\ + * erf(x) = --------- | exp(-t*t)dt + * sqrt(pi) \| + * 0 + * + * erfc(x) = 1-erf(x) + * Note that + * erf(-x) = -erf(x) + * erfc(-x) = 2 - erfc(x) + * + * Method: + * 1. For |x| in [0, 0.84375] + * erf(x) = x + x*R(x^2) + * erfc(x) = 1 - erf(x) if x in [-.84375,0.25] + * = 0.5 + ((0.5-x)-x*R) if x in [0.25,0.84375] + * where R = P/Q where P is an odd poly of degree 8 and + * Q is an odd poly of degree 10. + * -57.90 + * | R - (erf(x)-x)/x | <= 2 + * + * + * Remark. The formula is derived by noting + * erf(x) = (2/sqrt(pi))*(x - x^3/3 + x^5/10 - x^7/42 + ....) + * and that + * 2/sqrt(pi) = 1.128379167095512573896158903121545171688 + * is close to one. The interval is chosen because the fix + * point of erf(x) is near 0.6174 (i.e., erf(x)=x when x is + * near 0.6174), and by some experiment, 0.84375 is chosen to + * guarantee the error is less than one ulp for erf. + * + * 2. For |x| in [0.84375,1.25], let s = |x| - 1, and + * c = 0.84506291151 rounded to single (24 bits) + * erf(x) = sign(x) * (c + P1(s)/Q1(s)) + * erfc(x) = (1-c) - P1(s)/Q1(s) if x > 0 + * 1+(c+P1(s)/Q1(s)) if x < 0 + * |P1/Q1 - (erf(|x|)-c)| <= 2**-59.06 + * Remark: here we use the taylor series expansion at x=1. + * erf(1+s) = erf(1) + s*Poly(s) + * = 0.845.. + P1(s)/Q1(s) + * That is, we use rational approximation to approximate + * erf(1+s) - (c = (single)0.84506291151) + * Note that |P1/Q1|< 0.078 for x in [0.84375,1.25] + * where + * P1(s) = degree 6 poly in s + * Q1(s) = degree 6 poly in s + * + * 3. For x in [1.25,1/0.35(~2.857143)], + * erfc(x) = (1/x)*exp(-x*x-0.5625+R1/S1) + * erf(x) = 1 - erfc(x) + * where + * R1(z) = degree 7 poly in z, (z=1/x^2) + * S1(z) = degree 8 poly in z + * + * 4. For x in [1/0.35,28] + * erfc(x) = (1/x)*exp(-x*x-0.5625+R2/S2) if x > 0 + * = 2.0 - (1/x)*exp(-x*x-0.5625+R2/S2) if -6 x >= 28 + * erf(x) = sign(x) *(1 - tiny) (raise inexact) + * erfc(x) = tiny*tiny (raise underflow) if x > 0 + * = 2 - tiny if x<0 + * + * 7. Special case: + * erf(0) = 0, erf(inf) = 1, erf(-inf) = -1, + * erfc(0) = 1, erfc(inf) = 0, erfc(-inf) = 2, + * erfc/erf(NaN) is NaN + */ + +#define AU0 -9.86494292470009928597e-03 +#define AU1 -7.99283237680523006574e-01 +#define AU2 -1.77579549177547519889e+01 +#define AU3 -1.60636384855821916062e+02 +#define AU4 -6.37566443368389627722e+02 +#define AU5 -1.02509513161107724954e+03 +#define AU6 -4.83519191608651397019e+02 + +#define AV1 3.03380607434824582924e+01 +#define AV2 3.25792512996573918826e+02 +#define AV3 1.53672958608443695994e+03 +#define AV4 3.19985821950859553908e+03 +#define AV5 2.55305040643316442583e+03 +#define AV6 4.74528541206955367215e+02 +#define AV7 -2.24409524465858183362e+01 + +#define BU0 -9.86494403484714822705e-03 +#define BU1 -6.93858572707181764372e-01 +#define BU2 -1.05586262253232909814e+01 +#define BU3 -6.23753324503260060396e+01 +#define BU4 -1.62396669462573470355e+02 +#define BU5 -1.84605092906711035994e+02 +#define BU6 -8.12874355063065934246e+01 +#define BU7 -9.81432934416914548592e+00 + +#define BV1 1.96512716674392571292e+01 +#define BV2 1.37657754143519042600e+02 +#define BV3 4.34565877475229228821e+02 +#define BV4 6.45387271733267880336e+02 +#define BV5 4.29008140027567833386e+02 +#define BV6 1.08635005541779435134e+02 +#define BV7 6.57024977031928170135e+00 +#define BV8 -6.04244152148580987438e-02 + +#define CU0 -2.36211856075265944077e-03 +#define CU1 4.14856118683748331666e-01 +#define CU2 -3.72207876035701323847e-01 +#define CU3 3.18346619901161753674e-01 +#define CU4 -1.10894694282396677476e-01 +#define CU5 3.54783043256182359371e-02 +#define CU6 -2.16637559486879084300e-03 + +#define CV1 1.06420880400844228286e-01 +#define CV2 5.40397917702171048937e-01 +#define CV3 7.18286544141962662868e-02 +#define CV4 1.26171219808761642112e-01 +#define CV5 1.36370839120290507362e-02 +#define CV6 1.19844998467991074170e-02 + +#define DU0 1.28379167095512558561e-01 +#define DU1 -3.25042107247001499370e-01 +#define DU2 -2.84817495755985104766e-02 +#define DU3 -5.77027029648944159157e-03 +#define DU4 -2.37630166566501626084e-05 + +#define DV1 3.97917223959155352819e-01 +#define DV2 6.50222499887672944485e-02 +#define DV3 5.08130628187576562776e-03 +#define DV4 1.32494738004321644526e-04 +#define DV5 -3.96022827877536812320e-06 + +_CLC_OVERLOAD _CLC_DEF double __spirv_ocl_erf(double y) { + double x = __spirv_ocl_fabs(y); + double x2 = x * x; + double xm1 = x - 1.0; + + // Poly variable + double t = 1.0 / x2; + t = x < 1.25 ? xm1 : t; + t = x < 0.84375 ? x2 : t; + + double u, ut, v, vt; + + // Evaluate rational poly + // XXX We need to see of we can grab 16 coefficents from a table + // faster than evaluating 3 of the poly pairs + // if (x < 6.0) + u = __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, __spirv_ocl_fma(t, __spirv_ocl_fma(t, AU6, AU5), AU4), + AU3), + AU2), + AU1), + AU0); + v = __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, __spirv_ocl_fma(t, __spirv_ocl_fma(t, AV7, AV6), AV5), + AV4), + AV3), + AV2), + AV1); + + ut = __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, __spirv_ocl_fma(t, __spirv_ocl_fma(t, BU7, BU6), BU5), + BU4), + BU3), + BU2), + BU1), + BU0); + vt = __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, __spirv_ocl_fma(t, __spirv_ocl_fma(t, BV8, BV7), BV6), + BV5), + BV4), + BV3), + BV2), + BV1); + u = x < 0x1.6db6ep+1 ? ut : u; + v = x < 0x1.6db6ep+1 ? vt : v; + + ut = __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, __spirv_ocl_fma(t, __spirv_ocl_fma(t, CU6, CU5), CU4), + CU3), + CU2), + CU1), + CU0); + vt = __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, __spirv_ocl_fma(t, __spirv_ocl_fma(t, CV6, CV5), CV4), CV3), + CV2), + CV1); + u = x < 1.25 ? ut : u; + v = x < 1.25 ? vt : v; + + ut = __spirv_ocl_fma( + t, + __spirv_ocl_fma(t, __spirv_ocl_fma(t, __spirv_ocl_fma(t, DU4, DU3), DU2), + DU1), + DU0); + vt = __spirv_ocl_fma( + t, + __spirv_ocl_fma(t, __spirv_ocl_fma(t, __spirv_ocl_fma(t, DV5, DV4), DV3), + DV2), + DV1); + u = x < 0.84375 ? ut : u; + v = x < 0.84375 ? vt : v; + + v = __spirv_ocl_fma(t, v, 1.0); + + // Compute rational approximation + double q = u / v; + + // Compute results + double z = as_double(as_long(x) & 0xffffffff00000000L); + double r = + __spirv_ocl_exp(-z * z - 0.5625) * __spirv_ocl_exp((z - x) * (z + x) + q); + r = 1.0 - r / x; + + double ret = x < 6.0 ? r : 1.0; + + r = 8.45062911510467529297e-01 + q; + ret = x < 1.25 ? r : ret; + + q = x < 0x1.0p-28 ? 1.28379167095512586316e-01 : q; + + r = __spirv_ocl_fma(x, q, x); + ret = x < 0.84375 ? r : ret; + + ret = __spirv_IsNan(x) ? x : ret; + + return y < 0.0 ? -ret : ret; +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, double, __spirv_ocl_erf, double); + +#endif diff --git a/libclc/generic/libspirv/math/erfc.cl b/libclc/generic/libspirv/math/erfc.cl new file mode 100644 index 0000000000000..9f5db45f5aa50 --- /dev/null +++ b/libclc/generic/libspirv/math/erfc.cl @@ -0,0 +1,551 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include +#include + +/* + * ==================================================== + * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved. + * + * Developed at SunPro, a Sun Microsystems, Inc. business. + * Permission to use, copy, modify, and distribute this + * software is freely granted, provided that this notice + * is preserved. + * ==================================================== + */ + +#define erx_f 8.4506291151e-01f /* 0x3f58560b */ + +// Coefficients for approximation to erf on [00.84375] + +#define efx 1.2837916613e-01f /* 0x3e0375d4 */ +#define efx8 1.0270333290e+00f /* 0x3f8375d4 */ + +#define pp0 1.2837916613e-01f /* 0x3e0375d4 */ +#define pp1 -3.2504209876e-01f /* 0xbea66beb */ +#define pp2 -2.8481749818e-02f /* 0xbce9528f */ +#define pp3 -5.7702702470e-03f /* 0xbbbd1489 */ +#define pp4 -2.3763017452e-05f /* 0xb7c756b1 */ +#define qq1 3.9791721106e-01f /* 0x3ecbbbce */ +#define qq2 6.5022252500e-02f /* 0x3d852a63 */ +#define qq3 5.0813062117e-03f /* 0x3ba68116 */ +#define qq4 1.3249473704e-04f /* 0x390aee49 */ +#define qq5 -3.9602282413e-06f /* 0xb684e21a */ + +// Coefficients for approximation to erf in [0.843751.25] + +#define pa0 -2.3621185683e-03f /* 0xbb1acdc6 */ +#define pa1 4.1485610604e-01f /* 0x3ed46805 */ +#define pa2 -3.7220788002e-01f /* 0xbebe9208 */ +#define pa3 3.1834661961e-01f /* 0x3ea2fe54 */ +#define pa4 -1.1089469492e-01f /* 0xbde31cc2 */ +#define pa5 3.5478305072e-02f /* 0x3d1151b3 */ +#define pa6 -2.1663755178e-03f /* 0xbb0df9c0 */ +#define qa1 1.0642088205e-01f /* 0x3dd9f331 */ +#define qa2 5.4039794207e-01f /* 0x3f0a5785 */ +#define qa3 7.1828655899e-02f /* 0x3d931ae7 */ +#define qa4 1.2617121637e-01f /* 0x3e013307 */ +#define qa5 1.3637083583e-02f /* 0x3c5f6e13 */ +#define qa6 1.1984500103e-02f /* 0x3c445aa3 */ + +// Coefficients for approximation to erfc in [1.251/0.35] + +#define ra0 -9.8649440333e-03f /* 0xbc21a093 */ +#define ra1 -6.9385856390e-01f /* 0xbf31a0b7 */ +#define ra2 -1.0558626175e+01f /* 0xc128f022 */ +#define ra3 -6.2375331879e+01f /* 0xc2798057 */ +#define ra4 -1.6239666748e+02f /* 0xc322658c */ +#define ra5 -1.8460508728e+02f /* 0xc3389ae7 */ +#define ra6 -8.1287437439e+01f /* 0xc2a2932b */ +#define ra7 -9.8143291473e+00f /* 0xc11d077e */ +#define sa1 1.9651271820e+01f /* 0x419d35ce */ +#define sa2 1.3765776062e+02f /* 0x4309a863 */ +#define sa3 4.3456588745e+02f /* 0x43d9486f */ +#define sa4 6.4538726807e+02f /* 0x442158c9 */ +#define sa5 4.2900814819e+02f /* 0x43d6810b */ +#define sa6 1.0863500214e+02f /* 0x42d9451f */ +#define sa7 6.5702495575e+00f /* 0x40d23f7c */ +#define sa8 -6.0424413532e-02f /* 0xbd777f97 */ + +// Coefficients for approximation to erfc in [1/.3528] + +#define rb0 -9.8649431020e-03f /* 0xbc21a092 */ +#define rb1 -7.9928326607e-01f /* 0xbf4c9dd4 */ +#define rb2 -1.7757955551e+01f /* 0xc18e104b */ +#define rb3 -1.6063638306e+02f /* 0xc320a2ea */ +#define rb4 -6.3756646729e+02f /* 0xc41f6441 */ +#define rb5 -1.0250950928e+03f /* 0xc480230b */ +#define rb6 -4.8351919556e+02f /* 0xc3f1c275 */ +#define sb1 3.0338060379e+01f /* 0x41f2b459 */ +#define sb2 3.2579251099e+02f /* 0x43a2e571 */ +#define sb3 1.5367296143e+03f /* 0x44c01759 */ +#define sb4 3.1998581543e+03f /* 0x4547fdbb */ +#define sb5 2.5530502930e+03f /* 0x451f90ce */ +#define sb6 4.7452853394e+02f /* 0x43ed43a7 */ +#define sb7 -2.2440952301e+01f /* 0xc1b38712 */ + +_CLC_OVERLOAD _CLC_DEF float __spirv_ocl_erfc(float x) { + int hx = as_int(x); + int ix = hx & 0x7fffffff; + float absx = as_float(ix); + + // Argument for polys + float x2 = absx * absx; + float t = 1.0f / x2; + float tt = absx - 1.0f; + t = absx < 1.25f ? tt : t; + t = absx < 0.84375f ? x2 : t; + + // Evaluate polys + float tu, tv, u, v; + + u = __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, __spirv_ocl_mad(t, __spirv_ocl_mad(t, rb6, rb5), rb4), + rb3), + rb2), + rb1), + rb0); + v = __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, __spirv_ocl_mad(t, __spirv_ocl_mad(t, sb7, sb6), sb5), + sb4), + sb3), + sb2), + sb1); + + tu = __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, __spirv_ocl_mad(t, __spirv_ocl_mad(t, ra7, ra6), ra5), + ra4), + ra3), + ra2), + ra1), + ra0); + tv = __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, __spirv_ocl_mad(t, __spirv_ocl_mad(t, sa8, sa7), sa6), + sa5), + sa4), + sa3), + sa2), + sa1); + u = absx < 0x1.6db6dap+1f ? tu : u; + v = absx < 0x1.6db6dap+1f ? tv : v; + + tu = __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, __spirv_ocl_mad(t, __spirv_ocl_mad(t, pa6, pa5), pa4), + pa3), + pa2), + pa1), + pa0); + tv = __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, + __spirv_ocl_mad( + t, __spirv_ocl_mad(t, __spirv_ocl_mad(t, qa6, qa5), qa4), qa3), + qa2), + qa1); + u = absx < 1.25f ? tu : u; + v = absx < 1.25f ? tv : v; + + tu = __spirv_ocl_mad( + t, + __spirv_ocl_mad(t, __spirv_ocl_mad(t, __spirv_ocl_mad(t, pp4, pp3), pp2), + pp1), + pp0); + tv = __spirv_ocl_mad( + t, + __spirv_ocl_mad(t, __spirv_ocl_mad(t, __spirv_ocl_mad(t, qq5, qq4), qq3), + qq2), + qq1); + u = absx < 0.84375f ? tu : u; + v = absx < 0.84375f ? tv : v; + + v = __spirv_ocl_mad(t, v, 1.0f); + + float q = MATH_DIVIDE(u, v); + + float ret = 0.0f; + + float z = as_float(ix & 0xfffff000); + float r = __spirv_ocl_exp(__spirv_ocl_mad(-z, z, -0.5625f)) * + __spirv_ocl_exp(__spirv_ocl_mad(z - absx, z + absx, q)); + r = MATH_DIVIDE(r, absx); + t = 2.0f - r; + r = x < 0.0f ? t : r; + ret = absx < 28.0f ? r : ret; + + r = 1.0f - erx_f - q; + t = erx_f + q + 1.0f; + r = x < 0.0f ? t : r; + ret = absx < 1.25f ? r : ret; + + r = 0.5f - __spirv_ocl_mad(x, q, x - 0.5f); + ret = absx < 0.84375f ? r : ret; + + ret = x < -6.0f ? 2.0f : ret; + + ret = __spirv_IsNan(x) ? x : ret; + + return ret; +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, float, __spirv_ocl_erfc, float); + +#ifdef cl_khr_fp64 + +#pragma OPENCL EXTENSION cl_khr_fp64 : enable + +/* + * ==================================================== + * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved. + * + * Developed at SunPro, a Sun Microsystems, Inc. business. + * Permission to use, copy, modify, and distribute this + * software is freely granted, provided that this notice + * is preserved. + * ==================================================== + */ + +/* double erf(double x) + * double erfc(double x) + * x + * 2 |\ + * erf(x) = --------- | exp(-t*t)dt + * sqrt(pi) \| + * 0 + * + * erfc(x) = 1-erf(x) + * Note that + * erf(-x) = -erf(x) + * erfc(-x) = 2 - erfc(x) + * + * Method: + * 1. For |x| in [0, 0.84375] + * erf(x) = x + x*R(x^2) + * erfc(x) = 1 - erf(x) if x in [-.84375,0.25] + * = 0.5 + ((0.5-x)-x*R) if x in [0.25,0.84375] + * where R = P/Q where P is an odd poly of degree 8 and + * Q is an odd poly of degree 10. + * -57.90 + * | R - (erf(x)-x)/x | <= 2 + * + * + * Remark. The formula is derived by noting + * erf(x) = (2/sqrt(pi))*(x - x^3/3 + x^5/10 - x^7/42 + ....) + * and that + * 2/sqrt(pi) = 1.128379167095512573896158903121545171688 + * is close to one. The interval is chosen because the fix + * point of erf(x) is near 0.6174 (i.e., erf(x)=x when x is + * near 0.6174), and by some experiment, 0.84375 is chosen to + * guarantee the error is less than one ulp for erf. + * + * 2. For |x| in [0.84375,1.25], let s = |x| - 1, and + * c = 0.84506291151 rounded to single (24 bits) + * erf(x) = sign(x) * (c + P1(s)/Q1(s)) + * erfc(x) = (1-c) - P1(s)/Q1(s) if x > 0 + * 1+(c+P1(s)/Q1(s)) if x < 0 + * |P1/Q1 - (erf(|x|)-c)| <= 2**-59.06 + * Remark: here we use the taylor series expansion at x=1. + * erf(1+s) = erf(1) + s*Poly(s) + * = 0.845.. + P1(s)/Q1(s) + * That is, we use rational approximation to approximate + * erf(1+s) - (c = (single)0.84506291151) + * Note that |P1/Q1|< 0.078 for x in [0.84375,1.25] + * where + * P1(s) = degree 6 poly in s + * Q1(s) = degree 6 poly in s + * + * 3. For x in [1.25,1/0.35(~2.857143)], + * erfc(x) = (1/x)*exp(-x*x-0.5625+R1/S1) + * erf(x) = 1 - erfc(x) + * where + * R1(z) = degree 7 poly in z, (z=1/x^2) + * S1(z) = degree 8 poly in z + * + * 4. For x in [1/0.35,28] + * erfc(x) = (1/x)*exp(-x*x-0.5625+R2/S2) if x > 0 + * = 2.0 - (1/x)*exp(-x*x-0.5625+R2/S2) if -6 x >= 28 + * erf(x) = sign(x) *(1 - tiny) (raise inexact) + * erfc(x) = tiny*tiny (raise underflow) if x > 0 + * = 2 - tiny if x<0 + * + * 7. Special case: + * erf(0) = 0, erf(inf) = 1, erf(-inf) = -1, + * erfc(0) = 1, erfc(inf) = 0, erfc(-inf) = 2, + * erfc/erf(NaN) is NaN + */ + +#define AU0 -9.86494292470009928597e-03 +#define AU1 -7.99283237680523006574e-01 +#define AU2 -1.77579549177547519889e+01 +#define AU3 -1.60636384855821916062e+02 +#define AU4 -6.37566443368389627722e+02 +#define AU5 -1.02509513161107724954e+03 +#define AU6 -4.83519191608651397019e+02 + +#define AV0 3.03380607434824582924e+01 +#define AV1 3.25792512996573918826e+02 +#define AV2 1.53672958608443695994e+03 +#define AV3 3.19985821950859553908e+03 +#define AV4 2.55305040643316442583e+03 +#define AV5 4.74528541206955367215e+02 +#define AV6 -2.24409524465858183362e+01 + +#define BU0 -9.86494403484714822705e-03 +#define BU1 -6.93858572707181764372e-01 +#define BU2 -1.05586262253232909814e+01 +#define BU3 -6.23753324503260060396e+01 +#define BU4 -1.62396669462573470355e+02 +#define BU5 -1.84605092906711035994e+02 +#define BU6 -8.12874355063065934246e+01 +#define BU7 -9.81432934416914548592e+00 + +#define BV0 1.96512716674392571292e+01 +#define BV1 1.37657754143519042600e+02 +#define BV2 4.34565877475229228821e+02 +#define BV3 6.45387271733267880336e+02 +#define BV4 4.29008140027567833386e+02 +#define BV5 1.08635005541779435134e+02 +#define BV6 6.57024977031928170135e+00 +#define BV7 -6.04244152148580987438e-02 + +#define CU0 -2.36211856075265944077e-03 +#define CU1 4.14856118683748331666e-01 +#define CU2 -3.72207876035701323847e-01 +#define CU3 3.18346619901161753674e-01 +#define CU4 -1.10894694282396677476e-01 +#define CU5 3.54783043256182359371e-02 +#define CU6 -2.16637559486879084300e-03 + +#define CV0 1.06420880400844228286e-01 +#define CV1 5.40397917702171048937e-01 +#define CV2 7.18286544141962662868e-02 +#define CV3 1.26171219808761642112e-01 +#define CV4 1.36370839120290507362e-02 +#define CV5 1.19844998467991074170e-02 + +#define DU0 1.28379167095512558561e-01 +#define DU1 -3.25042107247001499370e-01 +#define DU2 -2.84817495755985104766e-02 +#define DU3 -5.77027029648944159157e-03 +#define DU4 -2.37630166566501626084e-05 + +#define DV0 3.97917223959155352819e-01 +#define DV1 6.50222499887672944485e-02 +#define DV2 5.08130628187576562776e-03 +#define DV3 1.32494738004321644526e-04 +#define DV4 -3.96022827877536812320e-06 + +_CLC_OVERLOAD _CLC_DEF double __spirv_ocl_erfc(double x) { + long lx = as_long(x); + long ax = lx & 0x7fffffffffffffffL; + double absx = as_double(ax); + int xneg = lx != ax; + + // Poly arg + double x2 = x * x; + double xm1 = absx - 1.0; + double t = 1.0 / x2; + t = absx < 1.25 ? xm1 : t; + t = absx < 0.84375 ? x2 : t; + + // Evaluate rational poly + // XXX Need to evaluate if we can grab the 14 coefficients from a + // table faster than evaluating 3 pairs of polys + double tu, tv, u, v; + + // |x| < 28 + u = __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, __spirv_ocl_fma(t, __spirv_ocl_fma(t, AU6, AU5), AU4), + AU3), + AU2), + AU1), + AU0); + v = __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, __spirv_ocl_fma(t, __spirv_ocl_fma(t, AV6, AV5), AV4), + AV3), + AV2), + AV1), + AV0); + + tu = __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, __spirv_ocl_fma(t, __spirv_ocl_fma(t, BU7, BU6), BU5), + BU4), + BU3), + BU2), + BU1), + BU0); + tv = __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, __spirv_ocl_fma(t, __spirv_ocl_fma(t, BV7, BV6), BV5), + BV4), + BV3), + BV2), + BV1), + BV0); + u = absx < 0x1.6db6dp+1 ? tu : u; + v = absx < 0x1.6db6dp+1 ? tv : v; + + tu = __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, __spirv_ocl_fma(t, __spirv_ocl_fma(t, CU6, CU5), CU4), + CU3), + CU2), + CU1), + CU0); + tv = __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, + __spirv_ocl_fma( + t, __spirv_ocl_fma(t, __spirv_ocl_fma(t, CV5, CV4), CV3), CV2), + CV1), + CV0); + u = absx < 1.25 ? tu : u; + v = absx < 1.25 ? tv : v; + + tu = __spirv_ocl_fma( + t, + __spirv_ocl_fma(t, __spirv_ocl_fma(t, __spirv_ocl_fma(t, DU4, DU3), DU2), + DU1), + DU0); + tv = __spirv_ocl_fma( + t, + __spirv_ocl_fma(t, __spirv_ocl_fma(t, __spirv_ocl_fma(t, DV4, DV3), DV2), + DV1), + DV0); + u = absx < 0.84375 ? tu : u; + v = absx < 0.84375 ? tv : v; + + v = __spirv_ocl_fma(t, v, 1.0); + double q = u / v; + + // Evaluate return value + + // |x| < 28 + double z = as_double(ax & 0xffffffff00000000UL); + double ret = __spirv_ocl_exp(-z * z - 0.5625) * + __spirv_ocl_exp((z - absx) * (z + absx) + q) / absx; + t = 2.0 - ret; + ret = xneg ? t : ret; + + const double erx = 8.45062911510467529297e-01; + z = erx + q + 1.0; + t = 1.0 - erx - q; + t = xneg ? z : t; + ret = absx < 1.25 ? t : ret; + + // z = 1.0 - fma(x, q, x); + // t = 0.5 - fma(x, q, x - 0.5); + // t = xneg == 1 | absx < 0.25 ? z : t; + t = __spirv_ocl_fma(-x, q, 1.0 - x); + ret = absx < 0.84375 ? t : ret; + + ret = x >= 28.0 ? 0.0 : ret; + ret = x <= -6.0 ? 2.0 : ret; + ret = ax > 0x7ff0000000000000UL ? x : ret; + + return ret; +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, double, __spirv_ocl_erfc, double); + +#endif diff --git a/libclc/generic/libspirv/math/exp.cl b/libclc/generic/libspirv/math/exp.cl index 512f54169e4f1..3fdc69a44fa13 100644 --- a/libclc/generic/libspirv/math/exp.cl +++ b/libclc/generic/libspirv/math/exp.cl @@ -8,8 +8,8 @@ #include -#include "../../lib/math/math.h" -#include "../../lib/clcmacro.h" +#include +#include _CLC_OVERLOAD _CLC_DEF float __spirv_ocl_exp(float x) { diff --git a/libclc/generic/libspirv/math/exp10.cl b/libclc/generic/libspirv/math/exp10.cl index 98c0795e4bbb2..bc97757995f3b 100644 --- a/libclc/generic/libspirv/math/exp10.cl +++ b/libclc/generic/libspirv/math/exp10.cl @@ -11,6 +11,6 @@ #define __CLC_FUNC __spirv_ocl_exp10 #define __CLC_SW_FUNC __clc_exp10 -#define __CLC_BODY <../../lib/math/clc_sw_unary.inc> +#define __CLC_BODY #include #undef __CLC_SW_FUNC diff --git a/libclc/generic/libspirv/math/exp2.cl b/libclc/generic/libspirv/math/exp2.cl index ac6f271ca352d..6e6a736722379 100644 --- a/libclc/generic/libspirv/math/exp2.cl +++ b/libclc/generic/libspirv/math/exp2.cl @@ -8,8 +8,8 @@ #include -#include "../../lib/math/math.h" -#include "../../lib/clcmacro.h" +#include +#include _CLC_OVERLOAD _CLC_DEF float __spirv_ocl_exp2(float x) { diff --git a/libclc/generic/libspirv/math/exp_helper.cl b/libclc/generic/libspirv/math/exp_helper.cl index e85be203a5f0c..8daf23a817f7d 100644 --- a/libclc/generic/libspirv/math/exp_helper.cl +++ b/libclc/generic/libspirv/math/exp_helper.cl @@ -22,8 +22,8 @@ #include -#include "../../lib/math/math.h" #include "tables.h" +#include #ifdef cl_khr_fp64 diff --git a/libclc/generic/libspirv/math/expm1.cl b/libclc/generic/libspirv/math/expm1.cl index 3b672d012115f..31407f8a689bd 100644 --- a/libclc/generic/libspirv/math/expm1.cl +++ b/libclc/generic/libspirv/math/expm1.cl @@ -8,9 +8,9 @@ #include -#include "../../lib/math/math.h" #include "tables.h" -#include "../../lib/clcmacro.h" +#include +#include /* Refer to the exp routine for the underlying algorithm */ @@ -45,7 +45,7 @@ _CLC_OVERLOAD _CLC_DEF float __spirv_ocl_expm1(float x) { z2 = __spirv_ocl_mad(z2, two_to_jby64, two_to_jby64_t) + (two_to_jby64_h - 1.0f); //Make subnormals work z2 = x == 0.f ? x : z2; - z2 = x < X_MIN | m < -24 ? -1.0f : z2; + z2 = x < X_MIN || m < -24 ? -1.0f : z2; z2 = x > X_MAX ? as_float(PINFBITPATT_SP32) : z2; z2 = __spirv_IsNan(x) ? x : z2; @@ -139,7 +139,7 @@ _CLC_OVERLOAD _CLC_DEF double __spirv_ocl_expm1(double x) { z = m < 53 ? zml53 : zmg52; z = m < -7 ? zmln7 : z; - z = x > log_OneMinus_OneByFour & x < log_OnePlus_OneByFour ? z1 : z; + z = x > log_OneMinus_OneByFour && x < log_OnePlus_OneByFour ? z1 : z; z = x > max_expm1_arg ? as_double(PINFBITPATT_DP64) : z; z = x < min_expm1_arg ? -1.0 : z; diff --git a/libclc/generic/libspirv/math/fabs.cl b/libclc/generic/libspirv/math/fabs.cl index b8cbd18cd7e63..395dadb57422f 100644 --- a/libclc/generic/libspirv/math/fabs.cl +++ b/libclc/generic/libspirv/math/fabs.cl @@ -6,14 +6,14 @@ // //===----------------------------------------------------------------------===// +#include #include -#include "../../lib/clcmacro.h" // Map the llvm intrinsic to an OpenCL function. #define __CLC_FUNCTION __clc___spirv_ocl_fabs #define __CLC_INTRINSIC "llvm.fabs" -#include "math/unary_intrin.inc" +#include #undef __CLC_FUNCTION #define __CLC_FUNCTION __spirv_ocl_fabs -#include "unary_builtin.inc" +#include diff --git a/libclc/generic/include/spirv/math/fract.h b/libclc/generic/libspirv/math/fdim.cl similarity index 76% rename from libclc/generic/include/spirv/math/fract.h rename to libclc/generic/libspirv/math/fdim.cl index 6cf7607c8d2f2..a4818b9ecf812 100644 --- a/libclc/generic/include/spirv/math/fract.h +++ b/libclc/generic/libspirv/math/fdim.cl @@ -6,5 +6,9 @@ // //===----------------------------------------------------------------------===// -#define __SPIRV_BODY -#include +#include + +#include + +#define __CLC_BODY +#include diff --git a/libclc/generic/libspirv/math/fdim.inc b/libclc/generic/libspirv/math/fdim.inc new file mode 100644 index 0000000000000..bd88078791015 --- /dev/null +++ b/libclc/generic/libspirv/math/fdim.inc @@ -0,0 +1,62 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#if __CLC_FPSIZE == 32 +#ifdef __CLC_SCALAR +_CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE __spirv_ocl_fdim(__CLC_GENTYPE x, + __CLC_GENTYPE y) { + if (__builtin_isnan(x) || __builtin_isnan(y)) + return as_float(QNANBITPATT_SP32); + return __spirv_ocl_fmax(x - y, 0.0f); +} +#define __CLC_FDIM_VEC(width) \ + _CLC_OVERLOAD _CLC_DEF float##width __spirv_ocl_fdim(float##width x, \ + float##width y) { \ + /* Determine if x or y is NaN. */ \ + /* Vector true is -1, i.e. all-bits-set, and NaN==NaN is false. */ \ + /* If either is NaN, then ~((x==x) & (y==y)) will be 0 (e.g. ~(-1)), as \ + * will n. */ \ + int##width n = ~((x == x) & (y == y)) & QNANBITPATT_SP32; \ + /* Calculate x-y if x>y, otherwise positive 0, again taking */ \ + /* advantage of vector true being all-bits-set. */ \ + int##width r = (x > y) & as_int##width(x - y); \ + return as_float##width(n | r); \ + } +__CLC_FDIM_VEC(2) +__CLC_FDIM_VEC(3) +__CLC_FDIM_VEC(4) +__CLC_FDIM_VEC(8) +__CLC_FDIM_VEC(16) +#undef __CLC_FDIM_VEC +#endif +#endif + +#if __CLC_FPSIZE == 64 +#ifdef __CLC_SCALAR +_CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE __spirv_ocl_fdim(__CLC_GENTYPE x, + private __CLC_GENTYPE y) { + long n = -(__spirv_IsNan(x) | __spirv_IsNan(y)) & QNANBITPATT_DP64; + long r = -(x > y) & as_long(x - y); + return as_double(n | r); +} +#define __CLC_FDIM_VEC(width) \ + _CLC_OVERLOAD _CLC_DEF double##width __spirv_ocl_fdim(double##width x, \ + double##width y) { \ + /* See comment in float implementation for explanation. */ \ + long##width n = ~((x == x) & (y == y)) & QNANBITPATT_DP64; \ + long##width r = (x > y) & as_long##width(x - y); \ + return as_double##width(n | r); \ + } +__CLC_FDIM_VEC(2) +__CLC_FDIM_VEC(3) +__CLC_FDIM_VEC(4) +__CLC_FDIM_VEC(8) +__CLC_FDIM_VEC(16) +#undef __CLC_FDIM_VEC +#endif +#endif diff --git a/libclc/generic/libspirv/math/floor.cl b/libclc/generic/libspirv/math/floor.cl index c37ebfad41de9..24c6e6801b8f1 100644 --- a/libclc/generic/libspirv/math/floor.cl +++ b/libclc/generic/libspirv/math/floor.cl @@ -6,14 +6,14 @@ // //===----------------------------------------------------------------------===// +#include #include -#include "../../lib/clcmacro.h" // Map the llvm intrinsic to an OpenCL function. #define __CLC_FUNCTION __clc___spirv_ocl_floor #define __CLC_INTRINSIC "llvm.floor" -#include "math/unary_intrin.inc" +#include #undef __CLC_FUNCTION #define __CLC_FUNCTION __spirv_ocl_floor -#include "unary_builtin.inc" +#include diff --git a/libclc/generic/libspirv/math/fma.cl b/libclc/generic/libspirv/math/fma.cl index 140f4860955a3..bcb834285e30e 100644 --- a/libclc/generic/libspirv/math/fma.cl +++ b/libclc/generic/libspirv/math/fma.cl @@ -8,8 +8,8 @@ #include -#include "../../lib/math/math.h" -#include "math/clc_fma.h" +#include +#include #define __CLC_BODY #include diff --git a/libclc/generic/libspirv/math/fmax.cl b/libclc/generic/libspirv/math/fmax.cl index 35ad878414599..985cb5fbfee66 100644 --- a/libclc/generic/libspirv/math/fmax.cl +++ b/libclc/generic/libspirv/math/fmax.cl @@ -6,10 +6,9 @@ // //===----------------------------------------------------------------------===// +#include #include -#include "../lib/clcmacro.h" - _CLC_DEFINE_BINARY_BUILTIN(float, __spirv_ocl_fmax, __builtin_fmaxf, float, float); #ifdef cl_khr_fp64 diff --git a/libclc/generic/libspirv/math/fmax_common.cl b/libclc/generic/libspirv/math/fmax_common.cl new file mode 100644 index 0000000000000..85ea31391f3b5 --- /dev/null +++ b/libclc/generic/libspirv/math/fmax_common.cl @@ -0,0 +1,13 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include +#include + +#define __CLC_BODY +#include diff --git a/libclc/generic/include/spirv/math/acos.h b/libclc/generic/libspirv/math/fmax_common.inc similarity index 66% rename from libclc/generic/include/spirv/math/acos.h rename to libclc/generic/libspirv/math/fmax_common.inc index 5f708d798529c..0c45e89ec4b48 100644 --- a/libclc/generic/include/spirv/math/acos.h +++ b/libclc/generic/libspirv/math/fmax_common.inc @@ -6,10 +6,7 @@ // //===----------------------------------------------------------------------===// -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_acos - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION +_CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE __spirv_ocl_fmax_common(__CLC_GENTYPE x, + __CLC_GENTYPE y) { + return (x < y) ? y : x; +} diff --git a/libclc/generic/libspirv/math/fmin.cl b/libclc/generic/libspirv/math/fmin.cl index c48917b2b7932..39f0fd589cdca 100644 --- a/libclc/generic/libspirv/math/fmin.cl +++ b/libclc/generic/libspirv/math/fmin.cl @@ -8,7 +8,7 @@ #include -#include "../../lib/clcmacro.h" +#include _CLC_DEFINE_BINARY_BUILTIN(float, __spirv_ocl_fmin, __builtin_fminf, float, float); diff --git a/libclc/generic/libspirv/math/fmin_common.cl b/libclc/generic/libspirv/math/fmin_common.cl new file mode 100644 index 0000000000000..4314b1bbe3e25 --- /dev/null +++ b/libclc/generic/libspirv/math/fmin_common.cl @@ -0,0 +1,13 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include +#include + +#define __CLC_BODY +#include diff --git a/libclc/generic/include/spirv/math/acosh.h b/libclc/generic/libspirv/math/fmin_common.inc similarity index 66% rename from libclc/generic/include/spirv/math/acosh.h rename to libclc/generic/libspirv/math/fmin_common.inc index c5bbf87b55632..6faa034f9d136 100644 --- a/libclc/generic/include/spirv/math/acosh.h +++ b/libclc/generic/libspirv/math/fmin_common.inc @@ -6,10 +6,7 @@ // //===----------------------------------------------------------------------===// -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_acosh - -#include - -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION +_CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE __spirv_ocl_fmin_common(__CLC_GENTYPE x, + __CLC_GENTYPE y) { + return (x < y) ? x : y; +} diff --git a/libclc/generic/libspirv/math/frexp.cl b/libclc/generic/libspirv/math/frexp.cl new file mode 100644 index 0000000000000..314befe6d4f76 --- /dev/null +++ b/libclc/generic/libspirv/math/frexp.cl @@ -0,0 +1,25 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include +#include + +#define __CLC_BODY +#define __CLC_ADDRESS_SPACE private +#include +#undef __CLC_ADDRESS_SPACE + +#define __CLC_BODY +#define __CLC_ADDRESS_SPACE global +#include +#undef __CLC_ADDRESS_SPACE + +#define __CLC_BODY +#define __CLC_ADDRESS_SPACE local +#include +#undef __CLC_ADDRESS_SPACE diff --git a/libclc/generic/libspirv/math/frexp.inc b/libclc/generic/libspirv/math/frexp.inc new file mode 100644 index 0000000000000..ce49d833bc299 --- /dev/null +++ b/libclc/generic/libspirv/math/frexp.inc @@ -0,0 +1,65 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#define __CLC_AS_GENTYPE __CLC_XCONCAT(as_, __CLC_GENTYPE) +#define __CLC_AS_INTN __CLC_XCONCAT(as_, __CLC_INTN) + +#if __CLC_FPSIZE == 32 +_CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE +__spirv_ocl_frexp(__CLC_GENTYPE x, __CLC_ADDRESS_SPACE __CLC_INTN *ep) { + __CLC_INTN i = __CLC_AS_INTN(x); + __CLC_INTN ai = i & 0x7fffffff; + __CLC_INTN d = ai > 0 & ai < 0x00800000; + /* scale subnormal by 2^26 without multiplying */ + __CLC_GENTYPE s = __CLC_AS_GENTYPE(ai | 0x0d800000) - 0x1.0p-100f; + ai = __spirv_ocl_select(ai, __CLC_AS_INTN(s), d); + __CLC_INTN e = + (ai >> 23) - 126 - __spirv_ocl_select((__CLC_INTN)0, (__CLC_INTN)26, d); + __CLC_INTN t = ai == (__CLC_INTN)0 | e == (__CLC_INTN)129; + i = (i & (__CLC_INTN)0x80000000) | (__CLC_INTN)0x3f000000 | (ai & 0x007fffff); + *ep = __spirv_ocl_select(e, (__CLC_INTN)0, t); + return __spirv_ocl_select(__CLC_AS_GENTYPE(i), x, t); +} +#endif + +#if __CLC_FPSIZE == 64 +#ifdef __CLC_SCALAR +#define __CLC_AS_LONGN as_long +#define __CLC_LONGN long +#define __CLC_CONVERT_INTN __spirv_SConvert_Rint +#else +#define __CLC_AS_LONGN __CLC_XCONCAT(as_long, __CLC_VECSIZE) +#define __CLC_LONGN __CLC_XCONCAT(long, __CLC_VECSIZE) +#define __CLC_CONVERT_INTN __CLC_XCONCAT(__spirv_SConvert_Rint, __CLC_VECSIZE) +#endif + +_CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE +__spirv_ocl_frexp(__CLC_GENTYPE x, __CLC_ADDRESS_SPACE __CLC_INTN *ep) { + __CLC_LONGN i = __CLC_AS_LONGN(x); + __CLC_LONGN ai = i & 0x7fffffffffffffffL; + __CLC_LONGN d = ai > 0 & ai < 0x0010000000000000L; + // scale subnormal by 2^54 without multiplying + __CLC_GENTYPE s = __CLC_AS_GENTYPE(ai | 0x0370000000000000L) - 0x1.0p-968; + ai = __spirv_ocl_select(ai, __CLC_AS_LONGN(s), d); + __CLC_LONGN e = (ai >> 52) - (__CLC_LONGN)1022 - + __spirv_ocl_select((__CLC_LONGN)0, (__CLC_LONGN)54, d); + __CLC_LONGN t = ai == 0 | e == 1025; + i = (i & (__CLC_LONGN)0x8000000000000000L) | + (__CLC_LONGN)0x3fe0000000000000L | + (ai & (__CLC_LONGN)0x000fffffffffffffL); + *ep = __CLC_CONVERT_INTN(__spirv_ocl_select(e, 0L, t)); + return __spirv_ocl_select(__CLC_AS_GENTYPE(i), x, t); +} + +#undef __CLC_AS_LONGN +#undef __CLC_LONGN +#undef __CLC_CONVERT_INTN +#endif + +#undef __CLC_AS_GENTYPE +#undef __CLC_AS_INTN diff --git a/libclc/generic/libspirv/math/half_cos.cl b/libclc/generic/libspirv/math/half_cos.cl new file mode 100644 index 0000000000000..b505bf660dbac --- /dev/null +++ b/libclc/generic/libspirv/math/half_cos.cl @@ -0,0 +1,13 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#define __CLC_BUILTIN __spirv_ocl_cos +#define __CLC_FUNCTION __spirv_ocl_half_cos +#include diff --git a/libclc/generic/libspirv/math/half_divide.cl b/libclc/generic/libspirv/math/half_divide.cl new file mode 100644 index 0000000000000..780277652a570 --- /dev/null +++ b/libclc/generic/libspirv/math/half_divide.cl @@ -0,0 +1,15 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#define divide(x, y) (x / y) + +#define __CLC_BUILTIN divide +#define __CLC_FUNCTION __spirv_ocl_half_divide +#include diff --git a/libclc/generic/libspirv/math/half_exp.cl b/libclc/generic/libspirv/math/half_exp.cl new file mode 100644 index 0000000000000..f20f6afeb0580 --- /dev/null +++ b/libclc/generic/libspirv/math/half_exp.cl @@ -0,0 +1,13 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#define __CLC_BUILTIN __spirv_ocl_exp +#define __CLC_FUNCTION __spirv_ocl_half_exp +#include diff --git a/libclc/generic/libspirv/math/half_exp10.cl b/libclc/generic/libspirv/math/half_exp10.cl new file mode 100644 index 0000000000000..3ffcb7004b254 --- /dev/null +++ b/libclc/generic/libspirv/math/half_exp10.cl @@ -0,0 +1,13 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#define __CLC_BUILTIN __spirv_ocl_exp10 +#define __CLC_FUNCTION __spirv_ocl_half_exp10 +#include diff --git a/libclc/generic/libspirv/math/half_exp2.cl b/libclc/generic/libspirv/math/half_exp2.cl new file mode 100644 index 0000000000000..9cb7ebee42d90 --- /dev/null +++ b/libclc/generic/libspirv/math/half_exp2.cl @@ -0,0 +1,13 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#define __CLC_BUILTIN __spirv_ocl_exp2 +#define __CLC_FUNCTION __spirv_ocl_half_exp2 +#include diff --git a/libclc/generic/libspirv/math/half_log.cl b/libclc/generic/libspirv/math/half_log.cl new file mode 100644 index 0000000000000..73808273e5aaf --- /dev/null +++ b/libclc/generic/libspirv/math/half_log.cl @@ -0,0 +1,13 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#define __CLC_BUILTIN __spirv_ocl_log +#define __CLC_FUNCTION __spirv_ocl_half_log +#include diff --git a/libclc/generic/libspirv/math/half_log10.cl b/libclc/generic/libspirv/math/half_log10.cl new file mode 100644 index 0000000000000..5391ec5308084 --- /dev/null +++ b/libclc/generic/libspirv/math/half_log10.cl @@ -0,0 +1,13 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#define __CLC_BUILTIN __spirv_ocl_log10 +#define __CLC_FUNCTION __spirv_ocl_half_log10 +#include diff --git a/libclc/generic/libspirv/math/half_log2.cl b/libclc/generic/libspirv/math/half_log2.cl new file mode 100644 index 0000000000000..e6353e9f1dc13 --- /dev/null +++ b/libclc/generic/libspirv/math/half_log2.cl @@ -0,0 +1,13 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#define __CLC_BUILTIN __spirv_ocl_log2 +#define __CLC_FUNCTION __spirv_ocl_half_log2 +#include diff --git a/libclc/generic/libspirv/math/half_powr.cl b/libclc/generic/libspirv/math/half_powr.cl new file mode 100644 index 0000000000000..76cb902a896fa --- /dev/null +++ b/libclc/generic/libspirv/math/half_powr.cl @@ -0,0 +1,13 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#define __CLC_BUILTIN __spirv_ocl_powr +#define __CLC_FUNCTION __spirv_ocl_half_powr +#include diff --git a/libclc/generic/include/spirv/math/fmod.h b/libclc/generic/libspirv/math/half_recip.cl similarity index 69% rename from libclc/generic/include/spirv/math/fmod.h rename to libclc/generic/libspirv/math/half_recip.cl index 0214b2a4d2d59..256d7c48a0e62 100644 --- a/libclc/generic/include/spirv/math/fmod.h +++ b/libclc/generic/libspirv/math/half_recip.cl @@ -6,7 +6,10 @@ // //===----------------------------------------------------------------------===// -#define __SPIRV_FUNCTION __spirv_ocl_fmod -#define __SPIRV_BODY -#include -#undef __SPIRV_FUNCTION +#include + +#define recip(x) (1.0f / x) + +#define __CLC_BUILTIN recip +#define __CLC_FUNCTION __spirv_ocl_half_recip +#include diff --git a/libclc/generic/libspirv/math/half_rsqrt.cl b/libclc/generic/libspirv/math/half_rsqrt.cl index 26e00018ec8d4..2118d7d3c1ca2 100644 --- a/libclc/generic/libspirv/math/half_rsqrt.cl +++ b/libclc/generic/libspirv/math/half_rsqrt.cl @@ -10,4 +10,4 @@ #define __CLC_BUILTIN __spirv_ocl_rsqrt #define __CLC_FUNCTION __spirv_ocl_half_rsqrt -#include "unary_builtin.inc" +#include diff --git a/libclc/generic/libspirv/math/half_sin.cl b/libclc/generic/libspirv/math/half_sin.cl new file mode 100644 index 0000000000000..bd280b7ad9935 --- /dev/null +++ b/libclc/generic/libspirv/math/half_sin.cl @@ -0,0 +1,13 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#define __CLC_BUILTIN __spirv_ocl_sin +#define __CLC_FUNCTION __spirv_ocl_half_sin +#include diff --git a/libclc/generic/libspirv/math/half_sqrt.cl b/libclc/generic/libspirv/math/half_sqrt.cl index 6ac8093447d48..4b9fb2769d122 100644 --- a/libclc/generic/libspirv/math/half_sqrt.cl +++ b/libclc/generic/libspirv/math/half_sqrt.cl @@ -10,4 +10,4 @@ #define __CLC_BUILTIN __spirv_ocl_sqrt #define __CLC_FUNCTION __spirv_ocl_half_sqrt -#include "unary_builtin.inc" +#include diff --git a/libclc/generic/libspirv/math/half_tan.cl b/libclc/generic/libspirv/math/half_tan.cl new file mode 100644 index 0000000000000..326b2c6b0bcbb --- /dev/null +++ b/libclc/generic/libspirv/math/half_tan.cl @@ -0,0 +1,13 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#define __CLC_BUILTIN __spirv_ocl_tan +#define __CLC_FUNCTION __spirv_ocl_half_tan +#include diff --git a/libclc/generic/include/spirv/math/asin.h b/libclc/generic/libspirv/math/hypot.cl similarity index 65% rename from libclc/generic/include/spirv/math/asin.h rename to libclc/generic/libspirv/math/hypot.cl index 63cc235cdfc82..14e5168fa1ff2 100644 --- a/libclc/generic/include/spirv/math/asin.h +++ b/libclc/generic/libspirv/math/hypot.cl @@ -6,10 +6,11 @@ // //===----------------------------------------------------------------------===// -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_asin +#include -#include +#include -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION +#define __CLC_FUNC __spirv_ocl_hypot +#define __CLC_SW_FUNC __clc_hypot +#define __CLC_BODY +#include diff --git a/libclc/generic/libspirv/math/ilogb.cl b/libclc/generic/libspirv/math/ilogb.cl new file mode 100644 index 0000000000000..2e991afa2f50a --- /dev/null +++ b/libclc/generic/libspirv/math/ilogb.cl @@ -0,0 +1,43 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include +#include + +_CLC_OVERLOAD _CLC_DEF int __spirv_ocl_ilogb(float x) { + uint ux = as_uint(x); + uint ax = ux & EXSIGNBIT_SP32; + int rs = -118 - (int)__spirv_ocl_clz(ux & MANTBITS_SP32); + int r = (int)(ax >> EXPSHIFTBITS_SP32) - EXPBIAS_SP32; + r = ax < 0x00800000U ? rs : r; + r = ax > EXPBITS_SP32 || ax == 0 ? 0x80000000 : r; + r = ax == EXPBITS_SP32 ? 0x7fffffff : r; + return r; +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, int, __spirv_ocl_ilogb, float); + +#ifdef cl_khr_fp64 +#pragma OPENCL EXTENSION cl_khr_fp64 : enable + +_CLC_OVERLOAD _CLC_DEF int __spirv_ocl_ilogb(double x) { + ulong ux = as_ulong(x); + ulong ax = ux & ~SIGNBIT_DP64; + int r = (int)(ax >> EXPSHIFTBITS_DP64) - EXPBIAS_DP64; + int rs = -1011 - (int)__spirv_ocl_clz(ax & MANTBITS_DP64); + r = ax < 0x0010000000000000UL ? rs : r; + r = ax > 0x7ff0000000000000UL || ax == 0UL ? 0x80000000 : r; + r = ax == 0x7ff0000000000000UL ? 0x7fffffff : r; + return r; +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, int, __spirv_ocl_ilogb, double); + +#endif // cl_khr_fp64 diff --git a/libclc/generic/libspirv/math/ldexp.cl b/libclc/generic/libspirv/math/ldexp.cl index d3d58206a2df6..aea4f0c7b4aa7 100644 --- a/libclc/generic/libspirv/math/ldexp.cl +++ b/libclc/generic/libspirv/math/ldexp.cl @@ -7,18 +7,21 @@ //===----------------------------------------------------------------------===// #include -#include "config.h" -#include "math/clc_ldexp.h" -#include "../../lib/clcmacro.h" -#include "../../lib/math/math.h" + +#include +#include +#include +#include _CLC_DEFINE_BINARY_BUILTIN(float, __spirv_ocl_ldexp, __clc_ldexp, float, int) +_CLC_DEFINE_BINARY_BUILTIN(float, __spirv_ocl_ldexp, __clc_ldexp, float, uint) #ifdef cl_khr_fp64 #pragma OPENCL EXTENSION cl_khr_fp64 : enable _CLC_DEFINE_BINARY_BUILTIN(double, __spirv_ocl_ldexp, __clc_ldexp, double, int) +_CLC_DEFINE_BINARY_BUILTIN(double, __spirv_ocl_ldexp, __clc_ldexp, double, uint) #endif #ifdef cl_khr_fp16 @@ -26,8 +29,5 @@ _CLC_DEFINE_BINARY_BUILTIN(double, __spirv_ocl_ldexp, __clc_ldexp, double, int) #pragma OPENCL EXTENSION cl_khr_fp16 : enable _CLC_DEFINE_BINARY_BUILTIN(half, __spirv_ocl_ldexp, __clc_ldexp, half, int) +_CLC_DEFINE_BINARY_BUILTIN(half, __spirv_ocl_ldexp, __clc_ldexp, half, uint) #endif - -// This defines all the ldexp(GENTYPE, int) variants -#define __CLC_BODY -#include diff --git a/libclc/generic/libspirv/math/unary_builtin.inc b/libclc/generic/libspirv/math/lgamma.cl similarity index 51% rename from libclc/generic/libspirv/math/unary_builtin.inc rename to libclc/generic/libspirv/math/lgamma.cl index 8a9a72e4cf5cb..701d898bc0538 100644 --- a/libclc/generic/libspirv/math/unary_builtin.inc +++ b/libclc/generic/libspirv/math/lgamma.cl @@ -6,27 +6,24 @@ // //===----------------------------------------------------------------------===// -#include "../../lib/clcmacro.h" -#include "utils.h" +#include +#include -#ifndef __CLC_BUILTIN -#define __CLC_BUILTIN __CLC_XCONCAT(__clc_, __CLC_FUNCTION) -#endif +_CLC_OVERLOAD _CLC_DEF float __spirv_ocl_lgamma(float x) { + int s; + return __spirv_ocl_lgamma_r(x, &s); +} -_CLC_DEFINE_UNARY_BUILTIN(float, __CLC_FUNCTION, __CLC_BUILTIN, float) +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, float, __spirv_ocl_lgamma, float) #ifdef cl_khr_fp64 - #pragma OPENCL EXTENSION cl_khr_fp64 : enable -_CLC_DEFINE_UNARY_BUILTIN(double, __CLC_FUNCTION, __CLC_BUILTIN, double) - -#endif - -#ifdef cl_khr_fp16 - -#pragma OPENCL EXTENSION cl_khr_fp16 : enable +_CLC_OVERLOAD _CLC_DEF double __spirv_ocl_lgamma(double x) { + int s; + return __spirv_ocl_lgamma_r(x, &s); +} -_CLC_DEFINE_UNARY_BUILTIN(half, __CLC_FUNCTION, __CLC_BUILTIN, half) +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, double, __spirv_ocl_lgamma, double) #endif diff --git a/libclc/generic/libspirv/math/lgamma_r.cl b/libclc/generic/libspirv/math/lgamma_r.cl new file mode 100644 index 0000000000000..6f23c50c0607a --- /dev/null +++ b/libclc/generic/libspirv/math/lgamma_r.cl @@ -0,0 +1,660 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include +#include + +/* + * ==================================================== + * Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved. + * + * Developed at SunPro, a Sun Microsystems, Inc. business. + * Permission to use, copy, modify, and distribute this + * software is freely granted, provided that this notice + * is preserved. + * ==================================================== + */ + +#define pi_f 3.1415927410e+00f /* 0x40490fdb */ + +#define a0_f 7.7215664089e-02f /* 0x3d9e233f */ +#define a1_f 3.2246702909e-01f /* 0x3ea51a66 */ +#define a2_f 6.7352302372e-02f /* 0x3d89f001 */ +#define a3_f 2.0580807701e-02f /* 0x3ca89915 */ +#define a4_f 7.3855509982e-03f /* 0x3bf2027e */ +#define a5_f 2.8905137442e-03f /* 0x3b3d6ec6 */ +#define a6_f 1.1927076848e-03f /* 0x3a9c54a1 */ +#define a7_f 5.1006977446e-04f /* 0x3a05b634 */ +#define a8_f 2.2086278477e-04f /* 0x39679767 */ +#define a9_f 1.0801156895e-04f /* 0x38e28445 */ +#define a10_f 2.5214456400e-05f /* 0x37d383a2 */ +#define a11_f 4.4864096708e-05f /* 0x383c2c75 */ + +#define tc_f 1.4616321325e+00f /* 0x3fbb16c3 */ + +#define tf_f -1.2148628384e-01f /* 0xbdf8cdcd */ +/* tt -(tail of tf) */ +#define tt_f 6.6971006518e-09f /* 0x31e61c52 */ + +#define t0_f 4.8383611441e-01f /* 0x3ef7b95e */ +#define t1_f -1.4758771658e-01f /* 0xbe17213c */ +#define t2_f 6.4624942839e-02f /* 0x3d845a15 */ +#define t3_f -3.2788541168e-02f /* 0xbd064d47 */ +#define t4_f 1.7970675603e-02f /* 0x3c93373d */ +#define t5_f -1.0314224288e-02f /* 0xbc28fcfe */ +#define t6_f 6.1005386524e-03f /* 0x3bc7e707 */ +#define t7_f -3.6845202558e-03f /* 0xbb7177fe */ +#define t8_f 2.2596477065e-03f /* 0x3b141699 */ +#define t9_f -1.4034647029e-03f /* 0xbab7f476 */ +#define t10_f 8.8108185446e-04f /* 0x3a66f867 */ +#define t11_f -5.3859531181e-04f /* 0xba0d3085 */ +#define t12_f 3.1563205994e-04f /* 0x39a57b6b */ +#define t13_f -3.1275415677e-04f /* 0xb9a3f927 */ +#define t14_f 3.3552918467e-04f /* 0x39afe9f7 */ + +#define u0_f -7.7215664089e-02f /* 0xbd9e233f */ +#define u1_f 6.3282704353e-01f /* 0x3f2200f4 */ +#define u2_f 1.4549225569e+00f /* 0x3fba3ae7 */ +#define u3_f 9.7771751881e-01f /* 0x3f7a4bb2 */ +#define u4_f 2.2896373272e-01f /* 0x3e6a7578 */ +#define u5_f 1.3381091878e-02f /* 0x3c5b3c5e */ + +#define v1_f 2.4559779167e+00f /* 0x401d2ebe */ +#define v2_f 2.1284897327e+00f /* 0x4008392d */ +#define v3_f 7.6928514242e-01f /* 0x3f44efdf */ +#define v4_f 1.0422264785e-01f /* 0x3dd572af */ +#define v5_f 3.2170924824e-03f /* 0x3b52d5db */ + +#define s0_f -7.7215664089e-02f /* 0xbd9e233f */ +#define s1_f 2.1498242021e-01f /* 0x3e5c245a */ +#define s2_f 3.2577878237e-01f /* 0x3ea6cc7a */ +#define s3_f 1.4635047317e-01f /* 0x3e15dce6 */ +#define s4_f 2.6642270386e-02f /* 0x3cda40e4 */ +#define s5_f 1.8402845599e-03f /* 0x3af135b4 */ +#define s6_f 3.1947532989e-05f /* 0x3805ff67 */ + +#define r1_f 1.3920053244e+00f /* 0x3fb22d3b */ +#define r2_f 7.2193557024e-01f /* 0x3f38d0c5 */ +#define r3_f 1.7193385959e-01f /* 0x3e300f6e */ +#define r4_f 1.8645919859e-02f /* 0x3c98bf54 */ +#define r5_f 7.7794247773e-04f /* 0x3a4beed6 */ +#define r6_f 7.3266842264e-06f /* 0x36f5d7bd */ + +#define w0_f 4.1893854737e-01f /* 0x3ed67f1d */ +#define w1_f 8.3333335817e-02f /* 0x3daaaaab */ +#define w2_f -2.7777778450e-03f /* 0xbb360b61 */ +#define w3_f 7.9365057172e-04f /* 0x3a500cfd */ +#define w4_f -5.9518753551e-04f /* 0xba1c065c */ +#define w5_f 8.3633989561e-04f /* 0x3a5b3dd2 */ +#define w6_f -1.6309292987e-03f /* 0xbad5c4e8 */ + +_CLC_OVERLOAD _CLC_DEF float __spirv_ocl_lgamma_r(float x, private int *signp) { + int hx = as_int(x); + int ix = hx & 0x7fffffff; + float absx = as_float(ix); + + if (ix >= 0x7f800000) { + *signp = 1; + return x; + } + + if (absx < 0x1.0p-70f) { + *signp = hx < 0 ? -1 : 1; + return -__spirv_ocl_log(absx); + } + + float r; + + if (absx == 1.0f | absx == 2.0f) + r = 0.0f; + + else if (absx < 2.0f) { + float y = 2.0f - absx; + int i = 0; + + int c = absx < 0x1.bb4c30p+0f; + float yt = absx - tc_f; + y = c ? yt : y; + i = c ? 1 : i; + + c = absx < 0x1.3b4c40p+0f; + yt = absx - 1.0f; + y = c ? yt : y; + i = c ? 2 : i; + + r = -__spirv_ocl_log(absx); + yt = 1.0f - absx; + c = absx <= 0x1.ccccccp-1f; + r = c ? r : 0.0f; + y = c ? yt : y; + i = c ? 0 : i; + + c = absx < 0x1.769440p-1f; + yt = absx - (tc_f - 1.0f); + y = c ? yt : y; + i = c ? 1 : i; + + c = absx < 0x1.da6610p-3f; + y = c ? absx : y; + i = c ? 2 : i; + + float z, w, p1, p2, p3, p; + switch (i) { + case 0: + z = y * y; + p1 = __spirv_ocl_mad( + z, + __spirv_ocl_mad( + z, + __spirv_ocl_mad( + z, __spirv_ocl_mad(z, __spirv_ocl_mad(z, a10_f, a8_f), a6_f), + a4_f), + a2_f), + a0_f); + p2 = + z * + __spirv_ocl_mad( + z, + __spirv_ocl_mad( + z, + __spirv_ocl_mad( + z, + __spirv_ocl_mad(z, __spirv_ocl_mad(z, a11_f, a9_f), a7_f), + a5_f), + a3_f), + a1_f); + p = __spirv_ocl_mad(y, p1, p2); + r += __spirv_ocl_mad(y, -0.5f, p); + break; + case 1: + z = y * y; + w = z * y; + p1 = __spirv_ocl_mad( + w, + __spirv_ocl_mad( + w, __spirv_ocl_mad(w, __spirv_ocl_mad(w, t12_f, t9_f), t6_f), + t3_f), + t0_f); + p2 = __spirv_ocl_mad( + w, + __spirv_ocl_mad( + w, __spirv_ocl_mad(w, __spirv_ocl_mad(w, t13_f, t10_f), t7_f), + t4_f), + t1_f); + p3 = __spirv_ocl_mad( + w, + __spirv_ocl_mad( + w, __spirv_ocl_mad(w, __spirv_ocl_mad(w, t14_f, t11_f), t8_f), + t5_f), + t2_f); + p = __spirv_ocl_mad( + z, p1, -__spirv_ocl_mad(w, -__spirv_ocl_mad(y, p3, p2), tt_f)); + r += tf_f + p; + break; + case 2: + p1 = y * + __spirv_ocl_mad( + y, + __spirv_ocl_mad( + y, + __spirv_ocl_mad( + y, + __spirv_ocl_mad(y, __spirv_ocl_mad(y, u5_f, u4_f), u3_f), + u2_f), + u1_f), + u0_f); + p2 = __spirv_ocl_mad( + y, + __spirv_ocl_mad( + y, + __spirv_ocl_mad( + y, __spirv_ocl_mad(y, __spirv_ocl_mad(y, v5_f, v4_f), v3_f), + v2_f), + v1_f), + 1.0f); + r += __spirv_ocl_mad(y, -0.5f, MATH_DIVIDE(p1, p2)); + break; + } + } else if (absx < 8.0f) { + int i = (int)absx; + float y = absx - (float)i; + float p = y * __spirv_ocl_mad( + y, + __spirv_ocl_mad( + y, + __spirv_ocl_mad( + y, + __spirv_ocl_mad( + y, + __spirv_ocl_mad( + y, __spirv_ocl_mad(y, s6_f, s5_f), s4_f), + s3_f), + s2_f), + s1_f), + s0_f); + float q = __spirv_ocl_mad( + y, + __spirv_ocl_mad( + y, + __spirv_ocl_mad( + y, + __spirv_ocl_mad( + y, __spirv_ocl_mad(y, __spirv_ocl_mad(y, r6_f, r5_f), r4_f), + r3_f), + r2_f), + r1_f), + 1.0f); + r = __spirv_ocl_mad(y, 0.5f, MATH_DIVIDE(p, q)); + + float y6 = y + 6.0f; + float y5 = y + 5.0f; + float y4 = y + 4.0f; + float y3 = y + 3.0f; + float y2 = y + 2.0f; + + float z = 1.0f; + z *= i > 6 ? y6 : 1.0f; + z *= i > 5 ? y5 : 1.0f; + z *= i > 4 ? y4 : 1.0f; + z *= i > 3 ? y3 : 1.0f; + z *= i > 2 ? y2 : 1.0f; + + r += __spirv_ocl_log(z); + } else if (absx < 0x1.0p+58f) { + float z = 1.0f / absx; + float y = z * z; + float w = __spirv_ocl_mad( + z, + __spirv_ocl_mad( + y, + __spirv_ocl_mad( + y, + __spirv_ocl_mad( + y, __spirv_ocl_mad(y, __spirv_ocl_mad(y, w6_f, w5_f), w4_f), + w3_f), + w2_f), + w1_f), + w0_f); + r = __spirv_ocl_mad(absx - 0.5f, __spirv_ocl_log(absx) - 1.0f, w); + } else + // 2**58 <= x <= Inf + r = absx * (__spirv_ocl_log(absx) - 1.0f); + + int s = 1; + + if (x < 0.0f) { + float t = __spirv_ocl_sinpi(x); + r = __spirv_ocl_log(pi_f / __spirv_ocl_fabs(t * x)) - r; + r = t == 0.0f ? as_float(PINFBITPATT_SP32) : r; + s = t < 0.0f ? -1 : s; + } + + *signp = s; + return r; +} + +_CLC_V_V_VP_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, float, __spirv_ocl_lgamma_r, + float, private, int) + +#ifdef cl_khr_fp64 +#pragma OPENCL EXTENSION cl_khr_fp64 : enable +// ==================================================== +// Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved. +// +// Developed at SunPro, a Sun Microsystems, Inc. business. +// Permission to use, copy, modify, and distribute this +// software is freely granted, provided that this notice +// is preserved. +// ==================================================== + +// lgamma_r(x, i) +// Reentrant version of the logarithm of the Gamma function +// with user provide pointer for the sign of Gamma(x). +// +// Method: +// 1. Argument Reduction for 0 < x <= 8 +// Since gamma(1+s)=s*gamma(s), for x in [0,8], we may +// reduce x to a number in [1.5,2.5] by +// lgamma(1+s) = log(s) + lgamma(s) +// for example, +// lgamma(7.3) = log(6.3) + lgamma(6.3) +// = log(6.3*5.3) + lgamma(5.3) +// = log(6.3*5.3*4.3*3.3*2.3) + lgamma(2.3) +// 2. Polynomial approximation of lgamma around its +// minimun ymin=1.461632144968362245 to maintain monotonicity. +// On [ymin-0.23, ymin+0.27] (i.e., [1.23164,1.73163]), use +// Let z = x-ymin; +// lgamma(x) = -1.214862905358496078218 + z^2*poly(z) +// where +// poly(z) is a 14 degree polynomial. +// 2. Rational approximation in the primary interval [2,3] +// We use the following approximation: +// s = x-2.0; +// lgamma(x) = 0.5*s + s*P(s)/Q(s) +// with accuracy +// |P/Q - (lgamma(x)-0.5s)| < 2**-61.71 +// Our algorithms are based on the following observation +// +// zeta(2)-1 2 zeta(3)-1 3 +// lgamma(2+s) = s*(1-Euler) + --------- * s - --------- * s + ... +// 2 3 +// +// where Euler = 0.5771... is the Euler constant, which is very +// close to 0.5. +// +// 3. For x>=8, we have +// lgamma(x)~(x-0.5)log(x)-x+0.5*log(2pi)+1/(12x)-1/(360x**3)+.... +// (better formula: +// lgamma(x)~(x-0.5)*(log(x)-1)-.5*(log(2pi)-1) + ...) +// Let z = 1/x, then we approximation +// f(z) = lgamma(x) - (x-0.5)(log(x)-1) +// by +// 3 5 11 +// w = w0 + w1*z + w2*z + w3*z + ... + w6*z +// where +// |w - f(z)| < 2**-58.74 +// +// 4. For negative x, since (G is gamma function) +// -x*G(-x)*G(x) = pi/sin(pi*x), +// we have +// G(x) = pi/(sin(pi*x)*(-x)*G(-x)) +// since G(-x) is positive, sign(G(x)) = sign(sin(pi*x)) for x<0 +// Hence, for x<0, signgam = sign(sin(pi*x)) and +// lgamma(x) = log(|Gamma(x)|) +// = log(pi/(|x*sin(pi*x)|)) - lgamma(-x); +// Note: one should avoid compute pi*(-x) directly in the +// computation of sin(pi*(-x)). +// +// 5. Special Cases +// lgamma(2+s) ~ s*(1-Euler) for tiny s +// lgamma(1)=lgamma(2)=0 +// lgamma(x) ~ -log(x) for tiny x +// lgamma(0) = lgamma(inf) = inf +// lgamma(-integer) = +-inf +// +#define pi 3.14159265358979311600e+00 /* 0x400921FB, 0x54442D18 */ + +#define a0 7.72156649015328655494e-02 /* 0x3FB3C467, 0xE37DB0C8 */ +#define a1 3.22467033424113591611e-01 /* 0x3FD4A34C, 0xC4A60FAD */ +#define a2 6.73523010531292681824e-02 /* 0x3FB13E00, 0x1A5562A7 */ +#define a3 2.05808084325167332806e-02 /* 0x3F951322, 0xAC92547B */ +#define a4 7.38555086081402883957e-03 /* 0x3F7E404F, 0xB68FEFE8 */ +#define a5 2.89051383673415629091e-03 /* 0x3F67ADD8, 0xCCB7926B */ +#define a6 1.19270763183362067845e-03 /* 0x3F538A94, 0x116F3F5D */ +#define a7 5.10069792153511336608e-04 /* 0x3F40B6C6, 0x89B99C00 */ +#define a8 2.20862790713908385557e-04 /* 0x3F2CF2EC, 0xED10E54D */ +#define a9 1.08011567247583939954e-04 /* 0x3F1C5088, 0x987DFB07 */ +#define a10 2.52144565451257326939e-05 /* 0x3EFA7074, 0x428CFA52 */ +#define a11 4.48640949618915160150e-05 /* 0x3F07858E, 0x90A45837 */ + +#define tc 1.46163214496836224576e+00 /* 0x3FF762D8, 0x6356BE3F */ +#define tf -1.21486290535849611461e-01 /* 0xBFBF19B9, 0xBCC38A42 */ +#define tt -3.63867699703950536541e-18 /* 0xBC50C7CA, 0xA48A971F */ + +#define t0 4.83836122723810047042e-01 /* 0x3FDEF72B, 0xC8EE38A2 */ +#define t1 -1.47587722994593911752e-01 /* 0xBFC2E427, 0x8DC6C509 */ +#define t2 6.46249402391333854778e-02 /* 0x3FB08B42, 0x94D5419B */ +#define t3 -3.27885410759859649565e-02 /* 0xBFA0C9A8, 0xDF35B713 */ +#define t4 1.79706750811820387126e-02 /* 0x3F9266E7, 0x970AF9EC */ +#define t5 -1.03142241298341437450e-02 /* 0xBF851F9F, 0xBA91EC6A */ +#define t6 6.10053870246291332635e-03 /* 0x3F78FCE0, 0xE370E344 */ +#define t7 -3.68452016781138256760e-03 /* 0xBF6E2EFF, 0xB3E914D7 */ +#define t8 2.25964780900612472250e-03 /* 0x3F6282D3, 0x2E15C915 */ +#define t9 -1.40346469989232843813e-03 /* 0xBF56FE8E, 0xBF2D1AF1 */ +#define t10 8.81081882437654011382e-04 /* 0x3F4CDF0C, 0xEF61A8E9 */ +#define t11 -5.38595305356740546715e-04 /* 0xBF41A610, 0x9C73E0EC */ +#define t12 3.15632070903625950361e-04 /* 0x3F34AF6D, 0x6C0EBBF7 */ +#define t13 -3.12754168375120860518e-04 /* 0xBF347F24, 0xECC38C38 */ +#define t14 3.35529192635519073543e-04 /* 0x3F35FD3E, 0xE8C2D3F4 */ + +#define u0 -7.72156649015328655494e-02 /* 0xBFB3C467, 0xE37DB0C8 */ +#define u1 6.32827064025093366517e-01 /* 0x3FE4401E, 0x8B005DFF */ +#define u2 1.45492250137234768737e+00 /* 0x3FF7475C, 0xD119BD6F */ +#define u3 9.77717527963372745603e-01 /* 0x3FEF4976, 0x44EA8450 */ +#define u4 2.28963728064692451092e-01 /* 0x3FCD4EAE, 0xF6010924 */ +#define u5 1.33810918536787660377e-02 /* 0x3F8B678B, 0xBF2BAB09 */ + +#define v1 2.45597793713041134822e+00 /* 0x4003A5D7, 0xC2BD619C */ +#define v2 2.12848976379893395361e+00 /* 0x40010725, 0xA42B18F5 */ +#define v3 7.69285150456672783825e-01 /* 0x3FE89DFB, 0xE45050AF */ +#define v4 1.04222645593369134254e-01 /* 0x3FBAAE55, 0xD6537C88 */ +#define v5 3.21709242282423911810e-03 /* 0x3F6A5ABB, 0x57D0CF61 */ + +#define s0 -7.72156649015328655494e-02 /* 0xBFB3C467, 0xE37DB0C8 */ +#define s1 2.14982415960608852501e-01 /* 0x3FCB848B, 0x36E20878 */ +#define s2 3.25778796408930981787e-01 /* 0x3FD4D98F, 0x4F139F59 */ +#define s3 1.46350472652464452805e-01 /* 0x3FC2BB9C, 0xBEE5F2F7 */ +#define s4 2.66422703033638609560e-02 /* 0x3F9B481C, 0x7E939961 */ +#define s5 1.84028451407337715652e-03 /* 0x3F5E26B6, 0x7368F239 */ +#define s6 3.19475326584100867617e-05 /* 0x3F00BFEC, 0xDD17E945 */ + +#define r1 1.39200533467621045958e+00 /* 0x3FF645A7, 0x62C4AB74 */ +#define r2 7.21935547567138069525e-01 /* 0x3FE71A18, 0x93D3DCDC */ +#define r3 1.71933865632803078993e-01 /* 0x3FC601ED, 0xCCFBDF27 */ +#define r4 1.86459191715652901344e-02 /* 0x3F9317EA, 0x742ED475 */ +#define r5 7.77942496381893596434e-04 /* 0x3F497DDA, 0xCA41A95B */ +#define r6 7.32668430744625636189e-06 /* 0x3EDEBAF7, 0xA5B38140 */ + +#define w0 4.18938533204672725052e-01 /* 0x3FDACFE3, 0x90C97D69 */ +#define w1 8.33333333333329678849e-02 /* 0x3FB55555, 0x5555553B */ +#define w2 -2.77777777728775536470e-03 /* 0xBF66C16C, 0x16B02E5C */ +#define w3 7.93650558643019558500e-04 /* 0x3F4A019F, 0x98CF38B6 */ +#define w4 -5.95187557450339963135e-04 /* 0xBF4380CB, 0x8C0FE741 */ +#define w5 8.36339918996282139126e-04 /* 0x3F4B67BA, 0x4CDAD5D1 */ +#define w6 -1.63092934096575273989e-03 /* 0xBF5AB89D, 0x0B9E43E4 */ + +_CLC_OVERLOAD _CLC_DEF double __spirv_ocl_lgamma_r(double x, private int *ip) { + ulong ux = as_ulong(x); + ulong ax = ux & EXSIGNBIT_DP64; + double absx = as_double(ax); + + if (ax >= 0x7ff0000000000000UL) { + // +-Inf, NaN + *ip = 1; + return absx; + } + + if (absx < 0x1.0p-70) { + *ip = ax == ux ? 1 : -1; + return -__spirv_ocl_log(absx); + } + + // Handle rest of range + double r; + + if (absx < 2.0) { + int i = 0; + double y = 2.0 - absx; + + int c = absx < 0x1.bb4c3p+0; + double t = absx - tc; + i = c ? 1 : i; + y = c ? t : y; + + c = absx < 0x1.3b4c4p+0; + t = absx - 1.0; + i = c ? 2 : i; + y = c ? t : y; + + c = absx <= 0x1.cccccp-1; + t = -__spirv_ocl_log(absx); + r = c ? t : 0.0; + t = 1.0 - absx; + i = c ? 0 : i; + y = c ? t : y; + + c = absx < 0x1.76944p-1; + t = absx - (tc - 1.0); + i = c ? 1 : i; + y = c ? t : y; + + c = absx < 0x1.da661p-3; + i = c ? 2 : i; + y = c ? absx : y; + + double p, q; + + switch (i) { + case 0: + p = __spirv_ocl_fma( + y, + __spirv_ocl_fma( + y, __spirv_ocl_fma(y, __spirv_ocl_fma(y, a11, a10), a9), a8), + a7); + p = __spirv_ocl_fma( + y, + __spirv_ocl_fma(y, __spirv_ocl_fma(y, __spirv_ocl_fma(y, p, a6), a5), + a4), + a3); + p = __spirv_ocl_fma(y, __spirv_ocl_fma(y, __spirv_ocl_fma(y, p, a2), a1), + a0); + r = __spirv_ocl_fma(y, p - 0.5, r); + break; + case 1: + p = __spirv_ocl_fma( + y, + __spirv_ocl_fma( + y, __spirv_ocl_fma(y, __spirv_ocl_fma(y, t14, t13), t12), t11), + t10); + p = __spirv_ocl_fma( + y, + __spirv_ocl_fma( + y, + __spirv_ocl_fma( + y, __spirv_ocl_fma(y, __spirv_ocl_fma(y, p, t9), t8), t7), + t6), + t5); + p = __spirv_ocl_fma( + y, + __spirv_ocl_fma( + y, + __spirv_ocl_fma( + y, __spirv_ocl_fma(y, __spirv_ocl_fma(y, p, t4), t3), t2), + t1), + t0); + p = __spirv_ocl_fma(y * y, p, -tt); + r += (tf + p); + break; + case 2: + p = y * __spirv_ocl_fma( + y, + __spirv_ocl_fma( + y, + __spirv_ocl_fma( + y, __spirv_ocl_fma(y, __spirv_ocl_fma(y, u5, u4), u3), + u2), + u1), + u0); + q = __spirv_ocl_fma( + y, + __spirv_ocl_fma( + y, + __spirv_ocl_fma( + y, __spirv_ocl_fma(y, __spirv_ocl_fma(y, v5, v4), v3), v2), + v1), + 1.0); + r += __spirv_ocl_fma(-0.5, y, p / q); + } + } else if (absx < 8.0) { + int i = absx; + double y = absx - (double)i; + double p = + y * + __spirv_ocl_fma( + y, + __spirv_ocl_fma( + y, + __spirv_ocl_fma( + y, + __spirv_ocl_fma( + y, __spirv_ocl_fma(y, __spirv_ocl_fma(y, s6, s5), s4), + s3), + s2), + s1), + s0); + double q = __spirv_ocl_fma( + y, + __spirv_ocl_fma( + y, + __spirv_ocl_fma( + y, + __spirv_ocl_fma( + y, __spirv_ocl_fma(y, __spirv_ocl_fma(y, r6, r5), r4), r3), + r2), + r1), + 1.0); + r = __spirv_ocl_fma(0.5, y, p / q); + double z = 1.0; + // lgamma(1+s) = log(s) + lgamma(s) + double y6 = y + 6.0; + double y5 = y + 5.0; + double y4 = y + 4.0; + double y3 = y + 3.0; + double y2 = y + 2.0; + z *= i > 6 ? y6 : 1.0; + z *= i > 5 ? y5 : 1.0; + z *= i > 4 ? y4 : 1.0; + z *= i > 3 ? y3 : 1.0; + z *= i > 2 ? y2 : 1.0; + r += __spirv_ocl_log(z); + } else { + double z = 1.0 / absx; + double z2 = z * z; + double w = __spirv_ocl_fma( + z, + __spirv_ocl_fma( + z2, + __spirv_ocl_fma( + z2, + __spirv_ocl_fma( + z2, __spirv_ocl_fma(z2, __spirv_ocl_fma(z2, w6, w5), w4), + w3), + w2), + w1), + w0); + r = (absx - 0.5) * (__spirv_ocl_log(absx) - 1.0) + w; + } + + if (x < 0.0) { + double t = __spirv_ocl_sinpi(x); + r = __spirv_ocl_log(pi / __spirv_ocl_fabs(t * x)) - r; + r = t == 0.0 ? as_double(PINFBITPATT_DP64) : r; + *ip = t < 0.0 ? -1 : 1; + } else + *ip = 1; + + return r; +} + +_CLC_V_V_VP_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, double, __spirv_ocl_lgamma_r, + double, private, int) +#endif + +#ifdef cl_khr_fp16 +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +_CLC_OVERLOAD _CLC_DEF half __spirv_ocl_lgamma_r(half x, private int *signp) { + return __spirv_ocl_lgamma_r((float)x, signp); +} + +_CLC_V_V_VP_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, half, __spirv_ocl_lgamma_r, half, + private, int) + +#endif + +#define __CLC_ADDRSPACE global +#define __CLC_BODY +#include +#undef __CLC_ADDRSPACE + +#define __CLC_ADDRSPACE local +#define __CLC_BODY +#include +#undef __CLC_ADDRSPACE diff --git a/libclc/generic/libspirv/math/lgamma_r.inc b/libclc/generic/libspirv/math/lgamma_r.inc new file mode 100644 index 0000000000000..3d697814f221f --- /dev/null +++ b/libclc/generic/libspirv/math/lgamma_r.inc @@ -0,0 +1,15 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +_CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE +__spirv_ocl_lgamma_r(__CLC_GENTYPE x, __CLC_ADDRSPACE __CLC_INTN *iptr) { + __CLC_INTN private_iptr; + __CLC_GENTYPE ret = __spirv_ocl_lgamma_r(x, &private_iptr); + *iptr = private_iptr; + return ret; +} diff --git a/libclc/generic/libspirv/math/log.cl b/libclc/generic/libspirv/math/log.cl index f400faeaf13af..dab1368109a1c 100644 --- a/libclc/generic/libspirv/math/log.cl +++ b/libclc/generic/libspirv/math/log.cl @@ -6,8 +6,8 @@ // //===----------------------------------------------------------------------===// +#include #include -#include "../../lib/clcmacro.h" /* *log(x) = log2(x) * (1/log2(e)) diff --git a/libclc/generic/libspirv/math/log10.cl b/libclc/generic/libspirv/math/log10.cl index e4407965ae3a0..9a6bcc996759d 100644 --- a/libclc/generic/libspirv/math/log10.cl +++ b/libclc/generic/libspirv/math/log10.cl @@ -7,8 +7,9 @@ //===----------------------------------------------------------------------===// #include -#include "../../lib/clcmacro.h" + #include "tables.h" +#include #ifdef cl_khr_fp64 #pragma OPENCL EXTENSION cl_khr_fp64 : enable diff --git a/libclc/generic/libspirv/math/log1p.cl b/libclc/generic/libspirv/math/log1p.cl new file mode 100644 index 0000000000000..b05873155f73e --- /dev/null +++ b/libclc/generic/libspirv/math/log1p.cl @@ -0,0 +1,168 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include "tables.h" +#include +#include + +_CLC_OVERLOAD _CLC_DEF float __spirv_ocl_log1p(float x) { + float w = x; + uint ux = as_uint(x); + uint ax = ux & EXSIGNBIT_SP32; + + // |x| < 2^-4 + float u2 = MATH_DIVIDE(x, 2.0f + x); + float u = u2 + u2; + float v = u * u; + // 2/(5 * 2^5), 2/(3 * 2^3) + float zsmall = + __spirv_ocl_mad( + -u2, x, __spirv_ocl_mad(v, 0x1.99999ap-7f, 0x1.555556p-4f) * v * u) + + x; + + // |x| >= 2^-4 + ux = as_uint(x + 1.0f); + + int m = (int)((ux >> EXPSHIFTBITS_SP32) & 0xff) - EXPBIAS_SP32; + float mf = (float)m; + uint indx = (ux & 0x007f0000) + ((ux & 0x00008000) << 1); + float F = as_float(indx | 0x3f000000); + + // x > 2^24 + float fg24 = F - as_float(0x3f000000 | (ux & MANTBITS_SP32)); + + // x <= 2^24 + uint xhi = ux & 0xffff8000; + float xh = as_float(xhi); + float xt = (1.0f - xh) + w; + uint xnm = ((~(xhi & 0x7f800000)) - 0x00800000) & 0x7f800000; + xt = xt * as_float(xnm) * 0.5f; + float fl24 = F - as_float(0x3f000000 | (xhi & MANTBITS_SP32)) - xt; + + float f = mf > 24.0f ? fg24 : fl24; + + indx = indx >> 16; + float r = f * USE_TABLE(log_inv_tbl, indx); + + // 1/3, 1/2 + float poly = + __spirv_ocl_mad(__spirv_ocl_mad(r, 0x1.555556p-2f, 0x1.0p-1f), r * r, r); + + const float LOG2_HEAD = 0x1.62e000p-1f; // 0.693115234 + const float LOG2_TAIL = 0x1.0bfbe8p-15f; // 0.0000319461833 + + float2 tv = USE_TABLE(loge_tbl, indx); + float z1 = __spirv_ocl_mad(mf, LOG2_HEAD, tv.s0); + float z2 = __spirv_ocl_mad(mf, LOG2_TAIL, -poly) + tv.s1; + float z = z1 + z2; + + z = ax < 0x3d800000U ? zsmall : z; + + // Edge cases + z = ax >= PINFBITPATT_SP32 ? w : z; + z = w < -1.0f ? as_float(QNANBITPATT_SP32) : z; + z = w == -1.0f ? as_float(NINFBITPATT_SP32) : z; + // fix subnormals + z = ax < 0x33800000 ? x : z; + + return z; +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, float, __spirv_ocl_log1p, float); + +#ifdef cl_khr_fp64 + +#pragma OPENCL EXTENSION cl_khr_fp64 : enable + +_CLC_OVERLOAD _CLC_DEF double __spirv_ocl_log1p(double x) { + // Computes natural log(1+x). Algorithm based on: + // Ping-Tak Peter Tang + // "Table-driven implementation of the logarithm function in IEEE + // floating-point arithmetic" + // ACM Transactions on Mathematical Software (TOMS) + // Volume 16, Issue 4 (December 1990) + // Note that we use a lookup table of size 64 rather than 128, + // and compensate by having extra terms in the minimax polynomial + // for the kernel approximation. + + // Process Inside the threshold now + ulong ux = as_ulong(1.0 + x); + int xexp = ((as_int2(ux).hi >> 20) & 0x7ff) - EXPBIAS_DP64; + double f = as_double(ONEEXPBITS_DP64 | (ux & MANTBITS_DP64)); + + int j = as_int2(ux).hi >> 13; + j = ((0x80 | (j & 0x7e)) >> 1) + (j & 0x1); + double f1 = (double)j * 0x1.0p-6; + j -= 64; + + double f2temp = f - f1; + double m2 = as_double(__spirv_SatConvertSToU_Rulong(0x3ff - xexp) + << EXPSHIFTBITS_DP64); + double f2l = __spirv_ocl_fma(m2, x, m2 - f1); + double f2g = __spirv_ocl_fma(m2, x, -f1) + m2; + double f2 = xexp <= MANTLENGTH_DP64 - 1 ? f2l : f2g; + f2 = (xexp <= -2) || (xexp >= MANTLENGTH_DP64 + 8) ? f2temp : f2; + + double2 tv = USE_TABLE(ln_tbl, j); + double z1 = tv.s0; + double q = tv.s1; + + double u = MATH_DIVIDE(f2, __spirv_ocl_fma(0.5, f2, f1)); + double v = u * u; + + double poly = + v * __spirv_ocl_fma(v, + __spirv_ocl_fma(v, 2.23219810758559851206e-03, + 1.24999999978138668903e-02), + 8.33333333333333593622e-02); + + // log2_lead and log2_tail sum to an extra-precise version of log(2) + const double log2_lead = 6.93147122859954833984e-01; /* 0x3fe62e42e0000000 */ + const double log2_tail = 5.76999904754328540596e-08; /* 0x3e6efa39ef35793c */ + + double z2 = q + __spirv_ocl_fma(u, poly, u); + double dxexp = (double)xexp; + double r1 = __spirv_ocl_fma(dxexp, log2_lead, z1); + double r2 = __spirv_ocl_fma(dxexp, log2_tail, z2); + double result1 = r1 + r2; + + // Process Outside the threshold now + double r = x; + u = r / (2.0 + r); + double correction = r * u; + u = u + u; + v = u * u; + r1 = r; + + poly = __spirv_ocl_fma( + v, + __spirv_ocl_fma(v, + __spirv_ocl_fma(v, 4.34887777707614552256e-04, + 2.23213998791944806202e-03), + 1.25000000037717509602e-02), + 8.33333333333317923934e-02); + + r2 = __spirv_ocl_fma(u * v, poly, -correction); + + // The values exp(-1/16)-1 and exp(1/16)-1 + const double log1p_thresh1 = -0x1.f0540438fd5c3p-5; + const double log1p_thresh2 = 0x1.082b577d34ed8p-4; + double result2 = r1 + r2; + result2 = x < log1p_thresh1 || x > log1p_thresh2 ? result1 : result2; + + result2 = __spirv_IsInf(x) ? x : result2; + result2 = x < -1.0 ? as_double(QNANBITPATT_DP64) : result2; + result2 = x == -1.0 ? as_double(NINFBITPATT_DP64) : result2; + return result2; +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, double, __spirv_ocl_log1p, double); + +#endif // cl_khr_fp64 diff --git a/libclc/generic/libspirv/math/log2.cl b/libclc/generic/libspirv/math/log2.cl index 670dbefd3adeb..46cc5e545aa27 100644 --- a/libclc/generic/libspirv/math/log2.cl +++ b/libclc/generic/libspirv/math/log2.cl @@ -7,8 +7,9 @@ //===----------------------------------------------------------------------===// #include -#include "../../lib/clcmacro.h" + #include "tables.h" +#include #ifdef cl_khr_fp64 #pragma OPENCL EXTENSION cl_khr_fp64 : enable diff --git a/libclc/generic/libspirv/math/log_base.h b/libclc/generic/libspirv/math/log_base.h index 3e51f34594ec3..00dfe970384f5 100644 --- a/libclc/generic/libspirv/math/log_base.h +++ b/libclc/generic/libspirv/math/log_base.h @@ -20,7 +20,7 @@ * THE SOFTWARE. */ -#include "../../lib/math/math.h" +#include /* Algorithm: @@ -316,7 +316,7 @@ __spirv_ocl_log(double x) double ret = is_near ? ret_near : ret_far; ret = __spirv_IsInf(x) ? as_double(PINFBITPATT_DP64) : ret; - ret = __spirv_IsNan(x) | (x < 0.0) ? as_double(QNANBITPATT_DP64) : ret; + ret = __spirv_IsNan(x) || (x < 0.0) ? as_double(QNANBITPATT_DP64) : ret; ret = x == 0.0 ? as_double(NINFBITPATT_DP64) : ret; return ret; } diff --git a/libclc/generic/libspirv/math/logb.cl b/libclc/generic/libspirv/math/logb.cl index b4d949bfc8651..224b7e3042618 100644 --- a/libclc/generic/libspirv/math/logb.cl +++ b/libclc/generic/libspirv/math/logb.cl @@ -7,8 +7,9 @@ //===----------------------------------------------------------------------===// #include -#include "../../lib/clcmacro.h" -#include "../../lib/math/math.h" + +#include +#include _CLC_OVERLOAD _CLC_DEF float __spirv_ocl_logb(float x) { int ax = as_int(x) & EXSIGNBIT_SP32; diff --git a/libclc/generic/include/spirv/math/ilogb.h b/libclc/generic/libspirv/math/maxmag.cl similarity index 77% rename from libclc/generic/include/spirv/math/ilogb.h rename to libclc/generic/libspirv/math/maxmag.cl index bdddb15b1bc0b..268d301da9172 100644 --- a/libclc/generic/include/spirv/math/ilogb.h +++ b/libclc/generic/libspirv/math/maxmag.cl @@ -6,8 +6,8 @@ // //===----------------------------------------------------------------------===// -#define __SPIRV_BODY +#include +#include -#include - -#undef __SPIRV_BODY +#define __CLC_BODY +#include diff --git a/libclc/generic/libspirv/math/maxmag.inc b/libclc/generic/libspirv/math/maxmag.inc new file mode 100644 index 0000000000000..e74e75d16268f --- /dev/null +++ b/libclc/generic/libspirv/math/maxmag.inc @@ -0,0 +1,41 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifdef __CLC_SCALAR +#define __CLC_VECSIZE +#endif + +#define __CLC_CHARN __CLC_XCONCAT(schar, __CLC_VECSIZE) + +#if __CLC_FPSIZE == 64 +#define __CLC_CONVERT_NATN __CLC_XCONCAT(__spirv_SConvert_Rlong, __CLC_VECSIZE) +#elif __CLC_FPSIZE == 32 +#define __CLC_CONVERT_NATN __CLC_XCONCAT(__spirv_SConvert_Rint, __CLC_VECSIZE) +#elif __CLC_FPSIZE == 16 +#define __CLC_CONVERT_NATN __CLC_XCONCAT(__spirv_SConvert_Rshort, __CLC_VECSIZE) +#endif + +_CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE __spirv_ocl_maxmag(__CLC_GENTYPE x, + __CLC_GENTYPE y) { + const __CLC_GENTYPE res = __spirv_ocl_select( + y, x, + __CLC_CONVERT_NATN((__CLC_CHARN)__spirv_FOrdGreaterThan( + __spirv_ocl_fabs(x), __spirv_ocl_fabs(y)))); + return __spirv_ocl_select( + res, __spirv_ocl_fmax(x, y), + __CLC_CONVERT_NATN((__CLC_CHARN)( + __spirv_IsNan(x) | __spirv_IsNan(y) | + __spirv_FOrdEqual(__spirv_ocl_fabs(x), __spirv_ocl_fabs(y))))); +} + +#undef __CLC_CONVERT_CHARN +#undef __CLC_CONVERT_NATN + +#ifdef __CLC_SCALAR +#undef __CLC_VECSIZE +#endif diff --git a/libclc/generic/include/spirv/math/binary_decl_tt.inc b/libclc/generic/libspirv/math/minmag.cl similarity index 77% rename from libclc/generic/include/spirv/math/binary_decl_tt.inc rename to libclc/generic/libspirv/math/minmag.cl index 918d63f61ad28..866c331a2ba37 100644 --- a/libclc/generic/include/spirv/math/binary_decl_tt.inc +++ b/libclc/generic/libspirv/math/minmag.cl @@ -6,4 +6,8 @@ // //===----------------------------------------------------------------------===// -_CLC_OVERLOAD _CLC_DECL __SPIRV_GENTYPE __SPIRV_FUNCTION(__SPIRV_GENTYPE a, __SPIRV_GENTYPE b); +#include +#include + +#define __CLC_BODY +#include diff --git a/libclc/generic/libspirv/math/minmag.inc b/libclc/generic/libspirv/math/minmag.inc new file mode 100644 index 0000000000000..56178269a17e5 --- /dev/null +++ b/libclc/generic/libspirv/math/minmag.inc @@ -0,0 +1,41 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifdef __CLC_SCALAR +#define __CLC_VECSIZE +#endif + +#define __CLC_CHARN __CLC_XCONCAT(schar, __CLC_VECSIZE) + +#if __CLC_FPSIZE == 64 +#define __CLC_CONVERT_NATN __CLC_XCONCAT(__spirv_SConvert_Rlong, __CLC_VECSIZE) +#elif __CLC_FPSIZE == 32 +#define __CLC_CONVERT_NATN __CLC_XCONCAT(__spirv_SConvert_Rint, __CLC_VECSIZE) +#elif __CLC_FPSIZE == 16 +#define __CLC_CONVERT_NATN __CLC_XCONCAT(__spirv_SConvert_Rshort, __CLC_VECSIZE) +#endif + +_CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE __spirv_ocl_minmag(__CLC_GENTYPE x, + __CLC_GENTYPE y) { + const __CLC_GENTYPE res = + __spirv_ocl_select(y, x, + __CLC_CONVERT_NATN((__CLC_CHARN)__spirv_FOrdLessThan( + __spirv_ocl_fabs(x), __spirv_ocl_fabs(y)))); + return __spirv_ocl_select( + res, __spirv_ocl_fmin(x, y), + __CLC_CONVERT_NATN((__CLC_CHARN)( + __spirv_IsNan(x) | __spirv_IsNan(y) | + __spirv_FOrdEqual(__spirv_ocl_fabs(x), __spirv_ocl_fabs(y))))); +} + +#undef __CLC_CONVERT_CHARN +#undef __CLC_CONVERT_NATN + +#ifdef __CLC_SCALAR +#undef __CLC_VECSIZE +#endif diff --git a/libclc/generic/libspirv/math/modf.cl b/libclc/generic/libspirv/math/modf.cl new file mode 100644 index 0000000000000..f38a614a6ce53 --- /dev/null +++ b/libclc/generic/libspirv/math/modf.cl @@ -0,0 +1,15 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include +#include + +#include + +#define __CLC_BODY +#include diff --git a/libclc/generic/libspirv/math/modf.inc b/libclc/generic/libspirv/math/modf.inc new file mode 100644 index 0000000000000..edd4171ac859c --- /dev/null +++ b/libclc/generic/libspirv/math/modf.inc @@ -0,0 +1,45 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#if __CLC_FPSIZE == 64 +#define ZERO 0.0 +#define __CLC_CONVERT_NATN __CLC_XCONCAT(__spirv_SConvert_Rlong, __CLC_VECSIZE) +#elif __CLC_FPSIZE == 32 +#define ZERO 0.0f +#define __CLC_CONVERT_NATN __CLC_XCONCAT(__spirv_SConvert_Rint, __CLC_VECSIZE) +#elif __CLC_FPSIZE == 16 +#define ZERO 0.0h +#define __CLC_CONVERT_NATN __CLC_XCONCAT(__spirv_SConvert_Rshort, __CLC_VECSIZE) +#endif + +#ifdef __CLC_SCALAR +#undef __CLC_CONVERT_NATN +#define __CLC_CONVERT_NATN +#endif + +_CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE __spirv_ocl_modf(__CLC_GENTYPE x, + __CLC_GENTYPE *iptr) { + *iptr = __spirv_ocl_trunc(x); + return __spirv_ocl_copysign( + __CLC_CONVERT_NATN(__spirv_IsInf(x)) ? ZERO : x - *iptr, x); +} + +#define MODF_DEF(addrspace) \ + _CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE __spirv_ocl_modf( \ + __CLC_GENTYPE x, addrspace __CLC_GENTYPE *iptr) { \ + __CLC_GENTYPE private_iptr; \ + __CLC_GENTYPE ret = __spirv_ocl_modf(x, &private_iptr); \ + *iptr = private_iptr; \ + return ret; \ + } + +MODF_DEF(local); +MODF_DEF(global); + +#undef __CLC_CONVERT_NATN +#undef ZERO diff --git a/libclc/generic/libspirv/math/nan.cl b/libclc/generic/libspirv/math/nan.cl new file mode 100644 index 0000000000000..2da5b8edda251 --- /dev/null +++ b/libclc/generic/libspirv/math/nan.cl @@ -0,0 +1,16 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include +#include + +#define __CLC_AS_GENTYPE __CLC_XCONCAT(as_, __CLC_GENTYPE) +#define __CLC_AS_UNSIGNED(TYPE) \ + __CLC_XCONCAT(as_, __CLC_XCONCAT(TYPE, __CLC_VECSIZE)) +#define __CLC_BODY +#include diff --git a/libclc/generic/libspirv/math/nan.inc b/libclc/generic/libspirv/math/nan.inc new file mode 100644 index 0000000000000..d778a82bca519 --- /dev/null +++ b/libclc/generic/libspirv/math/nan.inc @@ -0,0 +1,45 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +#ifdef __CLC_SCALAR +#define __CLC_VECSIZE +#endif + +#if __CLC_FPSIZE == 64 +_CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE +__spirv_ocl_nan(__CLC_XCONCAT(ulong, __CLC_VECSIZE) code) { + return __CLC_AS_GENTYPE(code | 0x7ff0000000000000ul); +} +_CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE +__spirv_ocl_nan(__CLC_XCONCAT(long, __CLC_VECSIZE) code) { + return __spirv_ocl_nan(__CLC_AS_UNSIGNED(ulong)(code)); +} +#elif __CLC_FPSIZE == 32 +_CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE +__spirv_ocl_nan(__CLC_XCONCAT(uint, __CLC_VECSIZE) code) { + return __CLC_AS_GENTYPE(code | 0x7fc00000); +} +_CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE +__spirv_ocl_nan(__CLC_XCONCAT(int, __CLC_VECSIZE) code) { + return __spirv_ocl_nan(__CLC_AS_UNSIGNED(uint)(code)); +} +#elif __CLC_FPSIZE == 16 +_CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE +__spirv_ocl_nan(__CLC_XCONCAT(ushort, __CLC_VECSIZE) code) { + const ushort mask = 0x7e00; + const __CLC_XCONCAT(ushort, __CLC_VECSIZE) res = code | mask; + return __CLC_AS_GENTYPE(res); +} +_CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE +__spirv_ocl_nan(__CLC_XCONCAT(short, __CLC_VECSIZE) code) { + return __spirv_ocl_nan(__CLC_AS_UNSIGNED(ushort)(code)); +} +#endif + +#ifdef __CLC_SCALAR +#undef __CLC_VECSIZE +#endif diff --git a/libclc/generic/include/spirv/math/ldexp.inc b/libclc/generic/libspirv/math/nextafter.cl similarity index 51% rename from libclc/generic/include/spirv/math/ldexp.inc rename to libclc/generic/libspirv/math/nextafter.cl index f5f396915d785..93f0191fefacf 100644 --- a/libclc/generic/include/spirv/math/ldexp.inc +++ b/libclc/generic/libspirv/math/nextafter.cl @@ -6,10 +6,17 @@ // //===----------------------------------------------------------------------===// -_CLC_OVERLOAD _CLC_DECL __SPIRV_GENTYPE __spirv_ocl_ldexp(__SPIRV_GENTYPE x, int n); +#include +#include -#ifndef __SPIRV_SCALAR +_CLC_DEFINE_BINARY_BUILTIN(float, __spirv_ocl_nextafter, __builtin_nextafterf, + float, float) -_CLC_OVERLOAD _CLC_DECL __SPIRV_GENTYPE __spirv_ocl_ldexp(__SPIRV_GENTYPE x, __SPIRV_INTN n); +#ifdef cl_khr_fp64 + +#pragma OPENCL EXTENSION cl_khr_fp64 : enable + +_CLC_DEFINE_BINARY_BUILTIN(double, __spirv_ocl_nextafter, __builtin_nextafter, + double, double) #endif diff --git a/libclc/generic/libspirv/math/pow.cl b/libclc/generic/libspirv/math/pow.cl index 7a39cab88f9fb..6c4f27232b8cb 100644 --- a/libclc/generic/libspirv/math/pow.cl +++ b/libclc/generic/libspirv/math/pow.cl @@ -7,11 +7,11 @@ //===----------------------------------------------------------------------===// #include -#include -#include "config.h" -#include "../../lib/clcmacro.h" -#include "../../lib/math/math.h" +#include +#include +#include +#include #define __CLC_BODY #include diff --git a/libclc/generic/libspirv/math/pow.inc b/libclc/generic/libspirv/math/pow.inc index d7c9394d7d5b3..6c0a215ec7bc7 100644 --- a/libclc/generic/libspirv/math/pow.inc +++ b/libclc/generic/libspirv/math/pow.inc @@ -8,11 +8,6 @@ #include -// TODO: Enable half precision when the sw routine is implemented. -#if __CLC_FPSIZE > 16 - _CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE __spirv_ocl_pow(__CLC_GENTYPE x, __CLC_GENTYPE y) { return __clc_pow(x, y); } - -#endif diff --git a/libclc/generic/libspirv/math/pown.cl b/libclc/generic/libspirv/math/pown.cl new file mode 100644 index 0000000000000..70fb7069a0a18 --- /dev/null +++ b/libclc/generic/libspirv/math/pown.cl @@ -0,0 +1,14 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include + +#define __CLC_BODY +#include diff --git a/libclc/generic/include/spirv/math/pown.inc b/libclc/generic/libspirv/math/pown.inc similarity index 68% rename from libclc/generic/include/spirv/math/pown.inc rename to libclc/generic/libspirv/math/pown.inc index a836218fb10e8..3fd7c0799a407 100644 --- a/libclc/generic/include/spirv/math/pown.inc +++ b/libclc/generic/libspirv/math/pown.inc @@ -6,4 +6,7 @@ // //===----------------------------------------------------------------------===// -_CLC_OVERLOAD _CLC_DECL __SPIRV_GENTYPE __spirv_ocl_pown(__SPIRV_GENTYPE a, __SPIRV_INTN b); +_CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE __spirv_ocl_pown(__CLC_GENTYPE x, + __CLC_INTN y) { + return __clc_pown(x, y); +} diff --git a/libclc/generic/include/spirv/math/acospi.h b/libclc/generic/libspirv/math/powr.cl similarity index 65% rename from libclc/generic/include/spirv/math/acospi.h rename to libclc/generic/libspirv/math/powr.cl index 1720b13ad6e90..6356c313cb22e 100644 --- a/libclc/generic/include/spirv/math/acospi.h +++ b/libclc/generic/libspirv/math/powr.cl @@ -6,10 +6,11 @@ // //===----------------------------------------------------------------------===// -#define __SPIRV_BODY -#define __SPIRV_FUNCTION __spirv_ocl_acospi +#include -#include +#include -#undef __SPIRV_BODY -#undef __SPIRV_FUNCTION +#define __CLC_FUNC __spirv_ocl_powr +#define __CLC_SW_FUNC __clc_powr +#define __CLC_BODY +#include diff --git a/libclc/generic/libspirv/math/remainer.cl b/libclc/generic/libspirv/math/remainer.cl new file mode 100644 index 0000000000000..354a004ecca7a --- /dev/null +++ b/libclc/generic/libspirv/math/remainer.cl @@ -0,0 +1,16 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include + +#define __CLC_FUNC __spirv_ocl_remainder +#define __CLC_SW_FUNC __clc_remainder +#define __CLC_BODY +#include diff --git a/libclc/generic/libspirv/math/remquo.cl b/libclc/generic/libspirv/math/remquo.cl new file mode 100644 index 0000000000000..3c12d082b4614 --- /dev/null +++ b/libclc/generic/libspirv/math/remquo.cl @@ -0,0 +1,26 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include + +#define __CLC_BODY +#define __CLC_ADDRESS_SPACE global +#include +#undef __CLC_ADDRESS_SPACE + +#define __CLC_BODY +#define __CLC_ADDRESS_SPACE local +#include +#undef __CLC_ADDRESS_SPACE + +#define __CLC_BODY +#define __CLC_ADDRESS_SPACE private +#include +#undef __CLC_ADDRESS_SPACE diff --git a/libclc/generic/include/spirv/math/remquo.inc b/libclc/generic/libspirv/math/remquo.inc similarity index 60% rename from libclc/generic/include/spirv/math/remquo.inc rename to libclc/generic/libspirv/math/remquo.inc index 0ab20b3d31459..f94fb6586b621 100644 --- a/libclc/generic/include/spirv/math/remquo.inc +++ b/libclc/generic/libspirv/math/remquo.inc @@ -6,4 +6,10 @@ // //===----------------------------------------------------------------------===// -_CLC_OVERLOAD _CLC_DECL __SPIRV_GENTYPE __SPIRV_FUNCTION(__SPIRV_GENTYPE x, __SPIRV_GENTYPE y, __SPIRV_ADDRESS_SPACE __SPIRV_INTN *q); +_CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE __spirv_ocl_remquo( + __CLC_GENTYPE x, __CLC_GENTYPE y, __CLC_ADDRESS_SPACE __CLC_INTN *q) { + __CLC_INTN local_q; + __CLC_GENTYPE ret = __clc_remquo(x, y, &local_q); + *q = local_q; + return ret; +} diff --git a/libclc/generic/libspirv/math/rint.cl b/libclc/generic/libspirv/math/rint.cl index 2228826770e33..824f64285f9d8 100644 --- a/libclc/generic/libspirv/math/rint.cl +++ b/libclc/generic/libspirv/math/rint.cl @@ -6,14 +6,14 @@ // //===----------------------------------------------------------------------===// +#include #include -#include "../../lib/clcmacro.h" // Map the llvm intrinsic to an OpenCL function. #define __CLC_FUNCTION __clc___spirv_ocl_rint #define __CLC_INTRINSIC "llvm.rint" -#include "math/unary_intrin.inc" +#include #undef __CLC_FUNCTION #define __CLC_FUNCTION __spirv_ocl_rint -#include "unary_builtin.inc" +#include diff --git a/libclc/generic/libspirv/math/rootn.cl b/libclc/generic/libspirv/math/rootn.cl new file mode 100644 index 0000000000000..9587f388cdf76 --- /dev/null +++ b/libclc/generic/libspirv/math/rootn.cl @@ -0,0 +1,14 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include + +#define __CLC_BODY +#include diff --git a/libclc/generic/include/spirv/math/rootn.inc b/libclc/generic/libspirv/math/rootn.inc similarity index 68% rename from libclc/generic/include/spirv/math/rootn.inc rename to libclc/generic/libspirv/math/rootn.inc index 6ec945d39d588..c7c0feacc45b9 100644 --- a/libclc/generic/include/spirv/math/rootn.inc +++ b/libclc/generic/libspirv/math/rootn.inc @@ -6,4 +6,7 @@ // //===----------------------------------------------------------------------===// -_CLC_OVERLOAD _CLC_DECL __SPIRV_GENTYPE __spirv_ocl_rootn(__SPIRV_GENTYPE a, __SPIRV_INTN b); +_CLC_OVERLOAD _CLC_DEF __CLC_GENTYPE __spirv_ocl_rootn(__CLC_GENTYPE x, + __CLC_INTN y) { + return __clc_rootn(x, y); +} diff --git a/libclc/generic/libspirv/math/round.cl b/libclc/generic/libspirv/math/round.cl index 5b272e432a616..63437fb6bab3e 100644 --- a/libclc/generic/libspirv/math/round.cl +++ b/libclc/generic/libspirv/math/round.cl @@ -6,14 +6,14 @@ // //===----------------------------------------------------------------------===// +#include #include -#include "../../lib/clcmacro.h" // Map the llvm intrinsic to an OpenCL function. #define __CLC_FUNCTION __clc___spirv_ocl_round #define __CLC_INTRINSIC "llvm.round" -#include "math/unary_intrin.inc" +#include #undef __CLC_FUNCTION #define __CLC_FUNCTION __spirv_ocl_round -#include "unary_builtin.inc" +#include diff --git a/libclc/generic/libspirv/math/sin.cl b/libclc/generic/libspirv/math/sin.cl index 7f6e4e7fd1b1f..8e4f7c06577be 100644 --- a/libclc/generic/libspirv/math/sin.cl +++ b/libclc/generic/libspirv/math/sin.cl @@ -9,8 +9,8 @@ #include #include "sincos_helpers.h" -#include "../../lib/math/math.h" -#include "../../lib/clcmacro.h" +#include +#include _CLC_OVERLOAD _CLC_DEF float __spirv_ocl_sin(float x) { @@ -57,7 +57,8 @@ _CLC_OVERLOAD _CLC_DEF double __spirv_ocl_sin(double x) { int2 s = as_int2(regn & 1 ? sc.hi : sc.lo); s.hi ^= ((regn > 1) << 31) ^ ((x < 0.0) << 31); - return __spirv_IsInf(x) | __spirv_IsNan(x) ? as_double(QNANBITPATT_DP64) : as_double(s); + return __spirv_IsInf(x) || __spirv_IsNan(x) ? as_double(QNANBITPATT_DP64) + : as_double(s); } _CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, double, __spirv_ocl_sin, double); diff --git a/libclc/generic/libspirv/math/sincos.inc b/libclc/generic/libspirv/math/sincos.inc index e1db6dfa3e0a5..33f964be33768 100644 --- a/libclc/generic/libspirv/math/sincos.inc +++ b/libclc/generic/libspirv/math/sincos.inc @@ -6,8 +6,6 @@ // //===----------------------------------------------------------------------===// -// TODO: Enable half precision when sin/cos is implemented -#if __CLC_FPSIZE > 16 #define __CLC_DECLARE_SINCOS(ADDRSPACE, TYPE) \ _CLC_OVERLOAD _CLC_DEF TYPE __spirv_ocl_sincos (TYPE x, ADDRSPACE TYPE * cosval) { \ *cosval = __spirv_ocl_cos(x); \ @@ -19,4 +17,3 @@ __CLC_DECLARE_SINCOS(local, __CLC_GENTYPE) __CLC_DECLARE_SINCOS(private, __CLC_GENTYPE) #undef __CLC_DECLARE_SINCOS -#endif diff --git a/libclc/generic/libspirv/math/sincos_helpers.cl b/libclc/generic/libspirv/math/sincos_helpers.cl index adecd79f1c420..42856edba4565 100644 --- a/libclc/generic/libspirv/math/sincos_helpers.cl +++ b/libclc/generic/libspirv/math/sincos_helpers.cl @@ -24,8 +24,8 @@ #include #include "sincos_helpers.h" -#include "../../lib/math/math.h" #include "tables.h" +#include #define bitalign(hi, lo, shift) ((hi) << (32 - (shift))) | ((lo) >> (shift)); @@ -94,7 +94,7 @@ _CLC_DEF float __clc_cosf_piby4(float x, float y) { // 0.78125 > |x| >= 0.3 float xby4 = as_float(ix - 0x01000000); - qx = (ix >= 0x3e99999a) & (ix <= 0x3f480000) ? xby4 : qx; + qx = (ix >= 0x3e99999a) && (ix <= 0x3f480000) ? xby4 : qx; // x > 0.78125 qx = ix > 0x3f480000 ? 0.28125f : qx; diff --git a/libclc/generic/libspirv/math/sincos_helpers.h b/libclc/generic/libspirv/math/sincos_helpers.h index 81ce3289c4de3..8b300d786bce5 100644 --- a/libclc/generic/libspirv/math/sincos_helpers.h +++ b/libclc/generic/libspirv/math/sincos_helpers.h @@ -20,7 +20,7 @@ * THE SOFTWARE. */ -#include "func.h" +#include _CLC_DECL float __clc_sinf_piby4(float x, float y); _CLC_DECL float __clc_cosf_piby4(float x, float y); diff --git a/libclc/generic/libspirv/math/sinh.cl b/libclc/generic/libspirv/math/sinh.cl new file mode 100644 index 0000000000000..b98c8512027c7 --- /dev/null +++ b/libclc/generic/libspirv/math/sinh.cl @@ -0,0 +1,220 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include "tables.h" +#include +#include + +_CLC_OVERLOAD _CLC_DEF float __spirv_ocl_sinh(float x) { + // After dealing with special cases the computation is split into regions as + // follows. abs(x) >= max_sinh_arg: sinh(x) = sign(x)*Inf abs(x) >= + // small_threshold: sinh(x) = sign(x)*exp(abs(x))/2 computed using the + // splitexp and scaleDouble functions as for exp_amd(). abs(x) < + // small_threshold: compute p = exp(y) - 1 and then z = 0.5*(p+(p/(p+1.0))) + // sinh(x) is then sign(x)*z. + + const float max_sinh_arg = 0x1.65a9fap+6f; + const float small_threshold = 0x1.0a2b24p+3f; + + uint ux = as_uint(x); + uint aux = ux & EXSIGNBIT_SP32; + uint xs = ux ^ aux; + float y = as_float(aux); + + // We find the integer part y0 of y and the increment dy = y - y0. We then + // compute z = sinh(y) = sinh(y0)cosh(dy) + cosh(y0)sinh(dy) where sinh(y0) + // and cosh(y0) are tabulated above. + int ind = (int)y; + ind = (uint)ind > 36U ? 0 : ind; + + float dy = y - ind; + float dy2 = dy * dy; + + float sdy = __spirv_ocl_mad( + dy2, + __spirv_ocl_mad( + dy2, + __spirv_ocl_mad( + dy2, + __spirv_ocl_mad( + dy2, + __spirv_ocl_mad( + dy2, + __spirv_ocl_mad(dy2, 0.7746188980094184251527126e-12f, + 0.160576793121939886190847e-9f), + 0.250521176994133472333666e-7f), + 0.275573191913636406057211e-5f), + 0.198412698413242405162014e-3f), + 0.833333333333329931873097e-2f), + 0.166666666666666667013899e0f); + sdy = __spirv_ocl_mad(sdy, dy * dy2, dy); + + float cdy = __spirv_ocl_mad( + dy2, + __spirv_ocl_mad( + dy2, + __spirv_ocl_mad( + dy2, + __spirv_ocl_mad( + dy2, + __spirv_ocl_mad( + dy2, + __spirv_ocl_mad(dy2, 0.1163921388172173692062032e-10f, + 0.208744349831471353536305e-8f), + 0.275573350756016588011357e-6f), + 0.248015872460622433115785e-4f), + 0.138888888889814854814536e-2f), + 0.416666666666660876512776e-1f), + 0.500000000000000005911074e0f); + cdy = __spirv_ocl_mad(cdy, dy2, 1.0f); + + float2 tv = USE_TABLE(sinhcosh_tbl, ind); + float z = __spirv_ocl_mad(tv.s1, sdy, tv.s0 * cdy); + z = as_float(xs | as_uint(z)); + + // When y is large enough so that the negative exponential is negligible, + // so sinh(y) is approximated by sign(x)*exp(y)/2. + float t = __spirv_ocl_exp(y - 0x1.62e500p-1f); + float zsmall = __spirv_ocl_mad(0x1.a0210ep-18f, t, t); + zsmall = as_float(xs | as_uint(zsmall)); + z = y >= small_threshold ? zsmall : z; + + // Corner cases + float zinf = as_float(PINFBITPATT_SP32 | xs); + z = y >= max_sinh_arg ? zinf : z; + z = aux > PINFBITPATT_SP32 || aux < 0x38800000U ? x : z; + + return z; +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, float, __spirv_ocl_sinh, float); + +#ifdef cl_khr_fp64 +#pragma OPENCL EXTENSION cl_khr_fp64 : enable + +_CLC_OVERLOAD _CLC_DEF double __spirv_ocl_sinh(double x) { + // After dealing with special cases the computation is split into + // regions as follows: + // + // abs(x) >= max_sinh_arg: + // sinh(x) = sign(x)*Inf + // + // abs(x) >= small_threshold: + // sinh(x) = sign(x)*exp(abs(x))/2 computed using the + // splitexp and scaleDouble functions as for exp_amd(). + // + // abs(x) < small_threshold: + // compute p = exp(y) - 1 and then z = 0.5*(p+(p/(p+1.0))) + // sinh(x) is then sign(x)*z. + + const double max_sinh_arg = 7.10475860073943977113e+02; // 0x408633ce8fb9f87e + + // This is where exp(-x) is insignificant compared to exp(x) = ln(2^27) + const double small_threshold = 0x1.2b708872320e2p+4; + + double y = __spirv_ocl_fabs(x); + + // In this range we find the integer part y0 of y + // and the increment dy = y - y0. We then compute + // z = sinh(y) = sinh(y0)cosh(dy) + cosh(y0)sinh(dy) + // where sinh(y0) and cosh(y0) are obtained from tables + + int ind = __spirv_ocl_s_min((int)y, 36); + double dy = y - ind; + double dy2 = dy * dy; + + double sdy = + dy * dy2 * + __spirv_ocl_fma( + dy2, + __spirv_ocl_fma( + dy2, + __spirv_ocl_fma( + dy2, + __spirv_ocl_fma( + dy2, + __spirv_ocl_fma( + dy2, + __spirv_ocl_fma(dy2, 0.7746188980094184251527126e-12, + 0.160576793121939886190847e-9), + 0.250521176994133472333666e-7), + 0.275573191913636406057211e-5), + 0.198412698413242405162014e-3), + 0.833333333333329931873097e-2), + 0.166666666666666667013899e0); + + double cdy = + dy2 * + __spirv_ocl_fma( + dy2, + __spirv_ocl_fma( + dy2, + __spirv_ocl_fma( + dy2, + __spirv_ocl_fma( + dy2, + __spirv_ocl_fma( + dy2, + __spirv_ocl_fma(dy2, 0.1163921388172173692062032e-10, + 0.208744349831471353536305e-8), + 0.275573350756016588011357e-6), + 0.248015872460622433115785e-4), + 0.138888888889814854814536e-2), + 0.416666666666660876512776e-1), + 0.500000000000000005911074e0); + + // At this point sinh(dy) is approximated by dy + sdy. + // Shift some significant bits from dy to sdy. + double sdy1 = as_double(as_ulong(dy) & 0xfffffffff8000000UL); + double sdy2 = sdy + (dy - sdy1); + + double2 tv = USE_TABLE(cosh_tbl, ind); + double cl = tv.s0; + double ct = tv.s1; + tv = USE_TABLE(sinh_tbl, ind); + double sl = tv.s0; + double st = tv.s1; + + double z = __spirv_ocl_fma( + cl, sdy1, + __spirv_ocl_fma( + sl, cdy, + __spirv_ocl_fma( + cl, sdy2, + __spirv_ocl_fma(ct, sdy1, + __spirv_ocl_fma(st, cdy, ct * sdy2)) + + st))) + + sl; + + // Other cases + z = (y < 0x1.0p-28) || __spirv_IsNan(x) || __spirv_IsInf(x) ? y : z; + + double t = __spirv_ocl_exp(y - 0x1.62e42fefa3800p-1); + t = __spirv_ocl_fma(t, -0x1.ef35793c76641p-45, t); + z = y >= small_threshold ? t : z; + z = y >= max_sinh_arg ? as_double(PINFBITPATT_DP64) : z; + + return __spirv_ocl_copysign(z, x); +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, double, __spirv_ocl_sinh, double) + +#endif + +#ifdef cl_khr_fp16 +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +_CLC_DEF _CLC_OVERLOAD half __spirv_ocl_sinh(half x) { + return __spirv_ocl_sinh((float)x); +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, half, __spirv_ocl_sinh, half) + +#endif diff --git a/libclc/generic/libspirv/math/sinpi.cl b/libclc/generic/libspirv/math/sinpi.cl index b9cba209b7c2c..c2b273e1fcdd8 100644 --- a/libclc/generic/libspirv/math/sinpi.cl +++ b/libclc/generic/libspirv/math/sinpi.cl @@ -8,9 +8,9 @@ #include -#include "../../lib/math/math.h" -#include "../../lib/clcmacro.h" #include "sincospiF_piby4.h" +#include +#include #ifdef cl_khr_fp64 #include "sincosD_piby4.h" #endif diff --git a/libclc/generic/libspirv/math/sqrt.cl b/libclc/generic/libspirv/math/sqrt.cl index bb6fb598ac39d..2355594ba189c 100644 --- a/libclc/generic/libspirv/math/sqrt.cl +++ b/libclc/generic/libspirv/math/sqrt.cl @@ -12,4 +12,4 @@ #define __CLC_BUILTIN __clc_sqrt #define __CLC_FUNCTION __spirv_ocl_sqrt -#include "unary_builtin.inc" +#include diff --git a/libclc/generic/libspirv/math/tan.cl b/libclc/generic/libspirv/math/tan.cl new file mode 100644 index 0000000000000..e84a6acdc34bb --- /dev/null +++ b/libclc/generic/libspirv/math/tan.cl @@ -0,0 +1,17 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include + +#define __CLC_FUNC __spirv_ocl_tan +#define __CLC_SW_FUNC __clc_tan +#define __CLC_BODY +#include +#undef __CLC_SW_FUNC diff --git a/libclc/generic/libspirv/math/tanh.cl b/libclc/generic/libspirv/math/tanh.cl new file mode 100644 index 0000000000000..a949d1392aca1 --- /dev/null +++ b/libclc/generic/libspirv/math/tanh.cl @@ -0,0 +1,153 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include +#include + +_CLC_OVERLOAD _CLC_DEF float __spirv_ocl_tanh(float x) { + // The definition of tanh(x) is sinh(x)/cosh(x), which is also equivalent + // to the following three formulae: + // 1. (exp(x) - exp(-x))/(exp(x) + exp(-x)) + // 2. (1 - (2/(exp(2*x) + 1 ))) + // 3. (exp(2*x) - 1)/(exp(2*x) + 1) + // but computationally, some formulae are better on some ranges. + + const float large_threshold = 0x1.0a2b24p+3f; + + uint ux = as_uint(x); + uint aux = ux & EXSIGNBIT_SP32; + uint xs = ux ^ aux; + + float y = as_float(aux); + float y2 = y * y; + + float a1 = __spirv_ocl_mad( + y2, + __spirv_ocl_mad(y2, 0.4891631088530669873e-4F, -0.14628356048797849e-2F), + -0.28192806108402678e0F); + float b1 = + __spirv_ocl_mad(y2, 0.3427017942262751343e0F, 0.845784192581041099e0F); + + float a2 = __spirv_ocl_mad( + y2, + __spirv_ocl_mad(y2, 0.3827534993599483396e-4F, -0.12325644183611929e-2F), + -0.24069858695196524e0F); + float b2 = + __spirv_ocl_mad(y2, 0.292529068698052819e0F, 0.72209738473684982e0F); + + int c = y < 0.9f; + float a = c ? a1 : a2; + float b = c ? b1 : b2; + float zlo = __spirv_ocl_mad(MATH_DIVIDE(a, b), y * y2, y); + + float p = __spirv_ocl_exp(2.0f * y) + 1.0f; + float zhi = 1.0F - MATH_DIVIDE(2.0F, p); + + float z = y <= 1.0f ? zlo : zhi; + z = as_float(xs | as_uint(z)); + + // Edge cases + float sone = as_float(0x3f800000U | xs); + z = y > large_threshold ? sone : z; + z = aux < 0x39000000 || aux > 0x7f800000 ? x : z; + + return z; +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, float, __spirv_ocl_tanh, float); + +#ifdef cl_khr_fp64 + +#pragma OPENCL EXTENSION cl_khr_fp64 : enable + +_CLC_OVERLOAD _CLC_DEF double __spirv_ocl_tanh(double x) { + // The definition of tanh(x) is sinh(x)/cosh(x), which is also equivalent + // to the following three formulae: + // 1. (exp(x) - exp(-x))/(exp(x) + exp(-x)) + // 2. (1 - (2/(exp(2*x) + 1 ))) + // 3. (exp(2*x) - 1)/(exp(2*x) + 1) + // but computationally, some formulae are better on some ranges. + + // The point at which e^-x is insignificant compared to e^x = ln(2^27) + const double large_threshold = 0x1.2b708872320e2p+4; + + ulong ux = as_ulong(x); + ulong ax = ux & ~SIGNBIT_DP64; + ulong sx = ux ^ ax; + double y = as_double(ax); + double y2 = y * y; + + // y < 0.9 + double znl = __spirv_ocl_fma( + y2, + __spirv_ocl_fma(y2, + __spirv_ocl_fma(y2, -0.142077926378834722618091e-7, + -0.200047621071909498730453e-3), + -0.176016349003044679402273e-1), + -0.274030424656179760118928e0); + + double zdl = __spirv_ocl_fma( + y2, + __spirv_ocl_fma(y2, + __spirv_ocl_fma(y2, 0.2091140262529164482568557e-3, + 0.201562166026937652780575e-1), + 0.381641414288328849317962e0), + 0.822091273968539282568011e0); + + // 0.9 <= y <= 1 + double znm = __spirv_ocl_fma( + y2, + __spirv_ocl_fma(y2, + __spirv_ocl_fma(y2, -0.115475878996143396378318e-7, + -0.165597043903549960486816e-3), + -0.146173047288731678404066e-1), + -0.227793870659088295252442e0); + + double zdm = __spirv_ocl_fma( + y2, + __spirv_ocl_fma(y2, + __spirv_ocl_fma(y2, 0.173076050126225961768710e-3, + 0.167358775461896562588695e-1), + 0.317204558977294374244770e0), + 0.683381611977295894959554e0); + + int c = y < 0.9; + double zn = c ? znl : znm; + double zd = c ? zdl : zdm; + double z = y + y * y2 * MATH_DIVIDE(zn, zd); + + // y > 1 + double p = __spirv_ocl_exp(2.0 * y) + 1.0; + double zg = 1.0 - 2.0 / p; + + z = y > 1.0 ? zg : z; + + // Other cases + z = y < 0x1.0p-28 || ax > PINFBITPATT_DP64 ? x : z; + + z = y > large_threshold ? 1.0 : z; + + return as_double(sx | as_ulong(z)); +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, double, __spirv_ocl_tanh, double); + +#endif // cl_khr_fp64 + +#ifdef cl_khr_fp16 +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +_CLC_DEF _CLC_OVERLOAD half __spirv_ocl_tanh(half x) { + return __spirv_ocl_tanh((float)x); +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, half, __spirv_ocl_tanh, half) + +#endif diff --git a/libclc/generic/libspirv/math/tanpi.cl b/libclc/generic/libspirv/math/tanpi.cl new file mode 100644 index 0000000000000..8b7c5e42fb3b0 --- /dev/null +++ b/libclc/generic/libspirv/math/tanpi.cl @@ -0,0 +1,17 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include + +#define __CLC_FUNC __spirv_ocl_tanpi +#define __CLC_SW_FUNC __clc_tanpi +#define __CLC_BODY +#include +#undef __CLC_SW_FUNC diff --git a/libclc/generic/libspirv/math/tgamma.cl b/libclc/generic/libspirv/math/tgamma.cl new file mode 100644 index 0000000000000..b0ef011d3d299 --- /dev/null +++ b/libclc/generic/libspirv/math/tgamma.cl @@ -0,0 +1,68 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include +#include + +_CLC_OVERLOAD _CLC_DEF float __spirv_ocl_tgamma(float x) { + const float pi = 3.1415926535897932384626433832795f; + float ax = __spirv_ocl_fabs(x); + float lg = __spirv_ocl_lgamma(ax); + float g = __spirv_ocl_exp(lg); + + if (x < 0.0f) { + float z = __spirv_ocl_sinpi(x); + g = g * ax * z; + g = pi / g; + g = g == 0 ? as_float(PINFBITPATT_SP32) : g; + g = z == 0 ? as_float(QNANBITPATT_SP32) : g; + } + + return g; +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, float, __spirv_ocl_tgamma, float); + +#ifdef cl_khr_fp64 + +#pragma OPENCL EXTENSION cl_khr_fp64 : enable + +_CLC_OVERLOAD _CLC_DEF double __spirv_ocl_tgamma(double x) { + const double pi = 3.1415926535897932384626433832795; + double ax = __spirv_ocl_fabs(x); + double lg = __spirv_ocl_lgamma(ax); + double g = __spirv_ocl_exp(lg); + + if (x < 0.0) { + double z = __spirv_ocl_sinpi(x); + g = g * ax * z; + g = pi / g; + g = g == 0 ? as_double(PINFBITPATT_DP64) : g; + g = z == 0 ? as_double(QNANBITPATT_DP64) : g; + } + + return g; +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, double, __spirv_ocl_tgamma, + double); + +#endif + +#ifdef cl_khr_fp16 +#pragma OPENCL EXTENSION cl_khr_fp16 : enable + +_CLC_DEF _CLC_OVERLOAD half __spirv_ocl_tgamma(half x) { + return __spirv_ocl_tgamma((float)x); +} + +_CLC_UNARY_VECTORIZE(_CLC_OVERLOAD _CLC_DEF, half, __spirv_ocl_tgamma, half) + +#endif diff --git a/libclc/generic/libspirv/math/trunc.cl b/libclc/generic/libspirv/math/trunc.cl index 8365f39beed26..ea110d8fbcad7 100644 --- a/libclc/generic/libspirv/math/trunc.cl +++ b/libclc/generic/libspirv/math/trunc.cl @@ -6,14 +6,14 @@ // //===----------------------------------------------------------------------===// +#include #include -#include "../../lib/clcmacro.h" // Map the llvm intrinsic to an OpenCL function. #define __CLC_FUNCTION __clc___spirv_ocl_trunc #define __CLC_INTRINSIC "llvm.trunc" -#include "math/unary_intrin.inc" +#include #undef __CLC_FUNCTION #define __CLC_FUNCTION __spirv_ocl_trunc -#include "unary_builtin.inc" +#include diff --git a/libclc/test/binding/ocl/acos.cl b/libclc/test/binding/ocl/acos.cl new file mode 100644 index 0000000000000..211bf56d5f9c8 --- /dev/null +++ b/libclc/test/binding/ocl/acos.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_acos(__clc_fp32_t args_0) { + return __spirv_ocl_acos(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_acos(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_acos(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_acos(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_acos(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_acos(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_acos(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_acos(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_acos(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_acos(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_acos(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_acos(__clc_fp64_t args_0) { + return __spirv_ocl_acos(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_acos(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_acos(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_acos(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_acos(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_acos(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_acos(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_acos(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_acos(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_acos(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_acos(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_acos(__clc_fp16_t args_0) { + return __spirv_ocl_acos(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_acos(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_acos(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_acos(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_acos(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_acos(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_acos(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_acos(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_acos(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_acos(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_acos(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/acosh.cl b/libclc/test/binding/ocl/acosh.cl new file mode 100644 index 0000000000000..ac841636b5805 --- /dev/null +++ b/libclc/test/binding/ocl/acosh.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_acosh(__clc_fp32_t args_0) { + return __spirv_ocl_acosh(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_acosh(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_acosh(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_acosh(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_acosh(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_acosh(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_acosh(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_acosh(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_acosh(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_acosh(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_acosh(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_acosh(__clc_fp64_t args_0) { + return __spirv_ocl_acosh(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_acosh(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_acosh(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_acosh(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_acosh(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_acosh(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_acosh(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_acosh(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_acosh(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_acosh(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_acosh(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_acosh(__clc_fp16_t args_0) { + return __spirv_ocl_acosh(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_acosh(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_acosh(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_acosh(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_acosh(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_acosh(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_acosh(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_acosh(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_acosh(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_acosh(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_acosh(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/acospi.cl b/libclc/test/binding/ocl/acospi.cl new file mode 100644 index 0000000000000..0139024065ad3 --- /dev/null +++ b/libclc/test/binding/ocl/acospi.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_acospi(__clc_fp32_t args_0) { + return __spirv_ocl_acospi(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_acospi(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_acospi(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_acospi(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_acospi(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_acospi(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_acospi(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_acospi(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_acospi(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_acospi(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_acospi(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_acospi(__clc_fp64_t args_0) { + return __spirv_ocl_acospi(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_acospi(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_acospi(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_acospi(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_acospi(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_acospi(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_acospi(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_acospi(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_acospi(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_acospi(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_acospi(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_acospi(__clc_fp16_t args_0) { + return __spirv_ocl_acospi(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_acospi(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_acospi(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_acospi(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_acospi(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_acospi(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_acospi(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_acospi(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_acospi(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_acospi(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_acospi(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/asin.cl b/libclc/test/binding/ocl/asin.cl new file mode 100644 index 0000000000000..fea4361926387 --- /dev/null +++ b/libclc/test/binding/ocl/asin.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_asin(__clc_fp32_t args_0) { + return __spirv_ocl_asin(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_asin(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_asin(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_asin(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_asin(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_asin(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_asin(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_asin(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_asin(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_asin(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_asin(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_asin(__clc_fp64_t args_0) { + return __spirv_ocl_asin(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_asin(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_asin(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_asin(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_asin(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_asin(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_asin(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_asin(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_asin(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_asin(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_asin(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_asin(__clc_fp16_t args_0) { + return __spirv_ocl_asin(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_asin(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_asin(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_asin(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_asin(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_asin(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_asin(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_asin(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_asin(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_asin(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_asin(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/asinh.cl b/libclc/test/binding/ocl/asinh.cl new file mode 100644 index 0000000000000..b796d44874193 --- /dev/null +++ b/libclc/test/binding/ocl/asinh.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_asinh(__clc_fp32_t args_0) { + return __spirv_ocl_asinh(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_asinh(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_asinh(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_asinh(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_asinh(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_asinh(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_asinh(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_asinh(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_asinh(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_asinh(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_asinh(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_asinh(__clc_fp64_t args_0) { + return __spirv_ocl_asinh(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_asinh(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_asinh(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_asinh(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_asinh(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_asinh(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_asinh(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_asinh(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_asinh(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_asinh(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_asinh(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_asinh(__clc_fp16_t args_0) { + return __spirv_ocl_asinh(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_asinh(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_asinh(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_asinh(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_asinh(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_asinh(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_asinh(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_asinh(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_asinh(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_asinh(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_asinh(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/asinpi.cl b/libclc/test/binding/ocl/asinpi.cl new file mode 100644 index 0000000000000..1fc2e256b9595 --- /dev/null +++ b/libclc/test/binding/ocl/asinpi.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_asinpi(__clc_fp32_t args_0) { + return __spirv_ocl_asinpi(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_asinpi(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_asinpi(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_asinpi(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_asinpi(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_asinpi(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_asinpi(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_asinpi(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_asinpi(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_asinpi(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_asinpi(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_asinpi(__clc_fp64_t args_0) { + return __spirv_ocl_asinpi(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_asinpi(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_asinpi(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_asinpi(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_asinpi(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_asinpi(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_asinpi(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_asinpi(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_asinpi(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_asinpi(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_asinpi(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_asinpi(__clc_fp16_t args_0) { + return __spirv_ocl_asinpi(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_asinpi(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_asinpi(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_asinpi(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_asinpi(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_asinpi(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_asinpi(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_asinpi(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_asinpi(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_asinpi(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_asinpi(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/atan.cl b/libclc/test/binding/ocl/atan.cl new file mode 100644 index 0000000000000..a54e9bdbecad6 --- /dev/null +++ b/libclc/test/binding/ocl/atan.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_atan(__clc_fp32_t args_0) { + return __spirv_ocl_atan(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_atan(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_atan(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_atan(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_atan(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_atan(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_atan(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_atan(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_atan(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_atan(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_atan(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_atan(__clc_fp64_t args_0) { + return __spirv_ocl_atan(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_atan(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_atan(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_atan(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_atan(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_atan(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_atan(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_atan(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_atan(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_atan(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_atan(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_atan(__clc_fp16_t args_0) { + return __spirv_ocl_atan(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_atan(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_atan(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_atan(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_atan(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_atan(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_atan(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_atan(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_atan(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_atan(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_atan(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/atan2.cl b/libclc/test/binding/ocl/atan2.cl new file mode 100644 index 0000000000000..621ddcb4ebc27 --- /dev/null +++ b/libclc/test/binding/ocl/atan2.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_atan2(__clc_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_ocl_atan2(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_atan2(__clc_vec2_fp32_t args_0, __clc_vec2_fp32_t args_1) { + return __spirv_ocl_atan2(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_atan2(__clc_vec3_fp32_t args_0, __clc_vec3_fp32_t args_1) { + return __spirv_ocl_atan2(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_atan2(__clc_vec4_fp32_t args_0, __clc_vec4_fp32_t args_1) { + return __spirv_ocl_atan2(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_atan2(__clc_vec8_fp32_t args_0, __clc_vec8_fp32_t args_1) { + return __spirv_ocl_atan2(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_atan2(__clc_vec16_fp32_t args_0, __clc_vec16_fp32_t args_1) { + return __spirv_ocl_atan2(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_atan2(__clc_fp64_t args_0, __clc_fp64_t args_1) { + return __spirv_ocl_atan2(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_atan2(__clc_vec2_fp64_t args_0, __clc_vec2_fp64_t args_1) { + return __spirv_ocl_atan2(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_atan2(__clc_vec3_fp64_t args_0, __clc_vec3_fp64_t args_1) { + return __spirv_ocl_atan2(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_atan2(__clc_vec4_fp64_t args_0, __clc_vec4_fp64_t args_1) { + return __spirv_ocl_atan2(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_atan2(__clc_vec8_fp64_t args_0, __clc_vec8_fp64_t args_1) { + return __spirv_ocl_atan2(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_atan2(__clc_vec16_fp64_t args_0, __clc_vec16_fp64_t args_1) { + return __spirv_ocl_atan2(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_atan2(__clc_fp16_t args_0, __clc_fp16_t args_1) { + return __spirv_ocl_atan2(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_atan2(__clc_vec2_fp16_t args_0, __clc_vec2_fp16_t args_1) { + return __spirv_ocl_atan2(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_atan2(__clc_vec3_fp16_t args_0, __clc_vec3_fp16_t args_1) { + return __spirv_ocl_atan2(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_atan2(__clc_vec4_fp16_t args_0, __clc_vec4_fp16_t args_1) { + return __spirv_ocl_atan2(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_atan2(__clc_vec8_fp16_t args_0, __clc_vec8_fp16_t args_1) { + return __spirv_ocl_atan2(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_atan2(__clc_vec16_fp16_t args_0, __clc_vec16_fp16_t args_1) { + return __spirv_ocl_atan2(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/atan2pi.cl b/libclc/test/binding/ocl/atan2pi.cl new file mode 100644 index 0000000000000..53865521ae80f --- /dev/null +++ b/libclc/test/binding/ocl/atan2pi.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_atan2pi(__clc_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_ocl_atan2pi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_atan2pi(__clc_vec2_fp32_t args_0, __clc_vec2_fp32_t args_1) { + return __spirv_ocl_atan2pi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_atan2pi(__clc_vec3_fp32_t args_0, __clc_vec3_fp32_t args_1) { + return __spirv_ocl_atan2pi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_atan2pi(__clc_vec4_fp32_t args_0, __clc_vec4_fp32_t args_1) { + return __spirv_ocl_atan2pi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_atan2pi(__clc_vec8_fp32_t args_0, __clc_vec8_fp32_t args_1) { + return __spirv_ocl_atan2pi(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_atan2pi(__clc_vec16_fp32_t args_0, __clc_vec16_fp32_t args_1) { + return __spirv_ocl_atan2pi(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_atan2pi(__clc_fp64_t args_0, __clc_fp64_t args_1) { + return __spirv_ocl_atan2pi(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_atan2pi(__clc_vec2_fp64_t args_0, __clc_vec2_fp64_t args_1) { + return __spirv_ocl_atan2pi(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_atan2pi(__clc_vec3_fp64_t args_0, __clc_vec3_fp64_t args_1) { + return __spirv_ocl_atan2pi(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_atan2pi(__clc_vec4_fp64_t args_0, __clc_vec4_fp64_t args_1) { + return __spirv_ocl_atan2pi(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_atan2pi(__clc_vec8_fp64_t args_0, __clc_vec8_fp64_t args_1) { + return __spirv_ocl_atan2pi(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_atan2pi(__clc_vec16_fp64_t args_0, __clc_vec16_fp64_t args_1) { + return __spirv_ocl_atan2pi(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_atan2pi(__clc_fp16_t args_0, __clc_fp16_t args_1) { + return __spirv_ocl_atan2pi(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_atan2pi(__clc_vec2_fp16_t args_0, __clc_vec2_fp16_t args_1) { + return __spirv_ocl_atan2pi(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_atan2pi(__clc_vec3_fp16_t args_0, __clc_vec3_fp16_t args_1) { + return __spirv_ocl_atan2pi(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_atan2pi(__clc_vec4_fp16_t args_0, __clc_vec4_fp16_t args_1) { + return __spirv_ocl_atan2pi(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_atan2pi(__clc_vec8_fp16_t args_0, __clc_vec8_fp16_t args_1) { + return __spirv_ocl_atan2pi(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_atan2pi(__clc_vec16_fp16_t args_0, __clc_vec16_fp16_t args_1) { + return __spirv_ocl_atan2pi(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/atanh.cl b/libclc/test/binding/ocl/atanh.cl new file mode 100644 index 0000000000000..05c03e0bfc568 --- /dev/null +++ b/libclc/test/binding/ocl/atanh.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_atanh(__clc_fp32_t args_0) { + return __spirv_ocl_atanh(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_atanh(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_atanh(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_atanh(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_atanh(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_atanh(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_atanh(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_atanh(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_atanh(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_atanh(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_atanh(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_atanh(__clc_fp64_t args_0) { + return __spirv_ocl_atanh(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_atanh(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_atanh(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_atanh(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_atanh(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_atanh(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_atanh(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_atanh(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_atanh(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_atanh(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_atanh(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_atanh(__clc_fp16_t args_0) { + return __spirv_ocl_atanh(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_atanh(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_atanh(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_atanh(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_atanh(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_atanh(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_atanh(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_atanh(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_atanh(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_atanh(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_atanh(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/atanpi.cl b/libclc/test/binding/ocl/atanpi.cl new file mode 100644 index 0000000000000..e44eba8214902 --- /dev/null +++ b/libclc/test/binding/ocl/atanpi.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_atanpi(__clc_fp32_t args_0) { + return __spirv_ocl_atanpi(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_atanpi(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_atanpi(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_atanpi(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_atanpi(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_atanpi(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_atanpi(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_atanpi(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_atanpi(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_atanpi(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_atanpi(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_atanpi(__clc_fp64_t args_0) { + return __spirv_ocl_atanpi(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_atanpi(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_atanpi(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_atanpi(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_atanpi(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_atanpi(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_atanpi(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_atanpi(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_atanpi(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_atanpi(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_atanpi(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_atanpi(__clc_fp16_t args_0) { + return __spirv_ocl_atanpi(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_atanpi(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_atanpi(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_atanpi(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_atanpi(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_atanpi(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_atanpi(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_atanpi(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_atanpi(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_atanpi(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_atanpi(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/cbrt.cl b/libclc/test/binding/ocl/cbrt.cl new file mode 100644 index 0000000000000..8925c92e2147c --- /dev/null +++ b/libclc/test/binding/ocl/cbrt.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_cbrt(__clc_fp32_t args_0) { + return __spirv_ocl_cbrt(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_cbrt(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_cbrt(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_cbrt(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_cbrt(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_cbrt(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_cbrt(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_cbrt(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_cbrt(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_cbrt(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_cbrt(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_cbrt(__clc_fp64_t args_0) { + return __spirv_ocl_cbrt(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_cbrt(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_cbrt(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_cbrt(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_cbrt(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_cbrt(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_cbrt(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_cbrt(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_cbrt(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_cbrt(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_cbrt(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_cbrt(__clc_fp16_t args_0) { + return __spirv_ocl_cbrt(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_cbrt(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_cbrt(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_cbrt(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_cbrt(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_cbrt(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_cbrt(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_cbrt(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_cbrt(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_cbrt(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_cbrt(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/ceil.cl b/libclc/test/binding/ocl/ceil.cl new file mode 100644 index 0000000000000..c60cd81e7e530 --- /dev/null +++ b/libclc/test/binding/ocl/ceil.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_ceil(__clc_fp32_t args_0) { + return __spirv_ocl_ceil(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_ceil(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_ceil(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_ceil(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_ceil(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_ceil(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_ceil(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_ceil(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_ceil(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_ceil(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_ceil(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_ceil(__clc_fp64_t args_0) { + return __spirv_ocl_ceil(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_ceil(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_ceil(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_ceil(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_ceil(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_ceil(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_ceil(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_ceil(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_ceil(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_ceil(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_ceil(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_ceil(__clc_fp16_t args_0) { + return __spirv_ocl_ceil(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_ceil(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_ceil(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_ceil(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_ceil(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_ceil(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_ceil(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_ceil(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_ceil(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_ceil(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_ceil(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/cos.cl b/libclc/test/binding/ocl/cos.cl new file mode 100644 index 0000000000000..7f9a884f989a7 --- /dev/null +++ b/libclc/test/binding/ocl/cos.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_cos(__clc_fp32_t args_0) { + return __spirv_ocl_cos(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_cos(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_cos(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_cos(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_cos(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_cos(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_cos(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_cos(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_cos(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_cos(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_cos(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_cos(__clc_fp64_t args_0) { + return __spirv_ocl_cos(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_cos(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_cos(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_cos(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_cos(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_cos(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_cos(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_cos(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_cos(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_cos(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_cos(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_cos(__clc_fp16_t args_0) { + return __spirv_ocl_cos(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_cos(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_cos(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_cos(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_cos(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_cos(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_cos(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_cos(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_cos(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_cos(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_cos(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/cosh.cl b/libclc/test/binding/ocl/cosh.cl new file mode 100644 index 0000000000000..35ebffab0fc8b --- /dev/null +++ b/libclc/test/binding/ocl/cosh.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_cosh(__clc_fp32_t args_0) { + return __spirv_ocl_cosh(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_cosh(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_cosh(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_cosh(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_cosh(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_cosh(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_cosh(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_cosh(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_cosh(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_cosh(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_cosh(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_cosh(__clc_fp64_t args_0) { + return __spirv_ocl_cosh(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_cosh(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_cosh(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_cosh(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_cosh(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_cosh(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_cosh(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_cosh(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_cosh(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_cosh(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_cosh(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_cosh(__clc_fp16_t args_0) { + return __spirv_ocl_cosh(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_cosh(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_cosh(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_cosh(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_cosh(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_cosh(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_cosh(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_cosh(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_cosh(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_cosh(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_cosh(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/cospi.cl b/libclc/test/binding/ocl/cospi.cl new file mode 100644 index 0000000000000..44b15bec63504 --- /dev/null +++ b/libclc/test/binding/ocl/cospi.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_cospi(__clc_fp32_t args_0) { + return __spirv_ocl_cospi(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_cospi(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_cospi(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_cospi(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_cospi(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_cospi(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_cospi(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_cospi(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_cospi(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_cospi(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_cospi(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_cospi(__clc_fp64_t args_0) { + return __spirv_ocl_cospi(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_cospi(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_cospi(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_cospi(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_cospi(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_cospi(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_cospi(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_cospi(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_cospi(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_cospi(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_cospi(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_cospi(__clc_fp16_t args_0) { + return __spirv_ocl_cospi(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_cospi(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_cospi(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_cospi(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_cospi(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_cospi(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_cospi(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_cospi(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_cospi(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_cospi(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_cospi(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/erf.cl b/libclc/test/binding/ocl/erf.cl new file mode 100644 index 0000000000000..d67c7833de1ec --- /dev/null +++ b/libclc/test/binding/ocl/erf.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_erf(__clc_fp32_t args_0) { + return __spirv_ocl_erf(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_erf(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_erf(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_erf(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_erf(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_erf(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_erf(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_erf(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_erf(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_erf(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_erf(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_erf(__clc_fp64_t args_0) { + return __spirv_ocl_erf(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_erf(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_erf(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_erf(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_erf(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_erf(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_erf(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_erf(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_erf(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_erf(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_erf(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_erf(__clc_fp16_t args_0) { + return __spirv_ocl_erf(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_erf(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_erf(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_erf(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_erf(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_erf(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_erf(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_erf(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_erf(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_erf(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_erf(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/erfc.cl b/libclc/test/binding/ocl/erfc.cl new file mode 100644 index 0000000000000..0a5d8c5cdae8d --- /dev/null +++ b/libclc/test/binding/ocl/erfc.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_erfc(__clc_fp32_t args_0) { + return __spirv_ocl_erfc(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_erfc(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_erfc(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_erfc(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_erfc(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_erfc(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_erfc(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_erfc(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_erfc(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_erfc(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_erfc(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_erfc(__clc_fp64_t args_0) { + return __spirv_ocl_erfc(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_erfc(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_erfc(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_erfc(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_erfc(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_erfc(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_erfc(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_erfc(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_erfc(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_erfc(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_erfc(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_erfc(__clc_fp16_t args_0) { + return __spirv_ocl_erfc(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_erfc(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_erfc(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_erfc(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_erfc(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_erfc(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_erfc(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_erfc(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_erfc(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_erfc(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_erfc(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/exp.cl b/libclc/test/binding/ocl/exp.cl new file mode 100644 index 0000000000000..21c48ad5a8c75 --- /dev/null +++ b/libclc/test/binding/ocl/exp.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_exp(__clc_fp32_t args_0) { + return __spirv_ocl_exp(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_exp(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_exp(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_exp(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_exp(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_exp(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_exp(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_exp(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_exp(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_exp(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_exp(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_exp(__clc_fp64_t args_0) { + return __spirv_ocl_exp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_exp(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_exp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_exp(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_exp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_exp(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_exp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_exp(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_exp(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_exp(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_exp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_exp(__clc_fp16_t args_0) { + return __spirv_ocl_exp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_exp(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_exp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_exp(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_exp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_exp(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_exp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_exp(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_exp(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_exp(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_exp(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/exp10.cl b/libclc/test/binding/ocl/exp10.cl new file mode 100644 index 0000000000000..ab49ff10abda0 --- /dev/null +++ b/libclc/test/binding/ocl/exp10.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_exp10(__clc_fp32_t args_0) { + return __spirv_ocl_exp10(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_exp10(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_exp10(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_exp10(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_exp10(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_exp10(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_exp10(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_exp10(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_exp10(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_exp10(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_exp10(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_exp10(__clc_fp64_t args_0) { + return __spirv_ocl_exp10(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_exp10(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_exp10(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_exp10(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_exp10(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_exp10(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_exp10(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_exp10(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_exp10(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_exp10(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_exp10(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_exp10(__clc_fp16_t args_0) { + return __spirv_ocl_exp10(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_exp10(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_exp10(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_exp10(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_exp10(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_exp10(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_exp10(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_exp10(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_exp10(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_exp10(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_exp10(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/exp2.cl b/libclc/test/binding/ocl/exp2.cl new file mode 100644 index 0000000000000..98b3bdcdcfa7d --- /dev/null +++ b/libclc/test/binding/ocl/exp2.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_exp2(__clc_fp32_t args_0) { + return __spirv_ocl_exp2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_exp2(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_exp2(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_exp2(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_exp2(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_exp2(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_exp2(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_exp2(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_exp2(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_exp2(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_exp2(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_exp2(__clc_fp64_t args_0) { + return __spirv_ocl_exp2(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_exp2(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_exp2(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_exp2(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_exp2(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_exp2(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_exp2(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_exp2(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_exp2(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_exp2(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_exp2(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_exp2(__clc_fp16_t args_0) { + return __spirv_ocl_exp2(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_exp2(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_exp2(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_exp2(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_exp2(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_exp2(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_exp2(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_exp2(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_exp2(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_exp2(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_exp2(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/expm1.cl b/libclc/test/binding/ocl/expm1.cl new file mode 100644 index 0000000000000..63947216b9eb9 --- /dev/null +++ b/libclc/test/binding/ocl/expm1.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_expm1(__clc_fp32_t args_0) { + return __spirv_ocl_expm1(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_expm1(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_expm1(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_expm1(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_expm1(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_expm1(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_expm1(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_expm1(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_expm1(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_expm1(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_expm1(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_expm1(__clc_fp64_t args_0) { + return __spirv_ocl_expm1(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_expm1(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_expm1(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_expm1(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_expm1(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_expm1(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_expm1(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_expm1(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_expm1(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_expm1(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_expm1(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_expm1(__clc_fp16_t args_0) { + return __spirv_ocl_expm1(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_expm1(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_expm1(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_expm1(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_expm1(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_expm1(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_expm1(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_expm1(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_expm1(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_expm1(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_expm1(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/fclamp.cl b/libclc/test/binding/ocl/fclamp.cl new file mode 100644 index 0000000000000..3bce2d2529ab2 --- /dev/null +++ b/libclc/test/binding/ocl/fclamp.cl @@ -0,0 +1,149 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_fclamp(__clc_fp32_t args_0, __clc_fp32_t args_1, + __clc_fp32_t args_2) { + return __spirv_ocl_fclamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_fclamp(__clc_vec2_fp32_t args_0, __clc_vec2_fp32_t args_1, + __clc_vec2_fp32_t args_2) { + return __spirv_ocl_fclamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_fclamp(__clc_vec3_fp32_t args_0, __clc_vec3_fp32_t args_1, + __clc_vec3_fp32_t args_2) { + return __spirv_ocl_fclamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_fclamp(__clc_vec4_fp32_t args_0, __clc_vec4_fp32_t args_1, + __clc_vec4_fp32_t args_2) { + return __spirv_ocl_fclamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_fclamp(__clc_vec8_fp32_t args_0, __clc_vec8_fp32_t args_1, + __clc_vec8_fp32_t args_2) { + return __spirv_ocl_fclamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_fclamp(__clc_vec16_fp32_t args_0, __clc_vec16_fp32_t args_1, + __clc_vec16_fp32_t args_2) { + return __spirv_ocl_fclamp(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_fclamp(__clc_fp64_t args_0, __clc_fp64_t args_1, + __clc_fp64_t args_2) { + return __spirv_ocl_fclamp(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_fclamp(__clc_vec2_fp64_t args_0, __clc_vec2_fp64_t args_1, + __clc_vec2_fp64_t args_2) { + return __spirv_ocl_fclamp(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_fclamp(__clc_vec3_fp64_t args_0, __clc_vec3_fp64_t args_1, + __clc_vec3_fp64_t args_2) { + return __spirv_ocl_fclamp(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_fclamp(__clc_vec4_fp64_t args_0, __clc_vec4_fp64_t args_1, + __clc_vec4_fp64_t args_2) { + return __spirv_ocl_fclamp(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_fclamp(__clc_vec8_fp64_t args_0, __clc_vec8_fp64_t args_1, + __clc_vec8_fp64_t args_2) { + return __spirv_ocl_fclamp(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_fclamp(__clc_vec16_fp64_t args_0, __clc_vec16_fp64_t args_1, + __clc_vec16_fp64_t args_2) { + return __spirv_ocl_fclamp(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_fclamp(__clc_fp16_t args_0, __clc_fp16_t args_1, + __clc_fp16_t args_2) { + return __spirv_ocl_fclamp(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_fclamp(__clc_vec2_fp16_t args_0, __clc_vec2_fp16_t args_1, + __clc_vec2_fp16_t args_2) { + return __spirv_ocl_fclamp(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_fclamp(__clc_vec3_fp16_t args_0, __clc_vec3_fp16_t args_1, + __clc_vec3_fp16_t args_2) { + return __spirv_ocl_fclamp(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_fclamp(__clc_vec4_fp16_t args_0, __clc_vec4_fp16_t args_1, + __clc_vec4_fp16_t args_2) { + return __spirv_ocl_fclamp(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_fclamp(__clc_vec8_fp16_t args_0, __clc_vec8_fp16_t args_1, + __clc_vec8_fp16_t args_2) { + return __spirv_ocl_fclamp(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_fclamp(__clc_vec16_fp16_t args_0, __clc_vec16_fp16_t args_1, + __clc_vec16_fp16_t args_2) { + return __spirv_ocl_fclamp(args_0, args_1, args_2); +} + +#endif diff --git a/libclc/test/binding/ocl/fdim.cl b/libclc/test/binding/ocl/fdim.cl new file mode 100644 index 0000000000000..d070214c1d764 --- /dev/null +++ b/libclc/test/binding/ocl/fdim.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_fdim(__clc_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_ocl_fdim(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_fdim(__clc_vec2_fp32_t args_0, __clc_vec2_fp32_t args_1) { + return __spirv_ocl_fdim(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_fdim(__clc_vec3_fp32_t args_0, __clc_vec3_fp32_t args_1) { + return __spirv_ocl_fdim(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_fdim(__clc_vec4_fp32_t args_0, __clc_vec4_fp32_t args_1) { + return __spirv_ocl_fdim(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_fdim(__clc_vec8_fp32_t args_0, __clc_vec8_fp32_t args_1) { + return __spirv_ocl_fdim(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_fdim(__clc_vec16_fp32_t args_0, __clc_vec16_fp32_t args_1) { + return __spirv_ocl_fdim(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_fdim(__clc_fp64_t args_0, __clc_fp64_t args_1) { + return __spirv_ocl_fdim(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_fdim(__clc_vec2_fp64_t args_0, __clc_vec2_fp64_t args_1) { + return __spirv_ocl_fdim(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_fdim(__clc_vec3_fp64_t args_0, __clc_vec3_fp64_t args_1) { + return __spirv_ocl_fdim(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_fdim(__clc_vec4_fp64_t args_0, __clc_vec4_fp64_t args_1) { + return __spirv_ocl_fdim(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_fdim(__clc_vec8_fp64_t args_0, __clc_vec8_fp64_t args_1) { + return __spirv_ocl_fdim(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_fdim(__clc_vec16_fp64_t args_0, __clc_vec16_fp64_t args_1) { + return __spirv_ocl_fdim(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_fdim(__clc_fp16_t args_0, __clc_fp16_t args_1) { + return __spirv_ocl_fdim(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_fdim(__clc_vec2_fp16_t args_0, __clc_vec2_fp16_t args_1) { + return __spirv_ocl_fdim(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_fdim(__clc_vec3_fp16_t args_0, __clc_vec3_fp16_t args_1) { + return __spirv_ocl_fdim(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_fdim(__clc_vec4_fp16_t args_0, __clc_vec4_fp16_t args_1) { + return __spirv_ocl_fdim(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_fdim(__clc_vec8_fp16_t args_0, __clc_vec8_fp16_t args_1) { + return __spirv_ocl_fdim(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_fdim(__clc_vec16_fp16_t args_0, __clc_vec16_fp16_t args_1) { + return __spirv_ocl_fdim(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/floor.cl b/libclc/test/binding/ocl/floor.cl new file mode 100644 index 0000000000000..368fba2bb1749 --- /dev/null +++ b/libclc/test/binding/ocl/floor.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_floor(__clc_fp32_t args_0) { + return __spirv_ocl_floor(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_floor(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_floor(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_floor(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_floor(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_floor(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_floor(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_floor(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_floor(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_floor(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_floor(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_floor(__clc_fp64_t args_0) { + return __spirv_ocl_floor(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_floor(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_floor(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_floor(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_floor(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_floor(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_floor(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_floor(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_floor(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_floor(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_floor(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_floor(__clc_fp16_t args_0) { + return __spirv_ocl_floor(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_floor(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_floor(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_floor(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_floor(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_floor(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_floor(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_floor(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_floor(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_floor(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_floor(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/fma.cl b/libclc/test/binding/ocl/fma.cl new file mode 100644 index 0000000000000..2064c12848046 --- /dev/null +++ b/libclc/test/binding/ocl/fma.cl @@ -0,0 +1,149 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_fma(__clc_fp32_t args_0, __clc_fp32_t args_1, + __clc_fp32_t args_2) { + return __spirv_ocl_fma(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_fma(__clc_vec2_fp32_t args_0, __clc_vec2_fp32_t args_1, + __clc_vec2_fp32_t args_2) { + return __spirv_ocl_fma(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_fma(__clc_vec3_fp32_t args_0, __clc_vec3_fp32_t args_1, + __clc_vec3_fp32_t args_2) { + return __spirv_ocl_fma(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_fma(__clc_vec4_fp32_t args_0, __clc_vec4_fp32_t args_1, + __clc_vec4_fp32_t args_2) { + return __spirv_ocl_fma(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_fma(__clc_vec8_fp32_t args_0, __clc_vec8_fp32_t args_1, + __clc_vec8_fp32_t args_2) { + return __spirv_ocl_fma(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_fma(__clc_vec16_fp32_t args_0, __clc_vec16_fp32_t args_1, + __clc_vec16_fp32_t args_2) { + return __spirv_ocl_fma(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_fma(__clc_fp64_t args_0, __clc_fp64_t args_1, + __clc_fp64_t args_2) { + return __spirv_ocl_fma(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_fma(__clc_vec2_fp64_t args_0, __clc_vec2_fp64_t args_1, + __clc_vec2_fp64_t args_2) { + return __spirv_ocl_fma(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_fma(__clc_vec3_fp64_t args_0, __clc_vec3_fp64_t args_1, + __clc_vec3_fp64_t args_2) { + return __spirv_ocl_fma(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_fma(__clc_vec4_fp64_t args_0, __clc_vec4_fp64_t args_1, + __clc_vec4_fp64_t args_2) { + return __spirv_ocl_fma(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_fma(__clc_vec8_fp64_t args_0, __clc_vec8_fp64_t args_1, + __clc_vec8_fp64_t args_2) { + return __spirv_ocl_fma(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_fma(__clc_vec16_fp64_t args_0, __clc_vec16_fp64_t args_1, + __clc_vec16_fp64_t args_2) { + return __spirv_ocl_fma(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_fma(__clc_fp16_t args_0, __clc_fp16_t args_1, + __clc_fp16_t args_2) { + return __spirv_ocl_fma(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_fma(__clc_vec2_fp16_t args_0, __clc_vec2_fp16_t args_1, + __clc_vec2_fp16_t args_2) { + return __spirv_ocl_fma(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_fma(__clc_vec3_fp16_t args_0, __clc_vec3_fp16_t args_1, + __clc_vec3_fp16_t args_2) { + return __spirv_ocl_fma(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_fma(__clc_vec4_fp16_t args_0, __clc_vec4_fp16_t args_1, + __clc_vec4_fp16_t args_2) { + return __spirv_ocl_fma(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_fma(__clc_vec8_fp16_t args_0, __clc_vec8_fp16_t args_1, + __clc_vec8_fp16_t args_2) { + return __spirv_ocl_fma(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_fma(__clc_vec16_fp16_t args_0, __clc_vec16_fp16_t args_1, + __clc_vec16_fp16_t args_2) { + return __spirv_ocl_fma(args_0, args_1, args_2); +} + +#endif diff --git a/libclc/test/binding/ocl/fmax.cl b/libclc/test/binding/ocl/fmax.cl new file mode 100644 index 0000000000000..f428d91e338cd --- /dev/null +++ b/libclc/test/binding/ocl/fmax.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_fmax(__clc_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_ocl_fmax(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_fmax(__clc_vec2_fp32_t args_0, __clc_vec2_fp32_t args_1) { + return __spirv_ocl_fmax(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_fmax(__clc_vec3_fp32_t args_0, __clc_vec3_fp32_t args_1) { + return __spirv_ocl_fmax(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_fmax(__clc_vec4_fp32_t args_0, __clc_vec4_fp32_t args_1) { + return __spirv_ocl_fmax(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_fmax(__clc_vec8_fp32_t args_0, __clc_vec8_fp32_t args_1) { + return __spirv_ocl_fmax(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_fmax(__clc_vec16_fp32_t args_0, __clc_vec16_fp32_t args_1) { + return __spirv_ocl_fmax(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_fmax(__clc_fp64_t args_0, __clc_fp64_t args_1) { + return __spirv_ocl_fmax(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_fmax(__clc_vec2_fp64_t args_0, __clc_vec2_fp64_t args_1) { + return __spirv_ocl_fmax(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_fmax(__clc_vec3_fp64_t args_0, __clc_vec3_fp64_t args_1) { + return __spirv_ocl_fmax(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_fmax(__clc_vec4_fp64_t args_0, __clc_vec4_fp64_t args_1) { + return __spirv_ocl_fmax(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_fmax(__clc_vec8_fp64_t args_0, __clc_vec8_fp64_t args_1) { + return __spirv_ocl_fmax(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_fmax(__clc_vec16_fp64_t args_0, __clc_vec16_fp64_t args_1) { + return __spirv_ocl_fmax(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_fmax(__clc_fp16_t args_0, __clc_fp16_t args_1) { + return __spirv_ocl_fmax(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_fmax(__clc_vec2_fp16_t args_0, __clc_vec2_fp16_t args_1) { + return __spirv_ocl_fmax(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_fmax(__clc_vec3_fp16_t args_0, __clc_vec3_fp16_t args_1) { + return __spirv_ocl_fmax(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_fmax(__clc_vec4_fp16_t args_0, __clc_vec4_fp16_t args_1) { + return __spirv_ocl_fmax(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_fmax(__clc_vec8_fp16_t args_0, __clc_vec8_fp16_t args_1) { + return __spirv_ocl_fmax(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_fmax(__clc_vec16_fp16_t args_0, __clc_vec16_fp16_t args_1) { + return __spirv_ocl_fmax(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/fmax_common.cl b/libclc/test/binding/ocl/fmax_common.cl new file mode 100644 index 0000000000000..e8b608a3824db --- /dev/null +++ b/libclc/test/binding/ocl/fmax_common.cl @@ -0,0 +1,146 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_fmax_common(__clc_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_ocl_fmax_common(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_fmax_common(__clc_vec2_fp32_t args_0, + __clc_vec2_fp32_t args_1) { + return __spirv_ocl_fmax_common(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_fmax_common(__clc_vec3_fp32_t args_0, + __clc_vec3_fp32_t args_1) { + return __spirv_ocl_fmax_common(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_fmax_common(__clc_vec4_fp32_t args_0, + __clc_vec4_fp32_t args_1) { + return __spirv_ocl_fmax_common(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_fmax_common(__clc_vec8_fp32_t args_0, + __clc_vec8_fp32_t args_1) { + return __spirv_ocl_fmax_common(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_fmax_common(__clc_vec16_fp32_t args_0, + __clc_vec16_fp32_t args_1) { + return __spirv_ocl_fmax_common(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_fmax_common(__clc_fp64_t args_0, __clc_fp64_t args_1) { + return __spirv_ocl_fmax_common(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_fmax_common(__clc_vec2_fp64_t args_0, + __clc_vec2_fp64_t args_1) { + return __spirv_ocl_fmax_common(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_fmax_common(__clc_vec3_fp64_t args_0, + __clc_vec3_fp64_t args_1) { + return __spirv_ocl_fmax_common(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_fmax_common(__clc_vec4_fp64_t args_0, + __clc_vec4_fp64_t args_1) { + return __spirv_ocl_fmax_common(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_fmax_common(__clc_vec8_fp64_t args_0, + __clc_vec8_fp64_t args_1) { + return __spirv_ocl_fmax_common(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_fmax_common(__clc_vec16_fp64_t args_0, + __clc_vec16_fp64_t args_1) { + return __spirv_ocl_fmax_common(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_fmax_common(__clc_fp16_t args_0, __clc_fp16_t args_1) { + return __spirv_ocl_fmax_common(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_fmax_common(__clc_vec2_fp16_t args_0, + __clc_vec2_fp16_t args_1) { + return __spirv_ocl_fmax_common(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_fmax_common(__clc_vec3_fp16_t args_0, + __clc_vec3_fp16_t args_1) { + return __spirv_ocl_fmax_common(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_fmax_common(__clc_vec4_fp16_t args_0, + __clc_vec4_fp16_t args_1) { + return __spirv_ocl_fmax_common(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_fmax_common(__clc_vec8_fp16_t args_0, + __clc_vec8_fp16_t args_1) { + return __spirv_ocl_fmax_common(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_fmax_common(__clc_vec16_fp16_t args_0, + __clc_vec16_fp16_t args_1) { + return __spirv_ocl_fmax_common(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/fmin.cl b/libclc/test/binding/ocl/fmin.cl new file mode 100644 index 0000000000000..ca3c02281baf6 --- /dev/null +++ b/libclc/test/binding/ocl/fmin.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_fmin(__clc_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_ocl_fmin(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_fmin(__clc_vec2_fp32_t args_0, __clc_vec2_fp32_t args_1) { + return __spirv_ocl_fmin(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_fmin(__clc_vec3_fp32_t args_0, __clc_vec3_fp32_t args_1) { + return __spirv_ocl_fmin(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_fmin(__clc_vec4_fp32_t args_0, __clc_vec4_fp32_t args_1) { + return __spirv_ocl_fmin(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_fmin(__clc_vec8_fp32_t args_0, __clc_vec8_fp32_t args_1) { + return __spirv_ocl_fmin(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_fmin(__clc_vec16_fp32_t args_0, __clc_vec16_fp32_t args_1) { + return __spirv_ocl_fmin(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_fmin(__clc_fp64_t args_0, __clc_fp64_t args_1) { + return __spirv_ocl_fmin(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_fmin(__clc_vec2_fp64_t args_0, __clc_vec2_fp64_t args_1) { + return __spirv_ocl_fmin(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_fmin(__clc_vec3_fp64_t args_0, __clc_vec3_fp64_t args_1) { + return __spirv_ocl_fmin(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_fmin(__clc_vec4_fp64_t args_0, __clc_vec4_fp64_t args_1) { + return __spirv_ocl_fmin(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_fmin(__clc_vec8_fp64_t args_0, __clc_vec8_fp64_t args_1) { + return __spirv_ocl_fmin(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_fmin(__clc_vec16_fp64_t args_0, __clc_vec16_fp64_t args_1) { + return __spirv_ocl_fmin(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_fmin(__clc_fp16_t args_0, __clc_fp16_t args_1) { + return __spirv_ocl_fmin(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_fmin(__clc_vec2_fp16_t args_0, __clc_vec2_fp16_t args_1) { + return __spirv_ocl_fmin(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_fmin(__clc_vec3_fp16_t args_0, __clc_vec3_fp16_t args_1) { + return __spirv_ocl_fmin(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_fmin(__clc_vec4_fp16_t args_0, __clc_vec4_fp16_t args_1) { + return __spirv_ocl_fmin(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_fmin(__clc_vec8_fp16_t args_0, __clc_vec8_fp16_t args_1) { + return __spirv_ocl_fmin(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_fmin(__clc_vec16_fp16_t args_0, __clc_vec16_fp16_t args_1) { + return __spirv_ocl_fmin(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/fmin_common.cl b/libclc/test/binding/ocl/fmin_common.cl new file mode 100644 index 0000000000000..104a26a2ad1a0 --- /dev/null +++ b/libclc/test/binding/ocl/fmin_common.cl @@ -0,0 +1,146 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_fmin_common(__clc_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_ocl_fmin_common(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_fmin_common(__clc_vec2_fp32_t args_0, + __clc_vec2_fp32_t args_1) { + return __spirv_ocl_fmin_common(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_fmin_common(__clc_vec3_fp32_t args_0, + __clc_vec3_fp32_t args_1) { + return __spirv_ocl_fmin_common(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_fmin_common(__clc_vec4_fp32_t args_0, + __clc_vec4_fp32_t args_1) { + return __spirv_ocl_fmin_common(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_fmin_common(__clc_vec8_fp32_t args_0, + __clc_vec8_fp32_t args_1) { + return __spirv_ocl_fmin_common(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_fmin_common(__clc_vec16_fp32_t args_0, + __clc_vec16_fp32_t args_1) { + return __spirv_ocl_fmin_common(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_fmin_common(__clc_fp64_t args_0, __clc_fp64_t args_1) { + return __spirv_ocl_fmin_common(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_fmin_common(__clc_vec2_fp64_t args_0, + __clc_vec2_fp64_t args_1) { + return __spirv_ocl_fmin_common(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_fmin_common(__clc_vec3_fp64_t args_0, + __clc_vec3_fp64_t args_1) { + return __spirv_ocl_fmin_common(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_fmin_common(__clc_vec4_fp64_t args_0, + __clc_vec4_fp64_t args_1) { + return __spirv_ocl_fmin_common(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_fmin_common(__clc_vec8_fp64_t args_0, + __clc_vec8_fp64_t args_1) { + return __spirv_ocl_fmin_common(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_fmin_common(__clc_vec16_fp64_t args_0, + __clc_vec16_fp64_t args_1) { + return __spirv_ocl_fmin_common(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_fmin_common(__clc_fp16_t args_0, __clc_fp16_t args_1) { + return __spirv_ocl_fmin_common(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_fmin_common(__clc_vec2_fp16_t args_0, + __clc_vec2_fp16_t args_1) { + return __spirv_ocl_fmin_common(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_fmin_common(__clc_vec3_fp16_t args_0, + __clc_vec3_fp16_t args_1) { + return __spirv_ocl_fmin_common(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_fmin_common(__clc_vec4_fp16_t args_0, + __clc_vec4_fp16_t args_1) { + return __spirv_ocl_fmin_common(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_fmin_common(__clc_vec8_fp16_t args_0, + __clc_vec8_fp16_t args_1) { + return __spirv_ocl_fmin_common(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_fmin_common(__clc_vec16_fp16_t args_0, + __clc_vec16_fp16_t args_1) { + return __spirv_ocl_fmin_common(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/fmod.cl b/libclc/test/binding/ocl/fmod.cl new file mode 100644 index 0000000000000..c76acfdb7f36f --- /dev/null +++ b/libclc/test/binding/ocl/fmod.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_fmod(__clc_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_ocl_fmod(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_fmod(__clc_vec2_fp32_t args_0, __clc_vec2_fp32_t args_1) { + return __spirv_ocl_fmod(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_fmod(__clc_vec3_fp32_t args_0, __clc_vec3_fp32_t args_1) { + return __spirv_ocl_fmod(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_fmod(__clc_vec4_fp32_t args_0, __clc_vec4_fp32_t args_1) { + return __spirv_ocl_fmod(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_fmod(__clc_vec8_fp32_t args_0, __clc_vec8_fp32_t args_1) { + return __spirv_ocl_fmod(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_fmod(__clc_vec16_fp32_t args_0, __clc_vec16_fp32_t args_1) { + return __spirv_ocl_fmod(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_fmod(__clc_fp64_t args_0, __clc_fp64_t args_1) { + return __spirv_ocl_fmod(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_fmod(__clc_vec2_fp64_t args_0, __clc_vec2_fp64_t args_1) { + return __spirv_ocl_fmod(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_fmod(__clc_vec3_fp64_t args_0, __clc_vec3_fp64_t args_1) { + return __spirv_ocl_fmod(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_fmod(__clc_vec4_fp64_t args_0, __clc_vec4_fp64_t args_1) { + return __spirv_ocl_fmod(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_fmod(__clc_vec8_fp64_t args_0, __clc_vec8_fp64_t args_1) { + return __spirv_ocl_fmod(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_fmod(__clc_vec16_fp64_t args_0, __clc_vec16_fp64_t args_1) { + return __spirv_ocl_fmod(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_fmod(__clc_fp16_t args_0, __clc_fp16_t args_1) { + return __spirv_ocl_fmod(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_fmod(__clc_vec2_fp16_t args_0, __clc_vec2_fp16_t args_1) { + return __spirv_ocl_fmod(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_fmod(__clc_vec3_fp16_t args_0, __clc_vec3_fp16_t args_1) { + return __spirv_ocl_fmod(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_fmod(__clc_vec4_fp16_t args_0, __clc_vec4_fp16_t args_1) { + return __spirv_ocl_fmod(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_fmod(__clc_vec8_fp16_t args_0, __clc_vec8_fp16_t args_1) { + return __spirv_ocl_fmod(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_fmod(__clc_vec16_fp16_t args_0, __clc_vec16_fp16_t args_1) { + return __spirv_ocl_fmod(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/fract.cl b/libclc/test/binding/ocl/fract.cl new file mode 100644 index 0000000000000..73bef44eab972 --- /dev/null +++ b/libclc/test/binding/ocl/fract.cl @@ -0,0 +1,389 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_fract(__clc_fp32_t args_0, __clc_fp32_t __local *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_fract(__clc_vec2_fp32_t args_0, + __clc_vec2_fp32_t __local *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_fract(__clc_vec3_fp32_t args_0, + __clc_vec3_fp32_t __local *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_fract(__clc_vec4_fp32_t args_0, + __clc_vec4_fp32_t __local *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_fract(__clc_vec8_fp32_t args_0, + __clc_vec8_fp32_t __local *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_fract(__clc_vec16_fp32_t args_0, + __clc_vec16_fp32_t __local *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_fract(__clc_fp64_t args_0, __clc_fp64_t __local *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_fract(__clc_vec2_fp64_t args_0, + __clc_vec2_fp64_t __local *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_fract(__clc_vec3_fp64_t args_0, + __clc_vec3_fp64_t __local *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_fract(__clc_vec4_fp64_t args_0, + __clc_vec4_fp64_t __local *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_fract(__clc_vec8_fp64_t args_0, + __clc_vec8_fp64_t __local *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_fract(__clc_vec16_fp64_t args_0, + __clc_vec16_fp64_t __local *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_fract(__clc_fp16_t args_0, __clc_fp16_t __local *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_fract(__clc_vec2_fp16_t args_0, + __clc_vec2_fp16_t __local *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_fract(__clc_vec3_fp16_t args_0, + __clc_vec3_fp16_t __local *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_fract(__clc_vec4_fp16_t args_0, + __clc_vec4_fp16_t __local *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_fract(__clc_vec8_fp16_t args_0, + __clc_vec8_fp16_t __local *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_fract(__clc_vec16_fp16_t args_0, + __clc_vec16_fp16_t __local *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_fract(__clc_fp32_t args_0, __clc_fp32_t *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_fract(__clc_vec2_fp32_t args_0, __clc_vec2_fp32_t *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_fract(__clc_vec3_fp32_t args_0, __clc_vec3_fp32_t *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_fract(__clc_vec4_fp32_t args_0, __clc_vec4_fp32_t *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_fract(__clc_vec8_fp32_t args_0, __clc_vec8_fp32_t *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_fract(__clc_vec16_fp32_t args_0, __clc_vec16_fp32_t *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_fract(__clc_fp64_t args_0, __clc_fp64_t *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_fract(__clc_vec2_fp64_t args_0, __clc_vec2_fp64_t *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_fract(__clc_vec3_fp64_t args_0, __clc_vec3_fp64_t *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_fract(__clc_vec4_fp64_t args_0, __clc_vec4_fp64_t *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_fract(__clc_vec8_fp64_t args_0, __clc_vec8_fp64_t *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_fract(__clc_vec16_fp64_t args_0, __clc_vec16_fp64_t *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_fract(__clc_fp16_t args_0, __clc_fp16_t *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_fract(__clc_vec2_fp16_t args_0, __clc_vec2_fp16_t *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_fract(__clc_vec3_fp16_t args_0, __clc_vec3_fp16_t *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_fract(__clc_vec4_fp16_t args_0, __clc_vec4_fp16_t *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_fract(__clc_vec8_fp16_t args_0, __clc_vec8_fp16_t *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_fract(__clc_vec16_fp16_t args_0, __clc_vec16_fp16_t *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_fract(__clc_fp32_t args_0, __clc_fp32_t __global *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_fract(__clc_vec2_fp32_t args_0, + __clc_vec2_fp32_t __global *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_fract(__clc_vec3_fp32_t args_0, + __clc_vec3_fp32_t __global *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_fract(__clc_vec4_fp32_t args_0, + __clc_vec4_fp32_t __global *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_fract(__clc_vec8_fp32_t args_0, + __clc_vec8_fp32_t __global *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_fract(__clc_vec16_fp32_t args_0, + __clc_vec16_fp32_t __global *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_fract(__clc_fp64_t args_0, __clc_fp64_t __global *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_fract(__clc_vec2_fp64_t args_0, + __clc_vec2_fp64_t __global *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_fract(__clc_vec3_fp64_t args_0, + __clc_vec3_fp64_t __global *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_fract(__clc_vec4_fp64_t args_0, + __clc_vec4_fp64_t __global *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_fract(__clc_vec8_fp64_t args_0, + __clc_vec8_fp64_t __global *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_fract(__clc_vec16_fp64_t args_0, + __clc_vec16_fp64_t __global *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_fract(__clc_fp16_t args_0, __clc_fp16_t __global *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_fract(__clc_vec2_fp16_t args_0, + __clc_vec2_fp16_t __global *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_fract(__clc_vec3_fp16_t args_0, + __clc_vec3_fp16_t __global *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_fract(__clc_vec4_fp16_t args_0, + __clc_vec4_fp16_t __global *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_fract(__clc_vec8_fp16_t args_0, + __clc_vec8_fp16_t __global *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_fract(__clc_vec16_fp16_t args_0, + __clc_vec16_fp16_t __global *args_1) { + return __spirv_ocl_fract(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/frexp.cl b/libclc/test/binding/ocl/frexp.cl new file mode 100644 index 0000000000000..6f147c2a05776 --- /dev/null +++ b/libclc/test/binding/ocl/frexp.cl @@ -0,0 +1,389 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_frexp(__clc_fp32_t args_0, __clc_int32_t __local *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_frexp(__clc_vec2_fp32_t args_0, + __clc_vec2_int32_t __local *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_frexp(__clc_vec3_fp32_t args_0, + __clc_vec3_int32_t __local *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_frexp(__clc_vec4_fp32_t args_0, + __clc_vec4_int32_t __local *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_frexp(__clc_vec8_fp32_t args_0, + __clc_vec8_int32_t __local *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_frexp(__clc_vec16_fp32_t args_0, + __clc_vec16_int32_t __local *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_frexp(__clc_fp64_t args_0, __clc_int32_t __local *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_frexp(__clc_vec2_fp64_t args_0, + __clc_vec2_int32_t __local *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_frexp(__clc_vec3_fp64_t args_0, + __clc_vec3_int32_t __local *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_frexp(__clc_vec4_fp64_t args_0, + __clc_vec4_int32_t __local *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_frexp(__clc_vec8_fp64_t args_0, + __clc_vec8_int32_t __local *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_frexp(__clc_vec16_fp64_t args_0, + __clc_vec16_int32_t __local *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_frexp(__clc_fp16_t args_0, __clc_int32_t __local *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_frexp(__clc_vec2_fp16_t args_0, + __clc_vec2_int32_t __local *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_frexp(__clc_vec3_fp16_t args_0, + __clc_vec3_int32_t __local *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_frexp(__clc_vec4_fp16_t args_0, + __clc_vec4_int32_t __local *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_frexp(__clc_vec8_fp16_t args_0, + __clc_vec8_int32_t __local *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_frexp(__clc_vec16_fp16_t args_0, + __clc_vec16_int32_t __local *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_frexp(__clc_fp32_t args_0, __clc_int32_t *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_frexp(__clc_vec2_fp32_t args_0, __clc_vec2_int32_t *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_frexp(__clc_vec3_fp32_t args_0, __clc_vec3_int32_t *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_frexp(__clc_vec4_fp32_t args_0, __clc_vec4_int32_t *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_frexp(__clc_vec8_fp32_t args_0, __clc_vec8_int32_t *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_frexp(__clc_vec16_fp32_t args_0, __clc_vec16_int32_t *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_frexp(__clc_fp64_t args_0, __clc_int32_t *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_frexp(__clc_vec2_fp64_t args_0, __clc_vec2_int32_t *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_frexp(__clc_vec3_fp64_t args_0, __clc_vec3_int32_t *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_frexp(__clc_vec4_fp64_t args_0, __clc_vec4_int32_t *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_frexp(__clc_vec8_fp64_t args_0, __clc_vec8_int32_t *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_frexp(__clc_vec16_fp64_t args_0, __clc_vec16_int32_t *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_frexp(__clc_fp16_t args_0, __clc_int32_t *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_frexp(__clc_vec2_fp16_t args_0, __clc_vec2_int32_t *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_frexp(__clc_vec3_fp16_t args_0, __clc_vec3_int32_t *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_frexp(__clc_vec4_fp16_t args_0, __clc_vec4_int32_t *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_frexp(__clc_vec8_fp16_t args_0, __clc_vec8_int32_t *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_frexp(__clc_vec16_fp16_t args_0, __clc_vec16_int32_t *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_frexp(__clc_fp32_t args_0, __clc_int32_t __global *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_frexp(__clc_vec2_fp32_t args_0, + __clc_vec2_int32_t __global *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_frexp(__clc_vec3_fp32_t args_0, + __clc_vec3_int32_t __global *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_frexp(__clc_vec4_fp32_t args_0, + __clc_vec4_int32_t __global *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_frexp(__clc_vec8_fp32_t args_0, + __clc_vec8_int32_t __global *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_frexp(__clc_vec16_fp32_t args_0, + __clc_vec16_int32_t __global *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_frexp(__clc_fp64_t args_0, __clc_int32_t __global *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_frexp(__clc_vec2_fp64_t args_0, + __clc_vec2_int32_t __global *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_frexp(__clc_vec3_fp64_t args_0, + __clc_vec3_int32_t __global *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_frexp(__clc_vec4_fp64_t args_0, + __clc_vec4_int32_t __global *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_frexp(__clc_vec8_fp64_t args_0, + __clc_vec8_int32_t __global *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_frexp(__clc_vec16_fp64_t args_0, + __clc_vec16_int32_t __global *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_frexp(__clc_fp16_t args_0, __clc_int32_t __global *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_frexp(__clc_vec2_fp16_t args_0, + __clc_vec2_int32_t __global *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_frexp(__clc_vec3_fp16_t args_0, + __clc_vec3_int32_t __global *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_frexp(__clc_vec4_fp16_t args_0, + __clc_vec4_int32_t __global *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_frexp(__clc_vec8_fp16_t args_0, + __clc_vec8_int32_t __global *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_frexp(__clc_vec16_fp16_t args_0, + __clc_vec16_int32_t __global *args_1) { + return __spirv_ocl_frexp(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/half_cos.cl b/libclc/test/binding/ocl/half_cos.cl new file mode 100644 index 0000000000000..513e84f02f499 --- /dev/null +++ b/libclc/test/binding/ocl/half_cos.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_half_cos(__clc_fp32_t args_0) { + return __spirv_ocl_half_cos(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_half_cos(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_half_cos(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_half_cos(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_half_cos(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_half_cos(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_half_cos(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_half_cos(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_half_cos(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_half_cos(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_half_cos(args_0); +} diff --git a/libclc/test/binding/ocl/half_divide.cl b/libclc/test/binding/ocl/half_divide.cl new file mode 100644 index 0000000000000..826807c37c9cf --- /dev/null +++ b/libclc/test/binding/ocl/half_divide.cl @@ -0,0 +1,51 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_half_divide(__clc_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_ocl_half_divide(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_half_divide(__clc_vec2_fp32_t args_0, + __clc_vec2_fp32_t args_1) { + return __spirv_ocl_half_divide(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_half_divide(__clc_vec3_fp32_t args_0, + __clc_vec3_fp32_t args_1) { + return __spirv_ocl_half_divide(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_half_divide(__clc_vec4_fp32_t args_0, + __clc_vec4_fp32_t args_1) { + return __spirv_ocl_half_divide(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_half_divide(__clc_vec8_fp32_t args_0, + __clc_vec8_fp32_t args_1) { + return __spirv_ocl_half_divide(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_half_divide(__clc_vec16_fp32_t args_0, + __clc_vec16_fp32_t args_1) { + return __spirv_ocl_half_divide(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/half_exp.cl b/libclc/test/binding/ocl/half_exp.cl new file mode 100644 index 0000000000000..3d99aa9d8aa39 --- /dev/null +++ b/libclc/test/binding/ocl/half_exp.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_half_exp(__clc_fp32_t args_0) { + return __spirv_ocl_half_exp(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_half_exp(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_half_exp(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_half_exp(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_half_exp(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_half_exp(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_half_exp(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_half_exp(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_half_exp(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_half_exp(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_half_exp(args_0); +} diff --git a/libclc/test/binding/ocl/half_exp10.cl b/libclc/test/binding/ocl/half_exp10.cl new file mode 100644 index 0000000000000..f68d7acd41e03 --- /dev/null +++ b/libclc/test/binding/ocl/half_exp10.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_half_exp10(__clc_fp32_t args_0) { + return __spirv_ocl_half_exp10(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_half_exp10(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_half_exp10(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_half_exp10(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_half_exp10(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_half_exp10(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_half_exp10(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_half_exp10(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_half_exp10(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_half_exp10(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_half_exp10(args_0); +} diff --git a/libclc/test/binding/ocl/half_exp2.cl b/libclc/test/binding/ocl/half_exp2.cl new file mode 100644 index 0000000000000..e46618c1a175b --- /dev/null +++ b/libclc/test/binding/ocl/half_exp2.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_half_exp2(__clc_fp32_t args_0) { + return __spirv_ocl_half_exp2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_half_exp2(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_half_exp2(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_half_exp2(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_half_exp2(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_half_exp2(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_half_exp2(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_half_exp2(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_half_exp2(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_half_exp2(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_half_exp2(args_0); +} diff --git a/libclc/test/binding/ocl/half_log.cl b/libclc/test/binding/ocl/half_log.cl new file mode 100644 index 0000000000000..9d26597b160b6 --- /dev/null +++ b/libclc/test/binding/ocl/half_log.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_half_log(__clc_fp32_t args_0) { + return __spirv_ocl_half_log(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_half_log(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_half_log(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_half_log(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_half_log(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_half_log(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_half_log(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_half_log(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_half_log(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_half_log(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_half_log(args_0); +} diff --git a/libclc/test/binding/ocl/half_log10.cl b/libclc/test/binding/ocl/half_log10.cl new file mode 100644 index 0000000000000..04c0ebf7df19c --- /dev/null +++ b/libclc/test/binding/ocl/half_log10.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_half_log10(__clc_fp32_t args_0) { + return __spirv_ocl_half_log10(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_half_log10(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_half_log10(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_half_log10(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_half_log10(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_half_log10(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_half_log10(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_half_log10(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_half_log10(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_half_log10(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_half_log10(args_0); +} diff --git a/libclc/test/binding/ocl/half_log2.cl b/libclc/test/binding/ocl/half_log2.cl new file mode 100644 index 0000000000000..6f3ddb980e4f7 --- /dev/null +++ b/libclc/test/binding/ocl/half_log2.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_half_log2(__clc_fp32_t args_0) { + return __spirv_ocl_half_log2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_half_log2(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_half_log2(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_half_log2(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_half_log2(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_half_log2(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_half_log2(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_half_log2(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_half_log2(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_half_log2(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_half_log2(args_0); +} diff --git a/libclc/test/binding/ocl/half_powr.cl b/libclc/test/binding/ocl/half_powr.cl new file mode 100644 index 0000000000000..a1e3e05484b65 --- /dev/null +++ b/libclc/test/binding/ocl/half_powr.cl @@ -0,0 +1,47 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_half_powr(__clc_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_ocl_half_powr(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_half_powr(__clc_vec2_fp32_t args_0, __clc_vec2_fp32_t args_1) { + return __spirv_ocl_half_powr(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_half_powr(__clc_vec3_fp32_t args_0, __clc_vec3_fp32_t args_1) { + return __spirv_ocl_half_powr(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_half_powr(__clc_vec4_fp32_t args_0, __clc_vec4_fp32_t args_1) { + return __spirv_ocl_half_powr(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_half_powr(__clc_vec8_fp32_t args_0, __clc_vec8_fp32_t args_1) { + return __spirv_ocl_half_powr(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_half_powr(__clc_vec16_fp32_t args_0, + __clc_vec16_fp32_t args_1) { + return __spirv_ocl_half_powr(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/half_recip.cl b/libclc/test/binding/ocl/half_recip.cl new file mode 100644 index 0000000000000..d6536e484edd9 --- /dev/null +++ b/libclc/test/binding/ocl/half_recip.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_half_recip(__clc_fp32_t args_0) { + return __spirv_ocl_half_recip(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_half_recip(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_half_recip(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_half_recip(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_half_recip(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_half_recip(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_half_recip(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_half_recip(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_half_recip(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_half_recip(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_half_recip(args_0); +} diff --git a/libclc/test/binding/ocl/half_sin.cl b/libclc/test/binding/ocl/half_sin.cl new file mode 100644 index 0000000000000..07a45bd031c50 --- /dev/null +++ b/libclc/test/binding/ocl/half_sin.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_half_sin(__clc_fp32_t args_0) { + return __spirv_ocl_half_sin(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_half_sin(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_half_sin(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_half_sin(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_half_sin(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_half_sin(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_half_sin(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_half_sin(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_half_sin(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_half_sin(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_half_sin(args_0); +} diff --git a/libclc/test/binding/ocl/half_tan.cl b/libclc/test/binding/ocl/half_tan.cl new file mode 100644 index 0000000000000..5af2180570fdf --- /dev/null +++ b/libclc/test/binding/ocl/half_tan.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_half_tan(__clc_fp32_t args_0) { + return __spirv_ocl_half_tan(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_half_tan(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_half_tan(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_half_tan(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_half_tan(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_half_tan(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_half_tan(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_half_tan(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_half_tan(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_half_tan(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_half_tan(args_0); +} diff --git a/libclc/test/binding/ocl/hypot.cl b/libclc/test/binding/ocl/hypot.cl new file mode 100644 index 0000000000000..cbc14d74ab727 --- /dev/null +++ b/libclc/test/binding/ocl/hypot.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_hypot(__clc_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_ocl_hypot(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_hypot(__clc_vec2_fp32_t args_0, __clc_vec2_fp32_t args_1) { + return __spirv_ocl_hypot(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_hypot(__clc_vec3_fp32_t args_0, __clc_vec3_fp32_t args_1) { + return __spirv_ocl_hypot(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_hypot(__clc_vec4_fp32_t args_0, __clc_vec4_fp32_t args_1) { + return __spirv_ocl_hypot(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_hypot(__clc_vec8_fp32_t args_0, __clc_vec8_fp32_t args_1) { + return __spirv_ocl_hypot(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_hypot(__clc_vec16_fp32_t args_0, __clc_vec16_fp32_t args_1) { + return __spirv_ocl_hypot(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_hypot(__clc_fp64_t args_0, __clc_fp64_t args_1) { + return __spirv_ocl_hypot(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_hypot(__clc_vec2_fp64_t args_0, __clc_vec2_fp64_t args_1) { + return __spirv_ocl_hypot(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_hypot(__clc_vec3_fp64_t args_0, __clc_vec3_fp64_t args_1) { + return __spirv_ocl_hypot(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_hypot(__clc_vec4_fp64_t args_0, __clc_vec4_fp64_t args_1) { + return __spirv_ocl_hypot(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_hypot(__clc_vec8_fp64_t args_0, __clc_vec8_fp64_t args_1) { + return __spirv_ocl_hypot(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_hypot(__clc_vec16_fp64_t args_0, __clc_vec16_fp64_t args_1) { + return __spirv_ocl_hypot(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_hypot(__clc_fp16_t args_0, __clc_fp16_t args_1) { + return __spirv_ocl_hypot(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_hypot(__clc_vec2_fp16_t args_0, __clc_vec2_fp16_t args_1) { + return __spirv_ocl_hypot(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_hypot(__clc_vec3_fp16_t args_0, __clc_vec3_fp16_t args_1) { + return __spirv_ocl_hypot(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_hypot(__clc_vec4_fp16_t args_0, __clc_vec4_fp16_t args_1) { + return __spirv_ocl_hypot(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_hypot(__clc_vec8_fp16_t args_0, __clc_vec8_fp16_t args_1) { + return __spirv_ocl_hypot(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_hypot(__clc_vec16_fp16_t args_0, __clc_vec16_fp16_t args_1) { + return __spirv_ocl_hypot(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/ilogb.cl b/libclc/test/binding/ocl/ilogb.cl new file mode 100644 index 0000000000000..6a909fb50cddc --- /dev/null +++ b/libclc/test/binding/ocl/ilogb.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int32_t +test___spirv_ocl_ilogb(__clc_fp32_t args_0) { + return __spirv_ocl_ilogb(args_0); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ocl_ilogb(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_ilogb(args_0); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ocl_ilogb(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_ilogb(args_0); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ocl_ilogb(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_ilogb(args_0); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ocl_ilogb(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_ilogb(args_0); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ocl_ilogb(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_ilogb(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_int32_t +test___spirv_ocl_ilogb(__clc_fp64_t args_0) { + return __spirv_ocl_ilogb(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ocl_ilogb(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_ilogb(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ocl_ilogb(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_ilogb(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ocl_ilogb(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_ilogb(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ocl_ilogb(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_ilogb(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ocl_ilogb(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_ilogb(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_int32_t +test___spirv_ocl_ilogb(__clc_fp16_t args_0) { + return __spirv_ocl_ilogb(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ocl_ilogb(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_ilogb(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ocl_ilogb(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_ilogb(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ocl_ilogb(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_ilogb(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ocl_ilogb(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_ilogb(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ocl_ilogb(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_ilogb(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/ldexp.cl b/libclc/test/binding/ocl/ldexp.cl new file mode 100644 index 0000000000000..e43e292e9a451 --- /dev/null +++ b/libclc/test/binding/ocl/ldexp.cl @@ -0,0 +1,245 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_ldexp(__clc_fp32_t args_0, __clc_int32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_ldexp(__clc_vec2_fp32_t args_0, __clc_vec2_int32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_ldexp(__clc_vec3_fp32_t args_0, __clc_vec3_int32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_ldexp(__clc_vec4_fp32_t args_0, __clc_vec4_int32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_ldexp(__clc_vec8_fp32_t args_0, __clc_vec8_int32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_ldexp(__clc_vec16_fp32_t args_0, __clc_vec16_int32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_ldexp(__clc_fp32_t args_0, __clc_uint32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_ldexp(__clc_vec2_fp32_t args_0, __clc_vec2_uint32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_ldexp(__clc_vec3_fp32_t args_0, __clc_vec3_uint32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_ldexp(__clc_vec4_fp32_t args_0, __clc_vec4_uint32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_ldexp(__clc_vec8_fp32_t args_0, __clc_vec8_uint32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_ldexp(__clc_vec16_fp32_t args_0, __clc_vec16_uint32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_ldexp(__clc_fp64_t args_0, __clc_int32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_ldexp(__clc_vec2_fp64_t args_0, __clc_vec2_int32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_ldexp(__clc_vec3_fp64_t args_0, __clc_vec3_int32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_ldexp(__clc_vec4_fp64_t args_0, __clc_vec4_int32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_ldexp(__clc_vec8_fp64_t args_0, __clc_vec8_int32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_ldexp(__clc_vec16_fp64_t args_0, __clc_vec16_int32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_ldexp(__clc_fp64_t args_0, __clc_uint32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_ldexp(__clc_vec2_fp64_t args_0, __clc_vec2_uint32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_ldexp(__clc_vec3_fp64_t args_0, __clc_vec3_uint32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_ldexp(__clc_vec4_fp64_t args_0, __clc_vec4_uint32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_ldexp(__clc_vec8_fp64_t args_0, __clc_vec8_uint32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_ldexp(__clc_vec16_fp64_t args_0, __clc_vec16_uint32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_ldexp(__clc_fp16_t args_0, __clc_int32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_ldexp(__clc_vec2_fp16_t args_0, __clc_vec2_int32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_ldexp(__clc_vec3_fp16_t args_0, __clc_vec3_int32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_ldexp(__clc_vec4_fp16_t args_0, __clc_vec4_int32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_ldexp(__clc_vec8_fp16_t args_0, __clc_vec8_int32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_ldexp(__clc_vec16_fp16_t args_0, __clc_vec16_int32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_ldexp(__clc_fp16_t args_0, __clc_uint32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_ldexp(__clc_vec2_fp16_t args_0, __clc_vec2_uint32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_ldexp(__clc_vec3_fp16_t args_0, __clc_vec3_uint32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_ldexp(__clc_vec4_fp16_t args_0, __clc_vec4_uint32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_ldexp(__clc_vec8_fp16_t args_0, __clc_vec8_uint32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_ldexp(__clc_vec16_fp16_t args_0, __clc_vec16_uint32_t args_1) { + return __spirv_ocl_ldexp(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/lgamma.cl b/libclc/test/binding/ocl/lgamma.cl new file mode 100644 index 0000000000000..5889623562c98 --- /dev/null +++ b/libclc/test/binding/ocl/lgamma.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_lgamma(__clc_fp32_t args_0) { + return __spirv_ocl_lgamma(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_lgamma(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_lgamma(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_lgamma(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_lgamma(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_lgamma(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_lgamma(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_lgamma(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_lgamma(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_lgamma(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_lgamma(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_lgamma(__clc_fp64_t args_0) { + return __spirv_ocl_lgamma(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_lgamma(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_lgamma(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_lgamma(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_lgamma(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_lgamma(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_lgamma(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_lgamma(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_lgamma(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_lgamma(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_lgamma(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_lgamma(__clc_fp16_t args_0) { + return __spirv_ocl_lgamma(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_lgamma(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_lgamma(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_lgamma(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_lgamma(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_lgamma(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_lgamma(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_lgamma(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_lgamma(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_lgamma(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_lgamma(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/lgamma_r.cl b/libclc/test/binding/ocl/lgamma_r.cl new file mode 100644 index 0000000000000..8a3f5ca201895 --- /dev/null +++ b/libclc/test/binding/ocl/lgamma_r.cl @@ -0,0 +1,404 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_lgamma_r(__clc_fp32_t args_0, __clc_int32_t __local *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_lgamma_r(__clc_vec2_fp32_t args_0, + __clc_vec2_int32_t __local *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_lgamma_r(__clc_vec3_fp32_t args_0, + __clc_vec3_int32_t __local *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_lgamma_r(__clc_vec4_fp32_t args_0, + __clc_vec4_int32_t __local *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_lgamma_r(__clc_vec8_fp32_t args_0, + __clc_vec8_int32_t __local *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_lgamma_r(__clc_vec16_fp32_t args_0, + __clc_vec16_int32_t __local *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_lgamma_r(__clc_fp64_t args_0, __clc_int32_t __local *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_lgamma_r(__clc_vec2_fp64_t args_0, + __clc_vec2_int32_t __local *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_lgamma_r(__clc_vec3_fp64_t args_0, + __clc_vec3_int32_t __local *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_lgamma_r(__clc_vec4_fp64_t args_0, + __clc_vec4_int32_t __local *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_lgamma_r(__clc_vec8_fp64_t args_0, + __clc_vec8_int32_t __local *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_lgamma_r(__clc_vec16_fp64_t args_0, + __clc_vec16_int32_t __local *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_lgamma_r(__clc_fp16_t args_0, __clc_int32_t __local *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_lgamma_r(__clc_vec2_fp16_t args_0, + __clc_vec2_int32_t __local *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_lgamma_r(__clc_vec3_fp16_t args_0, + __clc_vec3_int32_t __local *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_lgamma_r(__clc_vec4_fp16_t args_0, + __clc_vec4_int32_t __local *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_lgamma_r(__clc_vec8_fp16_t args_0, + __clc_vec8_int32_t __local *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_lgamma_r(__clc_vec16_fp16_t args_0, + __clc_vec16_int32_t __local *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_lgamma_r(__clc_fp32_t args_0, __clc_int32_t *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_lgamma_r(__clc_vec2_fp32_t args_0, + __clc_vec2_int32_t *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_lgamma_r(__clc_vec3_fp32_t args_0, + __clc_vec3_int32_t *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_lgamma_r(__clc_vec4_fp32_t args_0, + __clc_vec4_int32_t *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_lgamma_r(__clc_vec8_fp32_t args_0, + __clc_vec8_int32_t *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_lgamma_r(__clc_vec16_fp32_t args_0, + __clc_vec16_int32_t *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_lgamma_r(__clc_fp64_t args_0, __clc_int32_t *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_lgamma_r(__clc_vec2_fp64_t args_0, + __clc_vec2_int32_t *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_lgamma_r(__clc_vec3_fp64_t args_0, + __clc_vec3_int32_t *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_lgamma_r(__clc_vec4_fp64_t args_0, + __clc_vec4_int32_t *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_lgamma_r(__clc_vec8_fp64_t args_0, + __clc_vec8_int32_t *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_lgamma_r(__clc_vec16_fp64_t args_0, + __clc_vec16_int32_t *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_lgamma_r(__clc_fp16_t args_0, __clc_int32_t *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_lgamma_r(__clc_vec2_fp16_t args_0, + __clc_vec2_int32_t *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_lgamma_r(__clc_vec3_fp16_t args_0, + __clc_vec3_int32_t *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_lgamma_r(__clc_vec4_fp16_t args_0, + __clc_vec4_int32_t *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_lgamma_r(__clc_vec8_fp16_t args_0, + __clc_vec8_int32_t *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_lgamma_r(__clc_vec16_fp16_t args_0, + __clc_vec16_int32_t *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_lgamma_r(__clc_fp32_t args_0, __clc_int32_t __global *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_lgamma_r(__clc_vec2_fp32_t args_0, + __clc_vec2_int32_t __global *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_lgamma_r(__clc_vec3_fp32_t args_0, + __clc_vec3_int32_t __global *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_lgamma_r(__clc_vec4_fp32_t args_0, + __clc_vec4_int32_t __global *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_lgamma_r(__clc_vec8_fp32_t args_0, + __clc_vec8_int32_t __global *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_lgamma_r(__clc_vec16_fp32_t args_0, + __clc_vec16_int32_t __global *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_lgamma_r(__clc_fp64_t args_0, __clc_int32_t __global *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_lgamma_r(__clc_vec2_fp64_t args_0, + __clc_vec2_int32_t __global *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_lgamma_r(__clc_vec3_fp64_t args_0, + __clc_vec3_int32_t __global *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_lgamma_r(__clc_vec4_fp64_t args_0, + __clc_vec4_int32_t __global *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_lgamma_r(__clc_vec8_fp64_t args_0, + __clc_vec8_int32_t __global *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_lgamma_r(__clc_vec16_fp64_t args_0, + __clc_vec16_int32_t __global *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_lgamma_r(__clc_fp16_t args_0, __clc_int32_t __global *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_lgamma_r(__clc_vec2_fp16_t args_0, + __clc_vec2_int32_t __global *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_lgamma_r(__clc_vec3_fp16_t args_0, + __clc_vec3_int32_t __global *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_lgamma_r(__clc_vec4_fp16_t args_0, + __clc_vec4_int32_t __global *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_lgamma_r(__clc_vec8_fp16_t args_0, + __clc_vec8_int32_t __global *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_lgamma_r(__clc_vec16_fp16_t args_0, + __clc_vec16_int32_t __global *args_1) { + return __spirv_ocl_lgamma_r(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/log.cl b/libclc/test/binding/ocl/log.cl new file mode 100644 index 0000000000000..1096d49e3d6ad --- /dev/null +++ b/libclc/test/binding/ocl/log.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_log(__clc_fp32_t args_0) { + return __spirv_ocl_log(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_log(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_log(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_log(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_log(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_log(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_log(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_log(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_log(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_log(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_log(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_log(__clc_fp64_t args_0) { + return __spirv_ocl_log(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_log(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_log(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_log(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_log(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_log(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_log(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_log(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_log(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_log(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_log(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_log(__clc_fp16_t args_0) { + return __spirv_ocl_log(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_log(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_log(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_log(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_log(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_log(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_log(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_log(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_log(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_log(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_log(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/log10.cl b/libclc/test/binding/ocl/log10.cl new file mode 100644 index 0000000000000..1a1cba18149a5 --- /dev/null +++ b/libclc/test/binding/ocl/log10.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_log10(__clc_fp32_t args_0) { + return __spirv_ocl_log10(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_log10(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_log10(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_log10(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_log10(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_log10(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_log10(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_log10(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_log10(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_log10(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_log10(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_log10(__clc_fp64_t args_0) { + return __spirv_ocl_log10(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_log10(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_log10(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_log10(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_log10(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_log10(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_log10(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_log10(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_log10(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_log10(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_log10(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_log10(__clc_fp16_t args_0) { + return __spirv_ocl_log10(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_log10(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_log10(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_log10(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_log10(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_log10(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_log10(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_log10(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_log10(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_log10(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_log10(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/log1p.cl b/libclc/test/binding/ocl/log1p.cl new file mode 100644 index 0000000000000..2f647a70a7557 --- /dev/null +++ b/libclc/test/binding/ocl/log1p.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_log1p(__clc_fp32_t args_0) { + return __spirv_ocl_log1p(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_log1p(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_log1p(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_log1p(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_log1p(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_log1p(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_log1p(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_log1p(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_log1p(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_log1p(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_log1p(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_log1p(__clc_fp64_t args_0) { + return __spirv_ocl_log1p(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_log1p(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_log1p(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_log1p(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_log1p(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_log1p(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_log1p(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_log1p(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_log1p(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_log1p(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_log1p(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_log1p(__clc_fp16_t args_0) { + return __spirv_ocl_log1p(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_log1p(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_log1p(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_log1p(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_log1p(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_log1p(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_log1p(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_log1p(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_log1p(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_log1p(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_log1p(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/log2.cl b/libclc/test/binding/ocl/log2.cl new file mode 100644 index 0000000000000..499309bda4be7 --- /dev/null +++ b/libclc/test/binding/ocl/log2.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_log2(__clc_fp32_t args_0) { + return __spirv_ocl_log2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_log2(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_log2(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_log2(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_log2(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_log2(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_log2(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_log2(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_log2(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_log2(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_log2(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_log2(__clc_fp64_t args_0) { + return __spirv_ocl_log2(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_log2(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_log2(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_log2(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_log2(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_log2(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_log2(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_log2(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_log2(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_log2(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_log2(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_log2(__clc_fp16_t args_0) { + return __spirv_ocl_log2(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_log2(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_log2(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_log2(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_log2(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_log2(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_log2(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_log2(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_log2(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_log2(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_log2(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/logb.cl b/libclc/test/binding/ocl/logb.cl new file mode 100644 index 0000000000000..152bcc3cdab96 --- /dev/null +++ b/libclc/test/binding/ocl/logb.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_logb(__clc_fp32_t args_0) { + return __spirv_ocl_logb(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_logb(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_logb(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_logb(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_logb(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_logb(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_logb(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_logb(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_logb(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_logb(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_logb(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_logb(__clc_fp64_t args_0) { + return __spirv_ocl_logb(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_logb(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_logb(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_logb(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_logb(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_logb(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_logb(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_logb(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_logb(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_logb(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_logb(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_logb(__clc_fp16_t args_0) { + return __spirv_ocl_logb(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_logb(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_logb(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_logb(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_logb(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_logb(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_logb(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_logb(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_logb(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_logb(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_logb(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/mad.cl b/libclc/test/binding/ocl/mad.cl new file mode 100644 index 0000000000000..f1e78cc569546 --- /dev/null +++ b/libclc/test/binding/ocl/mad.cl @@ -0,0 +1,149 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_mad(__clc_fp32_t args_0, __clc_fp32_t args_1, + __clc_fp32_t args_2) { + return __spirv_ocl_mad(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_mad(__clc_vec2_fp32_t args_0, __clc_vec2_fp32_t args_1, + __clc_vec2_fp32_t args_2) { + return __spirv_ocl_mad(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_mad(__clc_vec3_fp32_t args_0, __clc_vec3_fp32_t args_1, + __clc_vec3_fp32_t args_2) { + return __spirv_ocl_mad(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_mad(__clc_vec4_fp32_t args_0, __clc_vec4_fp32_t args_1, + __clc_vec4_fp32_t args_2) { + return __spirv_ocl_mad(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_mad(__clc_vec8_fp32_t args_0, __clc_vec8_fp32_t args_1, + __clc_vec8_fp32_t args_2) { + return __spirv_ocl_mad(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_mad(__clc_vec16_fp32_t args_0, __clc_vec16_fp32_t args_1, + __clc_vec16_fp32_t args_2) { + return __spirv_ocl_mad(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_mad(__clc_fp64_t args_0, __clc_fp64_t args_1, + __clc_fp64_t args_2) { + return __spirv_ocl_mad(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_mad(__clc_vec2_fp64_t args_0, __clc_vec2_fp64_t args_1, + __clc_vec2_fp64_t args_2) { + return __spirv_ocl_mad(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_mad(__clc_vec3_fp64_t args_0, __clc_vec3_fp64_t args_1, + __clc_vec3_fp64_t args_2) { + return __spirv_ocl_mad(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_mad(__clc_vec4_fp64_t args_0, __clc_vec4_fp64_t args_1, + __clc_vec4_fp64_t args_2) { + return __spirv_ocl_mad(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_mad(__clc_vec8_fp64_t args_0, __clc_vec8_fp64_t args_1, + __clc_vec8_fp64_t args_2) { + return __spirv_ocl_mad(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_mad(__clc_vec16_fp64_t args_0, __clc_vec16_fp64_t args_1, + __clc_vec16_fp64_t args_2) { + return __spirv_ocl_mad(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_mad(__clc_fp16_t args_0, __clc_fp16_t args_1, + __clc_fp16_t args_2) { + return __spirv_ocl_mad(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_mad(__clc_vec2_fp16_t args_0, __clc_vec2_fp16_t args_1, + __clc_vec2_fp16_t args_2) { + return __spirv_ocl_mad(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_mad(__clc_vec3_fp16_t args_0, __clc_vec3_fp16_t args_1, + __clc_vec3_fp16_t args_2) { + return __spirv_ocl_mad(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_mad(__clc_vec4_fp16_t args_0, __clc_vec4_fp16_t args_1, + __clc_vec4_fp16_t args_2) { + return __spirv_ocl_mad(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_mad(__clc_vec8_fp16_t args_0, __clc_vec8_fp16_t args_1, + __clc_vec8_fp16_t args_2) { + return __spirv_ocl_mad(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_mad(__clc_vec16_fp16_t args_0, __clc_vec16_fp16_t args_1, + __clc_vec16_fp16_t args_2) { + return __spirv_ocl_mad(args_0, args_1, args_2); +} + +#endif diff --git a/libclc/test/binding/ocl/maxmag.cl b/libclc/test/binding/ocl/maxmag.cl new file mode 100644 index 0000000000000..5205d9a08558f --- /dev/null +++ b/libclc/test/binding/ocl/maxmag.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_maxmag(__clc_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_ocl_maxmag(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_maxmag(__clc_vec2_fp32_t args_0, __clc_vec2_fp32_t args_1) { + return __spirv_ocl_maxmag(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_maxmag(__clc_vec3_fp32_t args_0, __clc_vec3_fp32_t args_1) { + return __spirv_ocl_maxmag(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_maxmag(__clc_vec4_fp32_t args_0, __clc_vec4_fp32_t args_1) { + return __spirv_ocl_maxmag(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_maxmag(__clc_vec8_fp32_t args_0, __clc_vec8_fp32_t args_1) { + return __spirv_ocl_maxmag(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_maxmag(__clc_vec16_fp32_t args_0, __clc_vec16_fp32_t args_1) { + return __spirv_ocl_maxmag(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_maxmag(__clc_fp64_t args_0, __clc_fp64_t args_1) { + return __spirv_ocl_maxmag(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_maxmag(__clc_vec2_fp64_t args_0, __clc_vec2_fp64_t args_1) { + return __spirv_ocl_maxmag(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_maxmag(__clc_vec3_fp64_t args_0, __clc_vec3_fp64_t args_1) { + return __spirv_ocl_maxmag(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_maxmag(__clc_vec4_fp64_t args_0, __clc_vec4_fp64_t args_1) { + return __spirv_ocl_maxmag(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_maxmag(__clc_vec8_fp64_t args_0, __clc_vec8_fp64_t args_1) { + return __spirv_ocl_maxmag(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_maxmag(__clc_vec16_fp64_t args_0, __clc_vec16_fp64_t args_1) { + return __spirv_ocl_maxmag(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_maxmag(__clc_fp16_t args_0, __clc_fp16_t args_1) { + return __spirv_ocl_maxmag(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_maxmag(__clc_vec2_fp16_t args_0, __clc_vec2_fp16_t args_1) { + return __spirv_ocl_maxmag(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_maxmag(__clc_vec3_fp16_t args_0, __clc_vec3_fp16_t args_1) { + return __spirv_ocl_maxmag(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_maxmag(__clc_vec4_fp16_t args_0, __clc_vec4_fp16_t args_1) { + return __spirv_ocl_maxmag(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_maxmag(__clc_vec8_fp16_t args_0, __clc_vec8_fp16_t args_1) { + return __spirv_ocl_maxmag(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_maxmag(__clc_vec16_fp16_t args_0, __clc_vec16_fp16_t args_1) { + return __spirv_ocl_maxmag(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/minmag.cl b/libclc/test/binding/ocl/minmag.cl new file mode 100644 index 0000000000000..b05255d558659 --- /dev/null +++ b/libclc/test/binding/ocl/minmag.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_minmag(__clc_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_ocl_minmag(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_minmag(__clc_vec2_fp32_t args_0, __clc_vec2_fp32_t args_1) { + return __spirv_ocl_minmag(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_minmag(__clc_vec3_fp32_t args_0, __clc_vec3_fp32_t args_1) { + return __spirv_ocl_minmag(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_minmag(__clc_vec4_fp32_t args_0, __clc_vec4_fp32_t args_1) { + return __spirv_ocl_minmag(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_minmag(__clc_vec8_fp32_t args_0, __clc_vec8_fp32_t args_1) { + return __spirv_ocl_minmag(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_minmag(__clc_vec16_fp32_t args_0, __clc_vec16_fp32_t args_1) { + return __spirv_ocl_minmag(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_minmag(__clc_fp64_t args_0, __clc_fp64_t args_1) { + return __spirv_ocl_minmag(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_minmag(__clc_vec2_fp64_t args_0, __clc_vec2_fp64_t args_1) { + return __spirv_ocl_minmag(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_minmag(__clc_vec3_fp64_t args_0, __clc_vec3_fp64_t args_1) { + return __spirv_ocl_minmag(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_minmag(__clc_vec4_fp64_t args_0, __clc_vec4_fp64_t args_1) { + return __spirv_ocl_minmag(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_minmag(__clc_vec8_fp64_t args_0, __clc_vec8_fp64_t args_1) { + return __spirv_ocl_minmag(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_minmag(__clc_vec16_fp64_t args_0, __clc_vec16_fp64_t args_1) { + return __spirv_ocl_minmag(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_minmag(__clc_fp16_t args_0, __clc_fp16_t args_1) { + return __spirv_ocl_minmag(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_minmag(__clc_vec2_fp16_t args_0, __clc_vec2_fp16_t args_1) { + return __spirv_ocl_minmag(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_minmag(__clc_vec3_fp16_t args_0, __clc_vec3_fp16_t args_1) { + return __spirv_ocl_minmag(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_minmag(__clc_vec4_fp16_t args_0, __clc_vec4_fp16_t args_1) { + return __spirv_ocl_minmag(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_minmag(__clc_vec8_fp16_t args_0, __clc_vec8_fp16_t args_1) { + return __spirv_ocl_minmag(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_minmag(__clc_vec16_fp16_t args_0, __clc_vec16_fp16_t args_1) { + return __spirv_ocl_minmag(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/modf.cl b/libclc/test/binding/ocl/modf.cl new file mode 100644 index 0000000000000..cae70177d308c --- /dev/null +++ b/libclc/test/binding/ocl/modf.cl @@ -0,0 +1,389 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_modf(__clc_fp32_t args_0, __clc_fp32_t __local *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_modf(__clc_vec2_fp32_t args_0, + __clc_vec2_fp32_t __local *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_modf(__clc_vec3_fp32_t args_0, + __clc_vec3_fp32_t __local *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_modf(__clc_vec4_fp32_t args_0, + __clc_vec4_fp32_t __local *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_modf(__clc_vec8_fp32_t args_0, + __clc_vec8_fp32_t __local *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_modf(__clc_vec16_fp32_t args_0, + __clc_vec16_fp32_t __local *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_modf(__clc_fp64_t args_0, __clc_fp64_t __local *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_modf(__clc_vec2_fp64_t args_0, + __clc_vec2_fp64_t __local *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_modf(__clc_vec3_fp64_t args_0, + __clc_vec3_fp64_t __local *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_modf(__clc_vec4_fp64_t args_0, + __clc_vec4_fp64_t __local *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_modf(__clc_vec8_fp64_t args_0, + __clc_vec8_fp64_t __local *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_modf(__clc_vec16_fp64_t args_0, + __clc_vec16_fp64_t __local *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_modf(__clc_fp16_t args_0, __clc_fp16_t __local *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_modf(__clc_vec2_fp16_t args_0, + __clc_vec2_fp16_t __local *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_modf(__clc_vec3_fp16_t args_0, + __clc_vec3_fp16_t __local *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_modf(__clc_vec4_fp16_t args_0, + __clc_vec4_fp16_t __local *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_modf(__clc_vec8_fp16_t args_0, + __clc_vec8_fp16_t __local *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_modf(__clc_vec16_fp16_t args_0, + __clc_vec16_fp16_t __local *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_modf(__clc_fp32_t args_0, __clc_fp32_t *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_modf(__clc_vec2_fp32_t args_0, __clc_vec2_fp32_t *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_modf(__clc_vec3_fp32_t args_0, __clc_vec3_fp32_t *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_modf(__clc_vec4_fp32_t args_0, __clc_vec4_fp32_t *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_modf(__clc_vec8_fp32_t args_0, __clc_vec8_fp32_t *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_modf(__clc_vec16_fp32_t args_0, __clc_vec16_fp32_t *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_modf(__clc_fp64_t args_0, __clc_fp64_t *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_modf(__clc_vec2_fp64_t args_0, __clc_vec2_fp64_t *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_modf(__clc_vec3_fp64_t args_0, __clc_vec3_fp64_t *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_modf(__clc_vec4_fp64_t args_0, __clc_vec4_fp64_t *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_modf(__clc_vec8_fp64_t args_0, __clc_vec8_fp64_t *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_modf(__clc_vec16_fp64_t args_0, __clc_vec16_fp64_t *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_modf(__clc_fp16_t args_0, __clc_fp16_t *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_modf(__clc_vec2_fp16_t args_0, __clc_vec2_fp16_t *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_modf(__clc_vec3_fp16_t args_0, __clc_vec3_fp16_t *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_modf(__clc_vec4_fp16_t args_0, __clc_vec4_fp16_t *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_modf(__clc_vec8_fp16_t args_0, __clc_vec8_fp16_t *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_modf(__clc_vec16_fp16_t args_0, __clc_vec16_fp16_t *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_modf(__clc_fp32_t args_0, __clc_fp32_t __global *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_modf(__clc_vec2_fp32_t args_0, + __clc_vec2_fp32_t __global *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_modf(__clc_vec3_fp32_t args_0, + __clc_vec3_fp32_t __global *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_modf(__clc_vec4_fp32_t args_0, + __clc_vec4_fp32_t __global *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_modf(__clc_vec8_fp32_t args_0, + __clc_vec8_fp32_t __global *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_modf(__clc_vec16_fp32_t args_0, + __clc_vec16_fp32_t __global *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_modf(__clc_fp64_t args_0, __clc_fp64_t __global *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_modf(__clc_vec2_fp64_t args_0, + __clc_vec2_fp64_t __global *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_modf(__clc_vec3_fp64_t args_0, + __clc_vec3_fp64_t __global *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_modf(__clc_vec4_fp64_t args_0, + __clc_vec4_fp64_t __global *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_modf(__clc_vec8_fp64_t args_0, + __clc_vec8_fp64_t __global *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_modf(__clc_vec16_fp64_t args_0, + __clc_vec16_fp64_t __global *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_modf(__clc_fp16_t args_0, __clc_fp16_t __global *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_modf(__clc_vec2_fp16_t args_0, + __clc_vec2_fp16_t __global *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_modf(__clc_vec3_fp16_t args_0, + __clc_vec3_fp16_t __global *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_modf(__clc_vec4_fp16_t args_0, + __clc_vec4_fp16_t __global *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_modf(__clc_vec8_fp16_t args_0, + __clc_vec8_fp16_t __global *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_modf(__clc_vec16_fp16_t args_0, + __clc_vec16_fp16_t __global *args_1) { + return __spirv_ocl_modf(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/nan.cl b/libclc/test/binding/ocl/nan.cl new file mode 100644 index 0000000000000..c91347c21d05d --- /dev/null +++ b/libclc/test/binding/ocl/nan.cl @@ -0,0 +1,245 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_nan(__clc_int16_t args_0) { + return __spirv_ocl_nan(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_nan(__clc_vec2_int16_t args_0) { + return __spirv_ocl_nan(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_nan(__clc_vec3_int16_t args_0) { + return __spirv_ocl_nan(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_nan(__clc_vec4_int16_t args_0) { + return __spirv_ocl_nan(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_nan(__clc_vec8_int16_t args_0) { + return __spirv_ocl_nan(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_nan(__clc_vec16_int16_t args_0) { + return __spirv_ocl_nan(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_nan(__clc_uint16_t args_0) { + return __spirv_ocl_nan(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_nan(__clc_vec2_uint16_t args_0) { + return __spirv_ocl_nan(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_nan(__clc_vec3_uint16_t args_0) { + return __spirv_ocl_nan(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_nan(__clc_vec4_uint16_t args_0) { + return __spirv_ocl_nan(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_nan(__clc_vec8_uint16_t args_0) { + return __spirv_ocl_nan(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_nan(__clc_vec16_uint16_t args_0) { + return __spirv_ocl_nan(args_0); +} + +#endif +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_nan(__clc_int32_t args_0) { + return __spirv_ocl_nan(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_nan(__clc_vec2_int32_t args_0) { + return __spirv_ocl_nan(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_nan(__clc_vec3_int32_t args_0) { + return __spirv_ocl_nan(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_nan(__clc_vec4_int32_t args_0) { + return __spirv_ocl_nan(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_nan(__clc_vec8_int32_t args_0) { + return __spirv_ocl_nan(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_nan(__clc_vec16_int32_t args_0) { + return __spirv_ocl_nan(args_0); +} + +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_nan(__clc_uint32_t args_0) { + return __spirv_ocl_nan(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_nan(__clc_vec2_uint32_t args_0) { + return __spirv_ocl_nan(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_nan(__clc_vec3_uint32_t args_0) { + return __spirv_ocl_nan(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_nan(__clc_vec4_uint32_t args_0) { + return __spirv_ocl_nan(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_nan(__clc_vec8_uint32_t args_0) { + return __spirv_ocl_nan(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_nan(__clc_vec16_uint32_t args_0) { + return __spirv_ocl_nan(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_nan(__clc_int64_t args_0) { + return __spirv_ocl_nan(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_nan(__clc_vec2_int64_t args_0) { + return __spirv_ocl_nan(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_nan(__clc_vec3_int64_t args_0) { + return __spirv_ocl_nan(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_nan(__clc_vec4_int64_t args_0) { + return __spirv_ocl_nan(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_nan(__clc_vec8_int64_t args_0) { + return __spirv_ocl_nan(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_nan(__clc_vec16_int64_t args_0) { + return __spirv_ocl_nan(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_nan(__clc_uint64_t args_0) { + return __spirv_ocl_nan(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_nan(__clc_vec2_uint64_t args_0) { + return __spirv_ocl_nan(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_nan(__clc_vec3_uint64_t args_0) { + return __spirv_ocl_nan(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_nan(__clc_vec4_uint64_t args_0) { + return __spirv_ocl_nan(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_nan(__clc_vec8_uint64_t args_0) { + return __spirv_ocl_nan(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_nan(__clc_vec16_uint64_t args_0) { + return __spirv_ocl_nan(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/native_cos.cl b/libclc/test/binding/ocl/native_cos.cl new file mode 100644 index 0000000000000..b8dc4b427d082 --- /dev/null +++ b/libclc/test/binding/ocl/native_cos.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_native_cos(__clc_fp32_t args_0) { + return __spirv_ocl_native_cos(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_native_cos(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_native_cos(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_native_cos(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_native_cos(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_native_cos(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_native_cos(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_native_cos(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_native_cos(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_native_cos(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_native_cos(args_0); +} diff --git a/libclc/test/binding/ocl/native_divide.cl b/libclc/test/binding/ocl/native_divide.cl new file mode 100644 index 0000000000000..1add972930763 --- /dev/null +++ b/libclc/test/binding/ocl/native_divide.cl @@ -0,0 +1,51 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_native_divide(__clc_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_ocl_native_divide(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_native_divide(__clc_vec2_fp32_t args_0, + __clc_vec2_fp32_t args_1) { + return __spirv_ocl_native_divide(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_native_divide(__clc_vec3_fp32_t args_0, + __clc_vec3_fp32_t args_1) { + return __spirv_ocl_native_divide(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_native_divide(__clc_vec4_fp32_t args_0, + __clc_vec4_fp32_t args_1) { + return __spirv_ocl_native_divide(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_native_divide(__clc_vec8_fp32_t args_0, + __clc_vec8_fp32_t args_1) { + return __spirv_ocl_native_divide(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_native_divide(__clc_vec16_fp32_t args_0, + __clc_vec16_fp32_t args_1) { + return __spirv_ocl_native_divide(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/native_exp.cl b/libclc/test/binding/ocl/native_exp.cl new file mode 100644 index 0000000000000..efce8ffc8a654 --- /dev/null +++ b/libclc/test/binding/ocl/native_exp.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_native_exp(__clc_fp32_t args_0) { + return __spirv_ocl_native_exp(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_native_exp(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_native_exp(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_native_exp(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_native_exp(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_native_exp(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_native_exp(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_native_exp(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_native_exp(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_native_exp(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_native_exp(args_0); +} diff --git a/libclc/test/binding/ocl/native_exp10.cl b/libclc/test/binding/ocl/native_exp10.cl new file mode 100644 index 0000000000000..3befa2cbe6346 --- /dev/null +++ b/libclc/test/binding/ocl/native_exp10.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_native_exp10(__clc_fp32_t args_0) { + return __spirv_ocl_native_exp10(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_native_exp10(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_native_exp10(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_native_exp10(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_native_exp10(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_native_exp10(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_native_exp10(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_native_exp10(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_native_exp10(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_native_exp10(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_native_exp10(args_0); +} diff --git a/libclc/test/binding/ocl/native_exp2.cl b/libclc/test/binding/ocl/native_exp2.cl new file mode 100644 index 0000000000000..00b58282d8106 --- /dev/null +++ b/libclc/test/binding/ocl/native_exp2.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_native_exp2(__clc_fp32_t args_0) { + return __spirv_ocl_native_exp2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_native_exp2(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_native_exp2(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_native_exp2(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_native_exp2(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_native_exp2(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_native_exp2(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_native_exp2(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_native_exp2(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_native_exp2(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_native_exp2(args_0); +} diff --git a/libclc/test/binding/ocl/native_log.cl b/libclc/test/binding/ocl/native_log.cl new file mode 100644 index 0000000000000..9ae0d8a11171f --- /dev/null +++ b/libclc/test/binding/ocl/native_log.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_native_log(__clc_fp32_t args_0) { + return __spirv_ocl_native_log(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_native_log(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_native_log(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_native_log(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_native_log(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_native_log(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_native_log(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_native_log(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_native_log(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_native_log(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_native_log(args_0); +} diff --git a/libclc/test/binding/ocl/native_log10.cl b/libclc/test/binding/ocl/native_log10.cl new file mode 100644 index 0000000000000..fb855843d91af --- /dev/null +++ b/libclc/test/binding/ocl/native_log10.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_native_log10(__clc_fp32_t args_0) { + return __spirv_ocl_native_log10(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_native_log10(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_native_log10(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_native_log10(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_native_log10(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_native_log10(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_native_log10(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_native_log10(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_native_log10(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_native_log10(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_native_log10(args_0); +} diff --git a/libclc/test/binding/ocl/native_log2.cl b/libclc/test/binding/ocl/native_log2.cl new file mode 100644 index 0000000000000..b10bf05101229 --- /dev/null +++ b/libclc/test/binding/ocl/native_log2.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_native_log2(__clc_fp32_t args_0) { + return __spirv_ocl_native_log2(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_native_log2(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_native_log2(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_native_log2(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_native_log2(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_native_log2(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_native_log2(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_native_log2(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_native_log2(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_native_log2(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_native_log2(args_0); +} diff --git a/libclc/test/binding/ocl/native_powr.cl b/libclc/test/binding/ocl/native_powr.cl new file mode 100644 index 0000000000000..5c76af37876e8 --- /dev/null +++ b/libclc/test/binding/ocl/native_powr.cl @@ -0,0 +1,51 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_native_powr(__clc_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_ocl_native_powr(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_native_powr(__clc_vec2_fp32_t args_0, + __clc_vec2_fp32_t args_1) { + return __spirv_ocl_native_powr(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_native_powr(__clc_vec3_fp32_t args_0, + __clc_vec3_fp32_t args_1) { + return __spirv_ocl_native_powr(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_native_powr(__clc_vec4_fp32_t args_0, + __clc_vec4_fp32_t args_1) { + return __spirv_ocl_native_powr(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_native_powr(__clc_vec8_fp32_t args_0, + __clc_vec8_fp32_t args_1) { + return __spirv_ocl_native_powr(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_native_powr(__clc_vec16_fp32_t args_0, + __clc_vec16_fp32_t args_1) { + return __spirv_ocl_native_powr(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/native_recip.cl b/libclc/test/binding/ocl/native_recip.cl new file mode 100644 index 0000000000000..f5e505e0bb6e5 --- /dev/null +++ b/libclc/test/binding/ocl/native_recip.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_native_recip(__clc_fp32_t args_0) { + return __spirv_ocl_native_recip(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_native_recip(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_native_recip(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_native_recip(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_native_recip(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_native_recip(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_native_recip(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_native_recip(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_native_recip(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_native_recip(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_native_recip(args_0); +} diff --git a/libclc/test/binding/ocl/native_sin.cl b/libclc/test/binding/ocl/native_sin.cl new file mode 100644 index 0000000000000..047cca254822d --- /dev/null +++ b/libclc/test/binding/ocl/native_sin.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_native_sin(__clc_fp32_t args_0) { + return __spirv_ocl_native_sin(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_native_sin(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_native_sin(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_native_sin(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_native_sin(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_native_sin(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_native_sin(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_native_sin(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_native_sin(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_native_sin(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_native_sin(args_0); +} diff --git a/libclc/test/binding/ocl/native_tan.cl b/libclc/test/binding/ocl/native_tan.cl new file mode 100644 index 0000000000000..48fb75e3fef16 --- /dev/null +++ b/libclc/test/binding/ocl/native_tan.cl @@ -0,0 +1,46 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_native_tan(__clc_fp32_t args_0) { + return __spirv_ocl_native_tan(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_native_tan(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_native_tan(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_native_tan(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_native_tan(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_native_tan(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_native_tan(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_native_tan(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_native_tan(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_native_tan(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_native_tan(args_0); +} diff --git a/libclc/test/binding/ocl/nextafter.cl b/libclc/test/binding/ocl/nextafter.cl new file mode 100644 index 0000000000000..ce82e1b6bd77f --- /dev/null +++ b/libclc/test/binding/ocl/nextafter.cl @@ -0,0 +1,134 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_nextafter(__clc_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_ocl_nextafter(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_nextafter(__clc_vec2_fp32_t args_0, __clc_vec2_fp32_t args_1) { + return __spirv_ocl_nextafter(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_nextafter(__clc_vec3_fp32_t args_0, __clc_vec3_fp32_t args_1) { + return __spirv_ocl_nextafter(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_nextafter(__clc_vec4_fp32_t args_0, __clc_vec4_fp32_t args_1) { + return __spirv_ocl_nextafter(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_nextafter(__clc_vec8_fp32_t args_0, __clc_vec8_fp32_t args_1) { + return __spirv_ocl_nextafter(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_nextafter(__clc_vec16_fp32_t args_0, + __clc_vec16_fp32_t args_1) { + return __spirv_ocl_nextafter(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_nextafter(__clc_fp64_t args_0, __clc_fp64_t args_1) { + return __spirv_ocl_nextafter(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_nextafter(__clc_vec2_fp64_t args_0, __clc_vec2_fp64_t args_1) { + return __spirv_ocl_nextafter(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_nextafter(__clc_vec3_fp64_t args_0, __clc_vec3_fp64_t args_1) { + return __spirv_ocl_nextafter(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_nextafter(__clc_vec4_fp64_t args_0, __clc_vec4_fp64_t args_1) { + return __spirv_ocl_nextafter(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_nextafter(__clc_vec8_fp64_t args_0, __clc_vec8_fp64_t args_1) { + return __spirv_ocl_nextafter(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_nextafter(__clc_vec16_fp64_t args_0, + __clc_vec16_fp64_t args_1) { + return __spirv_ocl_nextafter(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_nextafter(__clc_fp16_t args_0, __clc_fp16_t args_1) { + return __spirv_ocl_nextafter(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_nextafter(__clc_vec2_fp16_t args_0, __clc_vec2_fp16_t args_1) { + return __spirv_ocl_nextafter(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_nextafter(__clc_vec3_fp16_t args_0, __clc_vec3_fp16_t args_1) { + return __spirv_ocl_nextafter(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_nextafter(__clc_vec4_fp16_t args_0, __clc_vec4_fp16_t args_1) { + return __spirv_ocl_nextafter(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_nextafter(__clc_vec8_fp16_t args_0, __clc_vec8_fp16_t args_1) { + return __spirv_ocl_nextafter(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_nextafter(__clc_vec16_fp16_t args_0, + __clc_vec16_fp16_t args_1) { + return __spirv_ocl_nextafter(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/pow.cl b/libclc/test/binding/ocl/pow.cl new file mode 100644 index 0000000000000..63328bb8d4b63 --- /dev/null +++ b/libclc/test/binding/ocl/pow.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_pow(__clc_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_ocl_pow(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_pow(__clc_vec2_fp32_t args_0, __clc_vec2_fp32_t args_1) { + return __spirv_ocl_pow(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_pow(__clc_vec3_fp32_t args_0, __clc_vec3_fp32_t args_1) { + return __spirv_ocl_pow(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_pow(__clc_vec4_fp32_t args_0, __clc_vec4_fp32_t args_1) { + return __spirv_ocl_pow(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_pow(__clc_vec8_fp32_t args_0, __clc_vec8_fp32_t args_1) { + return __spirv_ocl_pow(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_pow(__clc_vec16_fp32_t args_0, __clc_vec16_fp32_t args_1) { + return __spirv_ocl_pow(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_pow(__clc_fp64_t args_0, __clc_fp64_t args_1) { + return __spirv_ocl_pow(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_pow(__clc_vec2_fp64_t args_0, __clc_vec2_fp64_t args_1) { + return __spirv_ocl_pow(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_pow(__clc_vec3_fp64_t args_0, __clc_vec3_fp64_t args_1) { + return __spirv_ocl_pow(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_pow(__clc_vec4_fp64_t args_0, __clc_vec4_fp64_t args_1) { + return __spirv_ocl_pow(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_pow(__clc_vec8_fp64_t args_0, __clc_vec8_fp64_t args_1) { + return __spirv_ocl_pow(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_pow(__clc_vec16_fp64_t args_0, __clc_vec16_fp64_t args_1) { + return __spirv_ocl_pow(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_pow(__clc_fp16_t args_0, __clc_fp16_t args_1) { + return __spirv_ocl_pow(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_pow(__clc_vec2_fp16_t args_0, __clc_vec2_fp16_t args_1) { + return __spirv_ocl_pow(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_pow(__clc_vec3_fp16_t args_0, __clc_vec3_fp16_t args_1) { + return __spirv_ocl_pow(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_pow(__clc_vec4_fp16_t args_0, __clc_vec4_fp16_t args_1) { + return __spirv_ocl_pow(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_pow(__clc_vec8_fp16_t args_0, __clc_vec8_fp16_t args_1) { + return __spirv_ocl_pow(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_pow(__clc_vec16_fp16_t args_0, __clc_vec16_fp16_t args_1) { + return __spirv_ocl_pow(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/pown.cl b/libclc/test/binding/ocl/pown.cl new file mode 100644 index 0000000000000..21881bdf3772d --- /dev/null +++ b/libclc/test/binding/ocl/pown.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_pown(__clc_fp32_t args_0, __clc_int32_t args_1) { + return __spirv_ocl_pown(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_pown(__clc_vec2_fp32_t args_0, __clc_vec2_int32_t args_1) { + return __spirv_ocl_pown(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_pown(__clc_vec3_fp32_t args_0, __clc_vec3_int32_t args_1) { + return __spirv_ocl_pown(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_pown(__clc_vec4_fp32_t args_0, __clc_vec4_int32_t args_1) { + return __spirv_ocl_pown(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_pown(__clc_vec8_fp32_t args_0, __clc_vec8_int32_t args_1) { + return __spirv_ocl_pown(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_pown(__clc_vec16_fp32_t args_0, __clc_vec16_int32_t args_1) { + return __spirv_ocl_pown(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_pown(__clc_fp64_t args_0, __clc_int32_t args_1) { + return __spirv_ocl_pown(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_pown(__clc_vec2_fp64_t args_0, __clc_vec2_int32_t args_1) { + return __spirv_ocl_pown(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_pown(__clc_vec3_fp64_t args_0, __clc_vec3_int32_t args_1) { + return __spirv_ocl_pown(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_pown(__clc_vec4_fp64_t args_0, __clc_vec4_int32_t args_1) { + return __spirv_ocl_pown(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_pown(__clc_vec8_fp64_t args_0, __clc_vec8_int32_t args_1) { + return __spirv_ocl_pown(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_pown(__clc_vec16_fp64_t args_0, __clc_vec16_int32_t args_1) { + return __spirv_ocl_pown(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_pown(__clc_fp16_t args_0, __clc_int32_t args_1) { + return __spirv_ocl_pown(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_pown(__clc_vec2_fp16_t args_0, __clc_vec2_int32_t args_1) { + return __spirv_ocl_pown(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_pown(__clc_vec3_fp16_t args_0, __clc_vec3_int32_t args_1) { + return __spirv_ocl_pown(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_pown(__clc_vec4_fp16_t args_0, __clc_vec4_int32_t args_1) { + return __spirv_ocl_pown(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_pown(__clc_vec8_fp16_t args_0, __clc_vec8_int32_t args_1) { + return __spirv_ocl_pown(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_pown(__clc_vec16_fp16_t args_0, __clc_vec16_int32_t args_1) { + return __spirv_ocl_pown(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/powr.cl b/libclc/test/binding/ocl/powr.cl new file mode 100644 index 0000000000000..6a685f1d69879 --- /dev/null +++ b/libclc/test/binding/ocl/powr.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_powr(__clc_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_ocl_powr(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_powr(__clc_vec2_fp32_t args_0, __clc_vec2_fp32_t args_1) { + return __spirv_ocl_powr(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_powr(__clc_vec3_fp32_t args_0, __clc_vec3_fp32_t args_1) { + return __spirv_ocl_powr(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_powr(__clc_vec4_fp32_t args_0, __clc_vec4_fp32_t args_1) { + return __spirv_ocl_powr(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_powr(__clc_vec8_fp32_t args_0, __clc_vec8_fp32_t args_1) { + return __spirv_ocl_powr(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_powr(__clc_vec16_fp32_t args_0, __clc_vec16_fp32_t args_1) { + return __spirv_ocl_powr(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_powr(__clc_fp64_t args_0, __clc_fp64_t args_1) { + return __spirv_ocl_powr(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_powr(__clc_vec2_fp64_t args_0, __clc_vec2_fp64_t args_1) { + return __spirv_ocl_powr(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_powr(__clc_vec3_fp64_t args_0, __clc_vec3_fp64_t args_1) { + return __spirv_ocl_powr(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_powr(__clc_vec4_fp64_t args_0, __clc_vec4_fp64_t args_1) { + return __spirv_ocl_powr(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_powr(__clc_vec8_fp64_t args_0, __clc_vec8_fp64_t args_1) { + return __spirv_ocl_powr(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_powr(__clc_vec16_fp64_t args_0, __clc_vec16_fp64_t args_1) { + return __spirv_ocl_powr(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_powr(__clc_fp16_t args_0, __clc_fp16_t args_1) { + return __spirv_ocl_powr(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_powr(__clc_vec2_fp16_t args_0, __clc_vec2_fp16_t args_1) { + return __spirv_ocl_powr(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_powr(__clc_vec3_fp16_t args_0, __clc_vec3_fp16_t args_1) { + return __spirv_ocl_powr(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_powr(__clc_vec4_fp16_t args_0, __clc_vec4_fp16_t args_1) { + return __spirv_ocl_powr(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_powr(__clc_vec8_fp16_t args_0, __clc_vec8_fp16_t args_1) { + return __spirv_ocl_powr(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_powr(__clc_vec16_fp16_t args_0, __clc_vec16_fp16_t args_1) { + return __spirv_ocl_powr(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/remainder.cl b/libclc/test/binding/ocl/remainder.cl new file mode 100644 index 0000000000000..69e5307a48dde --- /dev/null +++ b/libclc/test/binding/ocl/remainder.cl @@ -0,0 +1,134 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_remainder(__clc_fp32_t args_0, __clc_fp32_t args_1) { + return __spirv_ocl_remainder(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_remainder(__clc_vec2_fp32_t args_0, __clc_vec2_fp32_t args_1) { + return __spirv_ocl_remainder(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_remainder(__clc_vec3_fp32_t args_0, __clc_vec3_fp32_t args_1) { + return __spirv_ocl_remainder(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_remainder(__clc_vec4_fp32_t args_0, __clc_vec4_fp32_t args_1) { + return __spirv_ocl_remainder(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_remainder(__clc_vec8_fp32_t args_0, __clc_vec8_fp32_t args_1) { + return __spirv_ocl_remainder(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_remainder(__clc_vec16_fp32_t args_0, + __clc_vec16_fp32_t args_1) { + return __spirv_ocl_remainder(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_remainder(__clc_fp64_t args_0, __clc_fp64_t args_1) { + return __spirv_ocl_remainder(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_remainder(__clc_vec2_fp64_t args_0, __clc_vec2_fp64_t args_1) { + return __spirv_ocl_remainder(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_remainder(__clc_vec3_fp64_t args_0, __clc_vec3_fp64_t args_1) { + return __spirv_ocl_remainder(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_remainder(__clc_vec4_fp64_t args_0, __clc_vec4_fp64_t args_1) { + return __spirv_ocl_remainder(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_remainder(__clc_vec8_fp64_t args_0, __clc_vec8_fp64_t args_1) { + return __spirv_ocl_remainder(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_remainder(__clc_vec16_fp64_t args_0, + __clc_vec16_fp64_t args_1) { + return __spirv_ocl_remainder(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_remainder(__clc_fp16_t args_0, __clc_fp16_t args_1) { + return __spirv_ocl_remainder(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_remainder(__clc_vec2_fp16_t args_0, __clc_vec2_fp16_t args_1) { + return __spirv_ocl_remainder(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_remainder(__clc_vec3_fp16_t args_0, __clc_vec3_fp16_t args_1) { + return __spirv_ocl_remainder(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_remainder(__clc_vec4_fp16_t args_0, __clc_vec4_fp16_t args_1) { + return __spirv_ocl_remainder(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_remainder(__clc_vec8_fp16_t args_0, __clc_vec8_fp16_t args_1) { + return __spirv_ocl_remainder(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_remainder(__clc_vec16_fp16_t args_0, + __clc_vec16_fp16_t args_1) { + return __spirv_ocl_remainder(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/remquo.cl b/libclc/test/binding/ocl/remquo.cl new file mode 100644 index 0000000000000..eb14d1d2beabb --- /dev/null +++ b/libclc/test/binding/ocl/remquo.cl @@ -0,0 +1,413 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_remquo(__clc_fp32_t args_0, __clc_fp32_t args_1, + __clc_int32_t __global *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_remquo(__clc_vec2_fp32_t args_0, __clc_vec2_fp32_t args_1, + __clc_vec2_int32_t __global *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_remquo(__clc_vec3_fp32_t args_0, __clc_vec3_fp32_t args_1, + __clc_vec3_int32_t __global *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_remquo(__clc_vec4_fp32_t args_0, __clc_vec4_fp32_t args_1, + __clc_vec4_int32_t __global *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_remquo(__clc_vec8_fp32_t args_0, __clc_vec8_fp32_t args_1, + __clc_vec8_int32_t __global *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_remquo(__clc_vec16_fp32_t args_0, __clc_vec16_fp32_t args_1, + __clc_vec16_int32_t __global *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_remquo(__clc_fp64_t args_0, __clc_fp64_t args_1, + __clc_int32_t __global *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_remquo(__clc_vec2_fp64_t args_0, __clc_vec2_fp64_t args_1, + __clc_vec2_int32_t __global *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_remquo(__clc_vec3_fp64_t args_0, __clc_vec3_fp64_t args_1, + __clc_vec3_int32_t __global *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_remquo(__clc_vec4_fp64_t args_0, __clc_vec4_fp64_t args_1, + __clc_vec4_int32_t __global *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_remquo(__clc_vec8_fp64_t args_0, __clc_vec8_fp64_t args_1, + __clc_vec8_int32_t __global *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_remquo(__clc_vec16_fp64_t args_0, __clc_vec16_fp64_t args_1, + __clc_vec16_int32_t __global *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_remquo(__clc_fp16_t args_0, __clc_fp16_t args_1, + __clc_int32_t __global *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_remquo(__clc_vec2_fp16_t args_0, __clc_vec2_fp16_t args_1, + __clc_vec2_int32_t __global *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_remquo(__clc_vec3_fp16_t args_0, __clc_vec3_fp16_t args_1, + __clc_vec3_int32_t __global *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_remquo(__clc_vec4_fp16_t args_0, __clc_vec4_fp16_t args_1, + __clc_vec4_int32_t __global *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_remquo(__clc_vec8_fp16_t args_0, __clc_vec8_fp16_t args_1, + __clc_vec8_int32_t __global *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_remquo(__clc_vec16_fp16_t args_0, __clc_vec16_fp16_t args_1, + __clc_vec16_int32_t __global *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#endif +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_remquo(__clc_fp32_t args_0, __clc_fp32_t args_1, + __clc_int32_t __local *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_remquo(__clc_vec2_fp32_t args_0, __clc_vec2_fp32_t args_1, + __clc_vec2_int32_t __local *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_remquo(__clc_vec3_fp32_t args_0, __clc_vec3_fp32_t args_1, + __clc_vec3_int32_t __local *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_remquo(__clc_vec4_fp32_t args_0, __clc_vec4_fp32_t args_1, + __clc_vec4_int32_t __local *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_remquo(__clc_vec8_fp32_t args_0, __clc_vec8_fp32_t args_1, + __clc_vec8_int32_t __local *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_remquo(__clc_vec16_fp32_t args_0, __clc_vec16_fp32_t args_1, + __clc_vec16_int32_t __local *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_remquo(__clc_fp64_t args_0, __clc_fp64_t args_1, + __clc_int32_t __local *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_remquo(__clc_vec2_fp64_t args_0, __clc_vec2_fp64_t args_1, + __clc_vec2_int32_t __local *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_remquo(__clc_vec3_fp64_t args_0, __clc_vec3_fp64_t args_1, + __clc_vec3_int32_t __local *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_remquo(__clc_vec4_fp64_t args_0, __clc_vec4_fp64_t args_1, + __clc_vec4_int32_t __local *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_remquo(__clc_vec8_fp64_t args_0, __clc_vec8_fp64_t args_1, + __clc_vec8_int32_t __local *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_remquo(__clc_vec16_fp64_t args_0, __clc_vec16_fp64_t args_1, + __clc_vec16_int32_t __local *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_remquo(__clc_fp16_t args_0, __clc_fp16_t args_1, + __clc_int32_t __local *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_remquo(__clc_vec2_fp16_t args_0, __clc_vec2_fp16_t args_1, + __clc_vec2_int32_t __local *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_remquo(__clc_vec3_fp16_t args_0, __clc_vec3_fp16_t args_1, + __clc_vec3_int32_t __local *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_remquo(__clc_vec4_fp16_t args_0, __clc_vec4_fp16_t args_1, + __clc_vec4_int32_t __local *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_remquo(__clc_vec8_fp16_t args_0, __clc_vec8_fp16_t args_1, + __clc_vec8_int32_t __local *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_remquo(__clc_vec16_fp16_t args_0, __clc_vec16_fp16_t args_1, + __clc_vec16_int32_t __local *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#endif +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_remquo(__clc_fp32_t args_0, __clc_fp32_t args_1, + __clc_int32_t *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_remquo(__clc_vec2_fp32_t args_0, __clc_vec2_fp32_t args_1, + __clc_vec2_int32_t *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_remquo(__clc_vec3_fp32_t args_0, __clc_vec3_fp32_t args_1, + __clc_vec3_int32_t *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_remquo(__clc_vec4_fp32_t args_0, __clc_vec4_fp32_t args_1, + __clc_vec4_int32_t *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_remquo(__clc_vec8_fp32_t args_0, __clc_vec8_fp32_t args_1, + __clc_vec8_int32_t *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_remquo(__clc_vec16_fp32_t args_0, __clc_vec16_fp32_t args_1, + __clc_vec16_int32_t *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_remquo(__clc_fp64_t args_0, __clc_fp64_t args_1, + __clc_int32_t *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_remquo(__clc_vec2_fp64_t args_0, __clc_vec2_fp64_t args_1, + __clc_vec2_int32_t *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_remquo(__clc_vec3_fp64_t args_0, __clc_vec3_fp64_t args_1, + __clc_vec3_int32_t *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_remquo(__clc_vec4_fp64_t args_0, __clc_vec4_fp64_t args_1, + __clc_vec4_int32_t *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_remquo(__clc_vec8_fp64_t args_0, __clc_vec8_fp64_t args_1, + __clc_vec8_int32_t *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_remquo(__clc_vec16_fp64_t args_0, __clc_vec16_fp64_t args_1, + __clc_vec16_int32_t *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_remquo(__clc_fp16_t args_0, __clc_fp16_t args_1, + __clc_int32_t *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_remquo(__clc_vec2_fp16_t args_0, __clc_vec2_fp16_t args_1, + __clc_vec2_int32_t *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_remquo(__clc_vec3_fp16_t args_0, __clc_vec3_fp16_t args_1, + __clc_vec3_int32_t *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_remquo(__clc_vec4_fp16_t args_0, __clc_vec4_fp16_t args_1, + __clc_vec4_int32_t *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_remquo(__clc_vec8_fp16_t args_0, __clc_vec8_fp16_t args_1, + __clc_vec8_int32_t *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_remquo(__clc_vec16_fp16_t args_0, __clc_vec16_fp16_t args_1, + __clc_vec16_int32_t *args_2) { + return __spirv_ocl_remquo(args_0, args_1, args_2); +} + +#endif diff --git a/libclc/test/binding/ocl/rint.cl b/libclc/test/binding/ocl/rint.cl new file mode 100644 index 0000000000000..8bea89e5d0dd2 --- /dev/null +++ b/libclc/test/binding/ocl/rint.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_rint(__clc_fp32_t args_0) { + return __spirv_ocl_rint(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_rint(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_rint(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_rint(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_rint(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_rint(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_rint(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_rint(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_rint(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_rint(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_rint(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_rint(__clc_fp64_t args_0) { + return __spirv_ocl_rint(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_rint(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_rint(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_rint(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_rint(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_rint(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_rint(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_rint(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_rint(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_rint(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_rint(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_rint(__clc_fp16_t args_0) { + return __spirv_ocl_rint(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_rint(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_rint(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_rint(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_rint(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_rint(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_rint(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_rint(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_rint(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_rint(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_rint(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/rootn.cl b/libclc/test/binding/ocl/rootn.cl new file mode 100644 index 0000000000000..450e07735d1ad --- /dev/null +++ b/libclc/test/binding/ocl/rootn.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_rootn(__clc_fp32_t args_0, __clc_int32_t args_1) { + return __spirv_ocl_rootn(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_rootn(__clc_vec2_fp32_t args_0, __clc_vec2_int32_t args_1) { + return __spirv_ocl_rootn(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_rootn(__clc_vec3_fp32_t args_0, __clc_vec3_int32_t args_1) { + return __spirv_ocl_rootn(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_rootn(__clc_vec4_fp32_t args_0, __clc_vec4_int32_t args_1) { + return __spirv_ocl_rootn(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_rootn(__clc_vec8_fp32_t args_0, __clc_vec8_int32_t args_1) { + return __spirv_ocl_rootn(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_rootn(__clc_vec16_fp32_t args_0, __clc_vec16_int32_t args_1) { + return __spirv_ocl_rootn(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_rootn(__clc_fp64_t args_0, __clc_int32_t args_1) { + return __spirv_ocl_rootn(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_rootn(__clc_vec2_fp64_t args_0, __clc_vec2_int32_t args_1) { + return __spirv_ocl_rootn(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_rootn(__clc_vec3_fp64_t args_0, __clc_vec3_int32_t args_1) { + return __spirv_ocl_rootn(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_rootn(__clc_vec4_fp64_t args_0, __clc_vec4_int32_t args_1) { + return __spirv_ocl_rootn(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_rootn(__clc_vec8_fp64_t args_0, __clc_vec8_int32_t args_1) { + return __spirv_ocl_rootn(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_rootn(__clc_vec16_fp64_t args_0, __clc_vec16_int32_t args_1) { + return __spirv_ocl_rootn(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_rootn(__clc_fp16_t args_0, __clc_int32_t args_1) { + return __spirv_ocl_rootn(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_rootn(__clc_vec2_fp16_t args_0, __clc_vec2_int32_t args_1) { + return __spirv_ocl_rootn(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_rootn(__clc_vec3_fp16_t args_0, __clc_vec3_int32_t args_1) { + return __spirv_ocl_rootn(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_rootn(__clc_vec4_fp16_t args_0, __clc_vec4_int32_t args_1) { + return __spirv_ocl_rootn(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_rootn(__clc_vec8_fp16_t args_0, __clc_vec8_int32_t args_1) { + return __spirv_ocl_rootn(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_rootn(__clc_vec16_fp16_t args_0, __clc_vec16_int32_t args_1) { + return __spirv_ocl_rootn(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/round.cl b/libclc/test/binding/ocl/round.cl new file mode 100644 index 0000000000000..008444948adaa --- /dev/null +++ b/libclc/test/binding/ocl/round.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_round(__clc_fp32_t args_0) { + return __spirv_ocl_round(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_round(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_round(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_round(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_round(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_round(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_round(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_round(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_round(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_round(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_round(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_round(__clc_fp64_t args_0) { + return __spirv_ocl_round(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_round(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_round(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_round(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_round(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_round(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_round(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_round(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_round(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_round(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_round(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_round(__clc_fp16_t args_0) { + return __spirv_ocl_round(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_round(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_round(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_round(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_round(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_round(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_round(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_round(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_round(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_round(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_round(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/s_clamp.cl b/libclc/test/binding/ocl/s_clamp.cl new file mode 100644 index 0000000000000..e1a0123bb6bb3 --- /dev/null +++ b/libclc/test/binding/ocl/s_clamp.cl @@ -0,0 +1,160 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int8_t +test___spirv_ocl_s_clamp(__clc_int8_t args_0, __clc_int8_t args_1, + __clc_int8_t args_2) { + return __spirv_ocl_s_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ocl_s_clamp(__clc_vec2_int8_t args_0, __clc_vec2_int8_t args_1, + __clc_vec2_int8_t args_2) { + return __spirv_ocl_s_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ocl_s_clamp(__clc_vec3_int8_t args_0, __clc_vec3_int8_t args_1, + __clc_vec3_int8_t args_2) { + return __spirv_ocl_s_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ocl_s_clamp(__clc_vec4_int8_t args_0, __clc_vec4_int8_t args_1, + __clc_vec4_int8_t args_2) { + return __spirv_ocl_s_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ocl_s_clamp(__clc_vec8_int8_t args_0, __clc_vec8_int8_t args_1, + __clc_vec8_int8_t args_2) { + return __spirv_ocl_s_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ocl_s_clamp(__clc_vec16_int8_t args_0, __clc_vec16_int8_t args_1, + __clc_vec16_int8_t args_2) { + return __spirv_ocl_s_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_int16_t +test___spirv_ocl_s_clamp(__clc_int16_t args_0, __clc_int16_t args_1, + __clc_int16_t args_2) { + return __spirv_ocl_s_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ocl_s_clamp(__clc_vec2_int16_t args_0, __clc_vec2_int16_t args_1, + __clc_vec2_int16_t args_2) { + return __spirv_ocl_s_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ocl_s_clamp(__clc_vec3_int16_t args_0, __clc_vec3_int16_t args_1, + __clc_vec3_int16_t args_2) { + return __spirv_ocl_s_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ocl_s_clamp(__clc_vec4_int16_t args_0, __clc_vec4_int16_t args_1, + __clc_vec4_int16_t args_2) { + return __spirv_ocl_s_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ocl_s_clamp(__clc_vec8_int16_t args_0, __clc_vec8_int16_t args_1, + __clc_vec8_int16_t args_2) { + return __spirv_ocl_s_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ocl_s_clamp(__clc_vec16_int16_t args_0, __clc_vec16_int16_t args_1, + __clc_vec16_int16_t args_2) { + return __spirv_ocl_s_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_int32_t +test___spirv_ocl_s_clamp(__clc_int32_t args_0, __clc_int32_t args_1, + __clc_int32_t args_2) { + return __spirv_ocl_s_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ocl_s_clamp(__clc_vec2_int32_t args_0, __clc_vec2_int32_t args_1, + __clc_vec2_int32_t args_2) { + return __spirv_ocl_s_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ocl_s_clamp(__clc_vec3_int32_t args_0, __clc_vec3_int32_t args_1, + __clc_vec3_int32_t args_2) { + return __spirv_ocl_s_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ocl_s_clamp(__clc_vec4_int32_t args_0, __clc_vec4_int32_t args_1, + __clc_vec4_int32_t args_2) { + return __spirv_ocl_s_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ocl_s_clamp(__clc_vec8_int32_t args_0, __clc_vec8_int32_t args_1, + __clc_vec8_int32_t args_2) { + return __spirv_ocl_s_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ocl_s_clamp(__clc_vec16_int32_t args_0, __clc_vec16_int32_t args_1, + __clc_vec16_int32_t args_2) { + return __spirv_ocl_s_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_int64_t +test___spirv_ocl_s_clamp(__clc_int64_t args_0, __clc_int64_t args_1, + __clc_int64_t args_2) { + return __spirv_ocl_s_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ocl_s_clamp(__clc_vec2_int64_t args_0, __clc_vec2_int64_t args_1, + __clc_vec2_int64_t args_2) { + return __spirv_ocl_s_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ocl_s_clamp(__clc_vec3_int64_t args_0, __clc_vec3_int64_t args_1, + __clc_vec3_int64_t args_2) { + return __spirv_ocl_s_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ocl_s_clamp(__clc_vec4_int64_t args_0, __clc_vec4_int64_t args_1, + __clc_vec4_int64_t args_2) { + return __spirv_ocl_s_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ocl_s_clamp(__clc_vec8_int64_t args_0, __clc_vec8_int64_t args_1, + __clc_vec8_int64_t args_2) { + return __spirv_ocl_s_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ocl_s_clamp(__clc_vec16_int64_t args_0, __clc_vec16_int64_t args_1, + __clc_vec16_int64_t args_2) { + return __spirv_ocl_s_clamp(args_0, args_1, args_2); +} diff --git a/libclc/test/binding/ocl/s_max.cl b/libclc/test/binding/ocl/s_max.cl new file mode 100644 index 0000000000000..7dea096eb1653 --- /dev/null +++ b/libclc/test/binding/ocl/s_max.cl @@ -0,0 +1,136 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int8_t +test___spirv_ocl_s_max(__clc_int8_t args_0, __clc_int8_t args_1) { + return __spirv_ocl_s_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ocl_s_max(__clc_vec2_int8_t args_0, __clc_vec2_int8_t args_1) { + return __spirv_ocl_s_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ocl_s_max(__clc_vec3_int8_t args_0, __clc_vec3_int8_t args_1) { + return __spirv_ocl_s_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ocl_s_max(__clc_vec4_int8_t args_0, __clc_vec4_int8_t args_1) { + return __spirv_ocl_s_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ocl_s_max(__clc_vec8_int8_t args_0, __clc_vec8_int8_t args_1) { + return __spirv_ocl_s_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ocl_s_max(__clc_vec16_int8_t args_0, __clc_vec16_int8_t args_1) { + return __spirv_ocl_s_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_int16_t +test___spirv_ocl_s_max(__clc_int16_t args_0, __clc_int16_t args_1) { + return __spirv_ocl_s_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ocl_s_max(__clc_vec2_int16_t args_0, __clc_vec2_int16_t args_1) { + return __spirv_ocl_s_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ocl_s_max(__clc_vec3_int16_t args_0, __clc_vec3_int16_t args_1) { + return __spirv_ocl_s_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ocl_s_max(__clc_vec4_int16_t args_0, __clc_vec4_int16_t args_1) { + return __spirv_ocl_s_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ocl_s_max(__clc_vec8_int16_t args_0, __clc_vec8_int16_t args_1) { + return __spirv_ocl_s_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ocl_s_max(__clc_vec16_int16_t args_0, __clc_vec16_int16_t args_1) { + return __spirv_ocl_s_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_int32_t +test___spirv_ocl_s_max(__clc_int32_t args_0, __clc_int32_t args_1) { + return __spirv_ocl_s_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ocl_s_max(__clc_vec2_int32_t args_0, __clc_vec2_int32_t args_1) { + return __spirv_ocl_s_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ocl_s_max(__clc_vec3_int32_t args_0, __clc_vec3_int32_t args_1) { + return __spirv_ocl_s_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ocl_s_max(__clc_vec4_int32_t args_0, __clc_vec4_int32_t args_1) { + return __spirv_ocl_s_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ocl_s_max(__clc_vec8_int32_t args_0, __clc_vec8_int32_t args_1) { + return __spirv_ocl_s_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ocl_s_max(__clc_vec16_int32_t args_0, __clc_vec16_int32_t args_1) { + return __spirv_ocl_s_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_int64_t +test___spirv_ocl_s_max(__clc_int64_t args_0, __clc_int64_t args_1) { + return __spirv_ocl_s_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ocl_s_max(__clc_vec2_int64_t args_0, __clc_vec2_int64_t args_1) { + return __spirv_ocl_s_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ocl_s_max(__clc_vec3_int64_t args_0, __clc_vec3_int64_t args_1) { + return __spirv_ocl_s_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ocl_s_max(__clc_vec4_int64_t args_0, __clc_vec4_int64_t args_1) { + return __spirv_ocl_s_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ocl_s_max(__clc_vec8_int64_t args_0, __clc_vec8_int64_t args_1) { + return __spirv_ocl_s_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ocl_s_max(__clc_vec16_int64_t args_0, __clc_vec16_int64_t args_1) { + return __spirv_ocl_s_max(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/s_min.cl b/libclc/test/binding/ocl/s_min.cl new file mode 100644 index 0000000000000..35c8f37ca687d --- /dev/null +++ b/libclc/test/binding/ocl/s_min.cl @@ -0,0 +1,136 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_int8_t +test___spirv_ocl_s_min(__clc_int8_t args_0, __clc_int8_t args_1) { + return __spirv_ocl_s_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int8_t +test___spirv_ocl_s_min(__clc_vec2_int8_t args_0, __clc_vec2_int8_t args_1) { + return __spirv_ocl_s_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int8_t +test___spirv_ocl_s_min(__clc_vec3_int8_t args_0, __clc_vec3_int8_t args_1) { + return __spirv_ocl_s_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int8_t +test___spirv_ocl_s_min(__clc_vec4_int8_t args_0, __clc_vec4_int8_t args_1) { + return __spirv_ocl_s_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int8_t +test___spirv_ocl_s_min(__clc_vec8_int8_t args_0, __clc_vec8_int8_t args_1) { + return __spirv_ocl_s_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int8_t +test___spirv_ocl_s_min(__clc_vec16_int8_t args_0, __clc_vec16_int8_t args_1) { + return __spirv_ocl_s_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_int16_t +test___spirv_ocl_s_min(__clc_int16_t args_0, __clc_int16_t args_1) { + return __spirv_ocl_s_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int16_t +test___spirv_ocl_s_min(__clc_vec2_int16_t args_0, __clc_vec2_int16_t args_1) { + return __spirv_ocl_s_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int16_t +test___spirv_ocl_s_min(__clc_vec3_int16_t args_0, __clc_vec3_int16_t args_1) { + return __spirv_ocl_s_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int16_t +test___spirv_ocl_s_min(__clc_vec4_int16_t args_0, __clc_vec4_int16_t args_1) { + return __spirv_ocl_s_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int16_t +test___spirv_ocl_s_min(__clc_vec8_int16_t args_0, __clc_vec8_int16_t args_1) { + return __spirv_ocl_s_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int16_t +test___spirv_ocl_s_min(__clc_vec16_int16_t args_0, __clc_vec16_int16_t args_1) { + return __spirv_ocl_s_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_int32_t +test___spirv_ocl_s_min(__clc_int32_t args_0, __clc_int32_t args_1) { + return __spirv_ocl_s_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int32_t +test___spirv_ocl_s_min(__clc_vec2_int32_t args_0, __clc_vec2_int32_t args_1) { + return __spirv_ocl_s_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int32_t +test___spirv_ocl_s_min(__clc_vec3_int32_t args_0, __clc_vec3_int32_t args_1) { + return __spirv_ocl_s_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int32_t +test___spirv_ocl_s_min(__clc_vec4_int32_t args_0, __clc_vec4_int32_t args_1) { + return __spirv_ocl_s_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int32_t +test___spirv_ocl_s_min(__clc_vec8_int32_t args_0, __clc_vec8_int32_t args_1) { + return __spirv_ocl_s_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int32_t +test___spirv_ocl_s_min(__clc_vec16_int32_t args_0, __clc_vec16_int32_t args_1) { + return __spirv_ocl_s_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_int64_t +test___spirv_ocl_s_min(__clc_int64_t args_0, __clc_int64_t args_1) { + return __spirv_ocl_s_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_int64_t +test___spirv_ocl_s_min(__clc_vec2_int64_t args_0, __clc_vec2_int64_t args_1) { + return __spirv_ocl_s_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_int64_t +test___spirv_ocl_s_min(__clc_vec3_int64_t args_0, __clc_vec3_int64_t args_1) { + return __spirv_ocl_s_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_int64_t +test___spirv_ocl_s_min(__clc_vec4_int64_t args_0, __clc_vec4_int64_t args_1) { + return __spirv_ocl_s_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_int64_t +test___spirv_ocl_s_min(__clc_vec8_int64_t args_0, __clc_vec8_int64_t args_1) { + return __spirv_ocl_s_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_int64_t +test___spirv_ocl_s_min(__clc_vec16_int64_t args_0, __clc_vec16_int64_t args_1) { + return __spirv_ocl_s_min(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/sin.cl b/libclc/test/binding/ocl/sin.cl new file mode 100644 index 0000000000000..a072b5922bb41 --- /dev/null +++ b/libclc/test/binding/ocl/sin.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_sin(__clc_fp32_t args_0) { + return __spirv_ocl_sin(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_sin(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_sin(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_sin(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_sin(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_sin(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_sin(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_sin(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_sin(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_sin(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_sin(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_sin(__clc_fp64_t args_0) { + return __spirv_ocl_sin(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_sin(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_sin(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_sin(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_sin(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_sin(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_sin(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_sin(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_sin(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_sin(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_sin(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_sin(__clc_fp16_t args_0) { + return __spirv_ocl_sin(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_sin(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_sin(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_sin(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_sin(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_sin(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_sin(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_sin(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_sin(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_sin(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_sin(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/sincos.cl b/libclc/test/binding/ocl/sincos.cl new file mode 100644 index 0000000000000..46c0eebe1f5f8 --- /dev/null +++ b/libclc/test/binding/ocl/sincos.cl @@ -0,0 +1,389 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_sincos(__clc_fp32_t args_0, __clc_fp32_t __local *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_sincos(__clc_vec2_fp32_t args_0, + __clc_vec2_fp32_t __local *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_sincos(__clc_vec3_fp32_t args_0, + __clc_vec3_fp32_t __local *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_sincos(__clc_vec4_fp32_t args_0, + __clc_vec4_fp32_t __local *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_sincos(__clc_vec8_fp32_t args_0, + __clc_vec8_fp32_t __local *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_sincos(__clc_vec16_fp32_t args_0, + __clc_vec16_fp32_t __local *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_sincos(__clc_fp64_t args_0, __clc_fp64_t __local *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_sincos(__clc_vec2_fp64_t args_0, + __clc_vec2_fp64_t __local *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_sincos(__clc_vec3_fp64_t args_0, + __clc_vec3_fp64_t __local *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_sincos(__clc_vec4_fp64_t args_0, + __clc_vec4_fp64_t __local *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_sincos(__clc_vec8_fp64_t args_0, + __clc_vec8_fp64_t __local *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_sincos(__clc_vec16_fp64_t args_0, + __clc_vec16_fp64_t __local *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_sincos(__clc_fp16_t args_0, __clc_fp16_t __local *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_sincos(__clc_vec2_fp16_t args_0, + __clc_vec2_fp16_t __local *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_sincos(__clc_vec3_fp16_t args_0, + __clc_vec3_fp16_t __local *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_sincos(__clc_vec4_fp16_t args_0, + __clc_vec4_fp16_t __local *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_sincos(__clc_vec8_fp16_t args_0, + __clc_vec8_fp16_t __local *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_sincos(__clc_vec16_fp16_t args_0, + __clc_vec16_fp16_t __local *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_sincos(__clc_fp32_t args_0, __clc_fp32_t *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_sincos(__clc_vec2_fp32_t args_0, __clc_vec2_fp32_t *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_sincos(__clc_vec3_fp32_t args_0, __clc_vec3_fp32_t *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_sincos(__clc_vec4_fp32_t args_0, __clc_vec4_fp32_t *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_sincos(__clc_vec8_fp32_t args_0, __clc_vec8_fp32_t *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_sincos(__clc_vec16_fp32_t args_0, __clc_vec16_fp32_t *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_sincos(__clc_fp64_t args_0, __clc_fp64_t *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_sincos(__clc_vec2_fp64_t args_0, __clc_vec2_fp64_t *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_sincos(__clc_vec3_fp64_t args_0, __clc_vec3_fp64_t *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_sincos(__clc_vec4_fp64_t args_0, __clc_vec4_fp64_t *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_sincos(__clc_vec8_fp64_t args_0, __clc_vec8_fp64_t *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_sincos(__clc_vec16_fp64_t args_0, __clc_vec16_fp64_t *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_sincos(__clc_fp16_t args_0, __clc_fp16_t *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_sincos(__clc_vec2_fp16_t args_0, __clc_vec2_fp16_t *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_sincos(__clc_vec3_fp16_t args_0, __clc_vec3_fp16_t *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_sincos(__clc_vec4_fp16_t args_0, __clc_vec4_fp16_t *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_sincos(__clc_vec8_fp16_t args_0, __clc_vec8_fp16_t *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_sincos(__clc_vec16_fp16_t args_0, __clc_vec16_fp16_t *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#endif +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_sincos(__clc_fp32_t args_0, __clc_fp32_t __global *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_sincos(__clc_vec2_fp32_t args_0, + __clc_vec2_fp32_t __global *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_sincos(__clc_vec3_fp32_t args_0, + __clc_vec3_fp32_t __global *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_sincos(__clc_vec4_fp32_t args_0, + __clc_vec4_fp32_t __global *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_sincos(__clc_vec8_fp32_t args_0, + __clc_vec8_fp32_t __global *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_sincos(__clc_vec16_fp32_t args_0, + __clc_vec16_fp32_t __global *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_sincos(__clc_fp64_t args_0, __clc_fp64_t __global *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_sincos(__clc_vec2_fp64_t args_0, + __clc_vec2_fp64_t __global *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_sincos(__clc_vec3_fp64_t args_0, + __clc_vec3_fp64_t __global *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_sincos(__clc_vec4_fp64_t args_0, + __clc_vec4_fp64_t __global *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_sincos(__clc_vec8_fp64_t args_0, + __clc_vec8_fp64_t __global *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_sincos(__clc_vec16_fp64_t args_0, + __clc_vec16_fp64_t __global *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_sincos(__clc_fp16_t args_0, __clc_fp16_t __global *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_sincos(__clc_vec2_fp16_t args_0, + __clc_vec2_fp16_t __global *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_sincos(__clc_vec3_fp16_t args_0, + __clc_vec3_fp16_t __global *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_sincos(__clc_vec4_fp16_t args_0, + __clc_vec4_fp16_t __global *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_sincos(__clc_vec8_fp16_t args_0, + __clc_vec8_fp16_t __global *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_sincos(__clc_vec16_fp16_t args_0, + __clc_vec16_fp16_t __global *args_1) { + return __spirv_ocl_sincos(args_0, args_1); +} + +#endif diff --git a/libclc/test/binding/ocl/sinh.cl b/libclc/test/binding/ocl/sinh.cl new file mode 100644 index 0000000000000..0af53d1aa9ba6 --- /dev/null +++ b/libclc/test/binding/ocl/sinh.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_sinh(__clc_fp32_t args_0) { + return __spirv_ocl_sinh(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_sinh(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_sinh(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_sinh(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_sinh(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_sinh(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_sinh(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_sinh(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_sinh(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_sinh(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_sinh(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_sinh(__clc_fp64_t args_0) { + return __spirv_ocl_sinh(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_sinh(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_sinh(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_sinh(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_sinh(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_sinh(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_sinh(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_sinh(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_sinh(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_sinh(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_sinh(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_sinh(__clc_fp16_t args_0) { + return __spirv_ocl_sinh(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_sinh(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_sinh(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_sinh(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_sinh(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_sinh(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_sinh(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_sinh(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_sinh(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_sinh(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_sinh(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/sinpi.cl b/libclc/test/binding/ocl/sinpi.cl new file mode 100644 index 0000000000000..146dbbeab60eb --- /dev/null +++ b/libclc/test/binding/ocl/sinpi.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_sinpi(__clc_fp32_t args_0) { + return __spirv_ocl_sinpi(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_sinpi(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_sinpi(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_sinpi(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_sinpi(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_sinpi(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_sinpi(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_sinpi(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_sinpi(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_sinpi(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_sinpi(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_sinpi(__clc_fp64_t args_0) { + return __spirv_ocl_sinpi(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_sinpi(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_sinpi(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_sinpi(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_sinpi(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_sinpi(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_sinpi(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_sinpi(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_sinpi(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_sinpi(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_sinpi(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_sinpi(__clc_fp16_t args_0) { + return __spirv_ocl_sinpi(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_sinpi(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_sinpi(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_sinpi(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_sinpi(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_sinpi(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_sinpi(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_sinpi(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_sinpi(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_sinpi(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_sinpi(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/tan.cl b/libclc/test/binding/ocl/tan.cl new file mode 100644 index 0000000000000..fb4aaee373ad2 --- /dev/null +++ b/libclc/test/binding/ocl/tan.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_tan(__clc_fp32_t args_0) { + return __spirv_ocl_tan(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_tan(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_tan(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_tan(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_tan(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_tan(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_tan(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_tan(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_tan(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_tan(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_tan(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_tan(__clc_fp64_t args_0) { + return __spirv_ocl_tan(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_tan(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_tan(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_tan(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_tan(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_tan(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_tan(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_tan(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_tan(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_tan(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_tan(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_tan(__clc_fp16_t args_0) { + return __spirv_ocl_tan(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_tan(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_tan(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_tan(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_tan(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_tan(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_tan(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_tan(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_tan(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_tan(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_tan(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/tanh.cl b/libclc/test/binding/ocl/tanh.cl new file mode 100644 index 0000000000000..396ff36b79724 --- /dev/null +++ b/libclc/test/binding/ocl/tanh.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_tanh(__clc_fp32_t args_0) { + return __spirv_ocl_tanh(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_tanh(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_tanh(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_tanh(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_tanh(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_tanh(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_tanh(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_tanh(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_tanh(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_tanh(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_tanh(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_tanh(__clc_fp64_t args_0) { + return __spirv_ocl_tanh(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_tanh(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_tanh(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_tanh(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_tanh(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_tanh(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_tanh(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_tanh(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_tanh(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_tanh(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_tanh(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_tanh(__clc_fp16_t args_0) { + return __spirv_ocl_tanh(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_tanh(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_tanh(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_tanh(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_tanh(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_tanh(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_tanh(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_tanh(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_tanh(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_tanh(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_tanh(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/tanpi.cl b/libclc/test/binding/ocl/tanpi.cl new file mode 100644 index 0000000000000..96e96f202ea9e --- /dev/null +++ b/libclc/test/binding/ocl/tanpi.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_tanpi(__clc_fp32_t args_0) { + return __spirv_ocl_tanpi(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_tanpi(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_tanpi(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_tanpi(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_tanpi(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_tanpi(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_tanpi(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_tanpi(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_tanpi(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_tanpi(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_tanpi(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_tanpi(__clc_fp64_t args_0) { + return __spirv_ocl_tanpi(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_tanpi(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_tanpi(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_tanpi(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_tanpi(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_tanpi(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_tanpi(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_tanpi(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_tanpi(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_tanpi(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_tanpi(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_tanpi(__clc_fp16_t args_0) { + return __spirv_ocl_tanpi(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_tanpi(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_tanpi(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_tanpi(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_tanpi(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_tanpi(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_tanpi(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_tanpi(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_tanpi(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_tanpi(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_tanpi(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/tgamma.cl b/libclc/test/binding/ocl/tgamma.cl new file mode 100644 index 0000000000000..f40763269d2bf --- /dev/null +++ b/libclc/test/binding/ocl/tgamma.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_tgamma(__clc_fp32_t args_0) { + return __spirv_ocl_tgamma(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_tgamma(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_tgamma(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_tgamma(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_tgamma(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_tgamma(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_tgamma(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_tgamma(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_tgamma(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_tgamma(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_tgamma(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_tgamma(__clc_fp64_t args_0) { + return __spirv_ocl_tgamma(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_tgamma(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_tgamma(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_tgamma(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_tgamma(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_tgamma(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_tgamma(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_tgamma(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_tgamma(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_tgamma(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_tgamma(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_tgamma(__clc_fp16_t args_0) { + return __spirv_ocl_tgamma(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_tgamma(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_tgamma(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_tgamma(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_tgamma(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_tgamma(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_tgamma(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_tgamma(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_tgamma(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_tgamma(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_tgamma(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/trunc.cl b/libclc/test/binding/ocl/trunc.cl new file mode 100644 index 0000000000000..74ee74b9fb0d9 --- /dev/null +++ b/libclc/test/binding/ocl/trunc.cl @@ -0,0 +1,131 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_fp32_t +test___spirv_ocl_trunc(__clc_fp32_t args_0) { + return __spirv_ocl_trunc(args_0); +} + +__attribute__((overloadable)) __clc_vec2_fp32_t +test___spirv_ocl_trunc(__clc_vec2_fp32_t args_0) { + return __spirv_ocl_trunc(args_0); +} + +__attribute__((overloadable)) __clc_vec3_fp32_t +test___spirv_ocl_trunc(__clc_vec3_fp32_t args_0) { + return __spirv_ocl_trunc(args_0); +} + +__attribute__((overloadable)) __clc_vec4_fp32_t +test___spirv_ocl_trunc(__clc_vec4_fp32_t args_0) { + return __spirv_ocl_trunc(args_0); +} + +__attribute__((overloadable)) __clc_vec8_fp32_t +test___spirv_ocl_trunc(__clc_vec8_fp32_t args_0) { + return __spirv_ocl_trunc(args_0); +} + +__attribute__((overloadable)) __clc_vec16_fp32_t +test___spirv_ocl_trunc(__clc_vec16_fp32_t args_0) { + return __spirv_ocl_trunc(args_0); +} + +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_fp64_t +test___spirv_ocl_trunc(__clc_fp64_t args_0) { + return __spirv_ocl_trunc(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec2_fp64_t +test___spirv_ocl_trunc(__clc_vec2_fp64_t args_0) { + return __spirv_ocl_trunc(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec3_fp64_t +test___spirv_ocl_trunc(__clc_vec3_fp64_t args_0) { + return __spirv_ocl_trunc(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec4_fp64_t +test___spirv_ocl_trunc(__clc_vec4_fp64_t args_0) { + return __spirv_ocl_trunc(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec8_fp64_t +test___spirv_ocl_trunc(__clc_vec8_fp64_t args_0) { + return __spirv_ocl_trunc(args_0); +} + +#endif +#ifdef cl_khr_fp64 +__attribute__((overloadable)) __clc_vec16_fp64_t +test___spirv_ocl_trunc(__clc_vec16_fp64_t args_0) { + return __spirv_ocl_trunc(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_fp16_t +test___spirv_ocl_trunc(__clc_fp16_t args_0) { + return __spirv_ocl_trunc(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec2_fp16_t +test___spirv_ocl_trunc(__clc_vec2_fp16_t args_0) { + return __spirv_ocl_trunc(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec3_fp16_t +test___spirv_ocl_trunc(__clc_vec3_fp16_t args_0) { + return __spirv_ocl_trunc(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec4_fp16_t +test___spirv_ocl_trunc(__clc_vec4_fp16_t args_0) { + return __spirv_ocl_trunc(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec8_fp16_t +test___spirv_ocl_trunc(__clc_vec8_fp16_t args_0) { + return __spirv_ocl_trunc(args_0); +} + +#endif +#ifdef cl_khr_fp16 +__attribute__((overloadable)) __clc_vec16_fp16_t +test___spirv_ocl_trunc(__clc_vec16_fp16_t args_0) { + return __spirv_ocl_trunc(args_0); +} + +#endif diff --git a/libclc/test/binding/ocl/u_clamp.cl b/libclc/test/binding/ocl/u_clamp.cl new file mode 100644 index 0000000000000..c4e36edf18771 --- /dev/null +++ b/libclc/test/binding/ocl/u_clamp.cl @@ -0,0 +1,163 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ocl_u_clamp(__clc_uint8_t args_0, __clc_uint8_t args_1, + __clc_uint8_t args_2) { + return __spirv_ocl_u_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ocl_u_clamp(__clc_vec2_uint8_t args_0, __clc_vec2_uint8_t args_1, + __clc_vec2_uint8_t args_2) { + return __spirv_ocl_u_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ocl_u_clamp(__clc_vec3_uint8_t args_0, __clc_vec3_uint8_t args_1, + __clc_vec3_uint8_t args_2) { + return __spirv_ocl_u_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ocl_u_clamp(__clc_vec4_uint8_t args_0, __clc_vec4_uint8_t args_1, + __clc_vec4_uint8_t args_2) { + return __spirv_ocl_u_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ocl_u_clamp(__clc_vec8_uint8_t args_0, __clc_vec8_uint8_t args_1, + __clc_vec8_uint8_t args_2) { + return __spirv_ocl_u_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ocl_u_clamp(__clc_vec16_uint8_t args_0, __clc_vec16_uint8_t args_1, + __clc_vec16_uint8_t args_2) { + return __spirv_ocl_u_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ocl_u_clamp(__clc_uint16_t args_0, __clc_uint16_t args_1, + __clc_uint16_t args_2) { + return __spirv_ocl_u_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ocl_u_clamp(__clc_vec2_uint16_t args_0, __clc_vec2_uint16_t args_1, + __clc_vec2_uint16_t args_2) { + return __spirv_ocl_u_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ocl_u_clamp(__clc_vec3_uint16_t args_0, __clc_vec3_uint16_t args_1, + __clc_vec3_uint16_t args_2) { + return __spirv_ocl_u_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ocl_u_clamp(__clc_vec4_uint16_t args_0, __clc_vec4_uint16_t args_1, + __clc_vec4_uint16_t args_2) { + return __spirv_ocl_u_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ocl_u_clamp(__clc_vec8_uint16_t args_0, __clc_vec8_uint16_t args_1, + __clc_vec8_uint16_t args_2) { + return __spirv_ocl_u_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ocl_u_clamp(__clc_vec16_uint16_t args_0, + __clc_vec16_uint16_t args_1, + __clc_vec16_uint16_t args_2) { + return __spirv_ocl_u_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ocl_u_clamp(__clc_uint32_t args_0, __clc_uint32_t args_1, + __clc_uint32_t args_2) { + return __spirv_ocl_u_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ocl_u_clamp(__clc_vec2_uint32_t args_0, __clc_vec2_uint32_t args_1, + __clc_vec2_uint32_t args_2) { + return __spirv_ocl_u_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ocl_u_clamp(__clc_vec3_uint32_t args_0, __clc_vec3_uint32_t args_1, + __clc_vec3_uint32_t args_2) { + return __spirv_ocl_u_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ocl_u_clamp(__clc_vec4_uint32_t args_0, __clc_vec4_uint32_t args_1, + __clc_vec4_uint32_t args_2) { + return __spirv_ocl_u_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ocl_u_clamp(__clc_vec8_uint32_t args_0, __clc_vec8_uint32_t args_1, + __clc_vec8_uint32_t args_2) { + return __spirv_ocl_u_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ocl_u_clamp(__clc_vec16_uint32_t args_0, + __clc_vec16_uint32_t args_1, + __clc_vec16_uint32_t args_2) { + return __spirv_ocl_u_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ocl_u_clamp(__clc_uint64_t args_0, __clc_uint64_t args_1, + __clc_uint64_t args_2) { + return __spirv_ocl_u_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ocl_u_clamp(__clc_vec2_uint64_t args_0, __clc_vec2_uint64_t args_1, + __clc_vec2_uint64_t args_2) { + return __spirv_ocl_u_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ocl_u_clamp(__clc_vec3_uint64_t args_0, __clc_vec3_uint64_t args_1, + __clc_vec3_uint64_t args_2) { + return __spirv_ocl_u_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ocl_u_clamp(__clc_vec4_uint64_t args_0, __clc_vec4_uint64_t args_1, + __clc_vec4_uint64_t args_2) { + return __spirv_ocl_u_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ocl_u_clamp(__clc_vec8_uint64_t args_0, __clc_vec8_uint64_t args_1, + __clc_vec8_uint64_t args_2) { + return __spirv_ocl_u_clamp(args_0, args_1, args_2); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ocl_u_clamp(__clc_vec16_uint64_t args_0, + __clc_vec16_uint64_t args_1, + __clc_vec16_uint64_t args_2) { + return __spirv_ocl_u_clamp(args_0, args_1, args_2); +} diff --git a/libclc/test/binding/ocl/u_max.cl b/libclc/test/binding/ocl/u_max.cl new file mode 100644 index 0000000000000..22ab628741adc --- /dev/null +++ b/libclc/test/binding/ocl/u_max.cl @@ -0,0 +1,139 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ocl_u_max(__clc_uint8_t args_0, __clc_uint8_t args_1) { + return __spirv_ocl_u_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ocl_u_max(__clc_vec2_uint8_t args_0, __clc_vec2_uint8_t args_1) { + return __spirv_ocl_u_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ocl_u_max(__clc_vec3_uint8_t args_0, __clc_vec3_uint8_t args_1) { + return __spirv_ocl_u_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ocl_u_max(__clc_vec4_uint8_t args_0, __clc_vec4_uint8_t args_1) { + return __spirv_ocl_u_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ocl_u_max(__clc_vec8_uint8_t args_0, __clc_vec8_uint8_t args_1) { + return __spirv_ocl_u_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ocl_u_max(__clc_vec16_uint8_t args_0, __clc_vec16_uint8_t args_1) { + return __spirv_ocl_u_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ocl_u_max(__clc_uint16_t args_0, __clc_uint16_t args_1) { + return __spirv_ocl_u_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ocl_u_max(__clc_vec2_uint16_t args_0, __clc_vec2_uint16_t args_1) { + return __spirv_ocl_u_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ocl_u_max(__clc_vec3_uint16_t args_0, __clc_vec3_uint16_t args_1) { + return __spirv_ocl_u_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ocl_u_max(__clc_vec4_uint16_t args_0, __clc_vec4_uint16_t args_1) { + return __spirv_ocl_u_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ocl_u_max(__clc_vec8_uint16_t args_0, __clc_vec8_uint16_t args_1) { + return __spirv_ocl_u_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ocl_u_max(__clc_vec16_uint16_t args_0, + __clc_vec16_uint16_t args_1) { + return __spirv_ocl_u_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ocl_u_max(__clc_uint32_t args_0, __clc_uint32_t args_1) { + return __spirv_ocl_u_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ocl_u_max(__clc_vec2_uint32_t args_0, __clc_vec2_uint32_t args_1) { + return __spirv_ocl_u_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ocl_u_max(__clc_vec3_uint32_t args_0, __clc_vec3_uint32_t args_1) { + return __spirv_ocl_u_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ocl_u_max(__clc_vec4_uint32_t args_0, __clc_vec4_uint32_t args_1) { + return __spirv_ocl_u_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ocl_u_max(__clc_vec8_uint32_t args_0, __clc_vec8_uint32_t args_1) { + return __spirv_ocl_u_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ocl_u_max(__clc_vec16_uint32_t args_0, + __clc_vec16_uint32_t args_1) { + return __spirv_ocl_u_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ocl_u_max(__clc_uint64_t args_0, __clc_uint64_t args_1) { + return __spirv_ocl_u_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ocl_u_max(__clc_vec2_uint64_t args_0, __clc_vec2_uint64_t args_1) { + return __spirv_ocl_u_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ocl_u_max(__clc_vec3_uint64_t args_0, __clc_vec3_uint64_t args_1) { + return __spirv_ocl_u_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ocl_u_max(__clc_vec4_uint64_t args_0, __clc_vec4_uint64_t args_1) { + return __spirv_ocl_u_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ocl_u_max(__clc_vec8_uint64_t args_0, __clc_vec8_uint64_t args_1) { + return __spirv_ocl_u_max(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ocl_u_max(__clc_vec16_uint64_t args_0, + __clc_vec16_uint64_t args_1) { + return __spirv_ocl_u_max(args_0, args_1); +} diff --git a/libclc/test/binding/ocl/u_min.cl b/libclc/test/binding/ocl/u_min.cl new file mode 100644 index 0000000000000..f283c66629105 --- /dev/null +++ b/libclc/test/binding/ocl/u_min.cl @@ -0,0 +1,139 @@ + +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Autogenerated by gen-libclc-test.py + +// RUN: %clang -emit-llvm -S -o - %s | FileCheck %s + +#include + +// CHECK-NOT: declare {{.*}} @_Z +// CHECK-NOT: call {{[^ ]*}} bitcast +__attribute__((overloadable)) __clc_uint8_t +test___spirv_ocl_u_min(__clc_uint8_t args_0, __clc_uint8_t args_1) { + return __spirv_ocl_u_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint8_t +test___spirv_ocl_u_min(__clc_vec2_uint8_t args_0, __clc_vec2_uint8_t args_1) { + return __spirv_ocl_u_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint8_t +test___spirv_ocl_u_min(__clc_vec3_uint8_t args_0, __clc_vec3_uint8_t args_1) { + return __spirv_ocl_u_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint8_t +test___spirv_ocl_u_min(__clc_vec4_uint8_t args_0, __clc_vec4_uint8_t args_1) { + return __spirv_ocl_u_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint8_t +test___spirv_ocl_u_min(__clc_vec8_uint8_t args_0, __clc_vec8_uint8_t args_1) { + return __spirv_ocl_u_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint8_t +test___spirv_ocl_u_min(__clc_vec16_uint8_t args_0, __clc_vec16_uint8_t args_1) { + return __spirv_ocl_u_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_uint16_t +test___spirv_ocl_u_min(__clc_uint16_t args_0, __clc_uint16_t args_1) { + return __spirv_ocl_u_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint16_t +test___spirv_ocl_u_min(__clc_vec2_uint16_t args_0, __clc_vec2_uint16_t args_1) { + return __spirv_ocl_u_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint16_t +test___spirv_ocl_u_min(__clc_vec3_uint16_t args_0, __clc_vec3_uint16_t args_1) { + return __spirv_ocl_u_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint16_t +test___spirv_ocl_u_min(__clc_vec4_uint16_t args_0, __clc_vec4_uint16_t args_1) { + return __spirv_ocl_u_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint16_t +test___spirv_ocl_u_min(__clc_vec8_uint16_t args_0, __clc_vec8_uint16_t args_1) { + return __spirv_ocl_u_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint16_t +test___spirv_ocl_u_min(__clc_vec16_uint16_t args_0, + __clc_vec16_uint16_t args_1) { + return __spirv_ocl_u_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_uint32_t +test___spirv_ocl_u_min(__clc_uint32_t args_0, __clc_uint32_t args_1) { + return __spirv_ocl_u_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint32_t +test___spirv_ocl_u_min(__clc_vec2_uint32_t args_0, __clc_vec2_uint32_t args_1) { + return __spirv_ocl_u_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint32_t +test___spirv_ocl_u_min(__clc_vec3_uint32_t args_0, __clc_vec3_uint32_t args_1) { + return __spirv_ocl_u_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint32_t +test___spirv_ocl_u_min(__clc_vec4_uint32_t args_0, __clc_vec4_uint32_t args_1) { + return __spirv_ocl_u_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint32_t +test___spirv_ocl_u_min(__clc_vec8_uint32_t args_0, __clc_vec8_uint32_t args_1) { + return __spirv_ocl_u_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint32_t +test___spirv_ocl_u_min(__clc_vec16_uint32_t args_0, + __clc_vec16_uint32_t args_1) { + return __spirv_ocl_u_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_uint64_t +test___spirv_ocl_u_min(__clc_uint64_t args_0, __clc_uint64_t args_1) { + return __spirv_ocl_u_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec2_uint64_t +test___spirv_ocl_u_min(__clc_vec2_uint64_t args_0, __clc_vec2_uint64_t args_1) { + return __spirv_ocl_u_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec3_uint64_t +test___spirv_ocl_u_min(__clc_vec3_uint64_t args_0, __clc_vec3_uint64_t args_1) { + return __spirv_ocl_u_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec4_uint64_t +test___spirv_ocl_u_min(__clc_vec4_uint64_t args_0, __clc_vec4_uint64_t args_1) { + return __spirv_ocl_u_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec8_uint64_t +test___spirv_ocl_u_min(__clc_vec8_uint64_t args_0, __clc_vec8_uint64_t args_1) { + return __spirv_ocl_u_min(args_0, args_1); +} + +__attribute__((overloadable)) __clc_vec16_uint64_t +test___spirv_ocl_u_min(__clc_vec16_uint64_t args_0, + __clc_vec16_uint64_t args_1) { + return __spirv_ocl_u_min(args_0, args_1); +} diff --git a/libclc/utils/gen-libclc-test.py b/libclc/utils/gen-libclc-test.py index 6d9b8e73326eb..e2af837254d77 100755 --- a/libclc/utils/gen-libclc-test.py +++ b/libclc/utils/gen-libclc-test.py @@ -12,65 +12,26 @@ from spirv_common import ignore_overload, emit_guards, close_guards, clang_format def ignore_function(fun): - whitelist = [ - "_All", - "_Any", - "_step", - "abs", - "abs_diff", - "add_sat", - "BitCount", - "bitselect", - "clz", - "ControlBarrier", - "cross", - "ctz", - "degrees", - "distance", - "Dot", - "Equal", - "GreaterThan", - "GreaterThanEqual", - "GroupAsyncCopy", - "GroupWaitEvents", - "hadd", - "hadd", - "IsFinite", - "IsInf", - "IsNan", - "IsNormal", - "length", - "LessOrGreater", - "LessThan", - "LessThanEqual", - "mad24", - "mad_hi", - "mad_sat", - "MemoryBarrier", - "mix", - "mul24", - "mul_hi", - "normalize", - "NotEqual", - "Ordered", - "popcount", - "prefetch", - "radians", - "rhadd", - "rotate", - "select", - "sign", - "SignBitSet", - "smoothstep", - "sqrt", - "sub_sat", - "Unordered", - "upsample", - "vload", - "vstore" + blacklist = [ + "Convert", + "GenericCastToPtrExplicit", + "GenericPtrMemSemantics", + "GroupAll", + "GroupAny", + "GroupBroadcast", + "GroupFAdd", + "GroupFMax", + "GroupFMin", + "GroupIAdd", + "GroupSMax", + "GroupSMin", + "GroupUMax", + "GroupUMin", + "printf", + "VectorTimesScalar", + "shuffle" ] - - return not any([fun.find(b) != -1 for b in whitelist]) + return any([fun.find(b) != -1 for b in blacklist]) def get_builtin_name(func): func = func.replace("__spirv_", "") diff --git a/sycl/test/built-ins/scalar_common.cpp b/sycl/test/built-ins/scalar_common.cpp index 10e2fdd5f61a9..0989d0e16f409 100644 --- a/sycl/test/built-ins/scalar_common.cpp +++ b/sycl/test/built-ins/scalar_common.cpp @@ -4,9 +4,6 @@ // RUN: %GPU_RUN_PLACEHOLDER %t.out // RUN: %ACC_RUN_PLACEHOLDER %t.out -// TODO: ptxas fatal : Unresolved extern function '_Z23__spirv_ocl_fmax_commonff' -// XFAIL: cuda - #include #include diff --git a/sycl/test/built-ins/scalar_math_2.cpp b/sycl/test/built-ins/scalar_math_2.cpp index c9805e0356d6a..6747f0ea99b71 100644 --- a/sycl/test/built-ins/scalar_math_2.cpp +++ b/sycl/test/built-ins/scalar_math_2.cpp @@ -4,9 +4,6 @@ // RUN: %GPU_RUN_PLACEHOLDER %t.out // RUN: %ACC_RUN_PLACEHOLDER %t.out -// TODO: ptxas fatal : Unresolved extern function '_Z18__spirv_ocl_acospif' -// XFAIL: cuda - #include #include diff --git a/sycl/test/built-ins/vector_common.cpp b/sycl/test/built-ins/vector_common.cpp index bb9d096831f9a..9dda5e2941882 100644 --- a/sycl/test/built-ins/vector_common.cpp +++ b/sycl/test/built-ins/vector_common.cpp @@ -4,9 +4,6 @@ // RUN: %GPU_RUN_PLACEHOLDER %t.out // RUN: %ACC_RUN_PLACEHOLDER %t.out -// TODO: ptxas fatal : Unresolved extern function '_Z23__spirv_ocl_fmax_commonDv2_fS_' -// XFAIL: cuda - #include #include diff --git a/sycl/test/built-ins/vector_math.cpp b/sycl/test/built-ins/vector_math.cpp index 3e13735d33634..8806eb1d8deb1 100644 --- a/sycl/test/built-ins/vector_math.cpp +++ b/sycl/test/built-ins/vector_math.cpp @@ -4,9 +4,6 @@ // RUN: %GPU_RUN_PLACEHOLDER %t.out // RUN: %ACC_RUN_PLACEHOLDER %t.out -// TODO: ptxas fatal : Unresolved extern function '_Z17__spirv_ocl_fractDv2_fPU3AS0S_' -// XFAIL: cuda - #include #include