diff --git a/SYCL/Basic/fpga_tests/fpga_latency_control_lsu.cpp b/SYCL/Basic/fpga_tests/fpga_latency_control_lsu.cpp
index 86fd79d718..99b87e5f60 100644
--- a/SYCL/Basic/fpga_tests/fpga_latency_control_lsu.cpp
+++ b/SYCL/Basic/fpga_tests/fpga_latency_control_lsu.cpp
@@ -40,11 +40,16 @@ int test_latency_control(queue Queue) {
         auto in_ptr = input_accessor.get_pointer();
         auto out_ptr = output_accessor.get_pointer();
 
-        float value = PrefetchingLSU::load<
-            ext::intel::experimental::latency_anchor_id<0>>(in_ptr);
-
-        BurstCoalescedLSU::store<ext::intel::experimental::latency_constraint<
-            0, ext::intel::experimental::type::exact, 5>>(out_ptr, value);
+        float value = PrefetchingLSU::load(
+            in_ptr, ext::oneapi::experimental::properties(
+                        ext::intel::experimental::latency_anchor_id<0>));
+
+        BurstCoalescedLSU::store(
+            out_ptr, value,
+            ext::oneapi::experimental::properties(
+                ext::intel::experimental::latency_constraint<
+                    0, ext::intel::experimental::latency_control_type::exact,
+                    5>));
       });
     });
   }
diff --git a/SYCL/Basic/fpga_tests/fpga_latency_control_pipe.cpp b/SYCL/Basic/fpga_tests/fpga_latency_control_pipe.cpp
index f27477e0f5..eaad84725a 100644
--- a/SYCL/Basic/fpga_tests/fpga_latency_control_pipe.cpp
+++ b/SYCL/Basic/fpga_tests/fpga_latency_control_pipe.cpp
@@ -34,12 +34,16 @@ int test_latency_control(queue Queue) {
       cgh.single_task<class kernel>([=] {
         Pipe1::write(input_accessor[0]);
 
-        int value =
-            Pipe1::read<ext::intel::experimental::latency_anchor_id<0>>();
-
-        Pipe2::write<ext::intel::experimental::latency_anchor_id<1>,
-                     ext::intel::experimental::latency_constraint<
-                         0, ext::intel::experimental::type::exact, 2>>(value);
+        int value = Pipe1::read(ext::oneapi::experimental::properties(
+            ext::intel::experimental::latency_anchor_id<0>));
+
+        Pipe2::write(
+            value,
+            ext::oneapi::experimental::properties(
+                ext::intel::experimental::latency_anchor_id<1>,
+                ext::intel::experimental::latency_constraint<
+                    0, ext::intel::experimental::latency_control_type::exact,
+                    2>));
 
         output_accessor[0] = Pipe2::read();
       });