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crc: add RISC-V implementation
The CRC module of ISA-L has been accelerated using RISC-V's V, Zbc and Zvbc, instruction sets, implementing data folding and Barrett reduction optimizations. Signed-off-by: Ji Dong <[email protected]>
1 parent 73c5044 commit ade80d5

35 files changed

+3664
-18
lines changed

‎configure.ac‎

Lines changed: 73 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -38,6 +38,9 @@ AM_CONDITIONAL([CPU_PPC64LE], [test "$CPU" = "ppc64le"])
3838
AM_CONDITIONAL([CPU_RISCV64], [test "$CPU" = "riscv64"])
3939
AM_CONDITIONAL([CPU_UNDEFINED], [test "x$CPU" = "x"])
4040
AM_CONDITIONAL([HAVE_RVV], [false])
41+
AM_CONDITIONAL([HAVE_ZBC], [false])
42+
AM_CONDITIONAL([HAVE_ZVBC], [false])
43+
AM_CONDITIONAL([HAVE_HWPROBE_H], [false])
4144

4245
# Check for programs
4346
AC_PROG_CC_STDC
@@ -57,24 +60,78 @@ case "${CPU}" in
5760

5861
riscv64)
5962

60-
AC_MSG_CHECKING([checking RVV support])
61-
AC_COMPILE_IFELSE(
62-
[AC_LANG_PROGRAM([], [
63-
__asm__ volatile(
64-
".option arch, +v\n"
65-
"vsetivli zero, 0, e8, m1, ta, ma\n"
66-
);
67-
])],
68-
[AC_DEFINE([HAVE_RVV], [1], [Enable RVV instructions])
69-
AM_CONDITIONAL([HAVE_RVV], [true]) rvv=yes],
70-
[AC_DEFINE([HAVE_RVV], [0], [Disable RVV instructions])
71-
AM_CONDITIONAL([HAVE_RVV], [false]) rvv=no]
63+
AC_CHECK_HEADER([asm/hwprobe.h],
64+
[AC_DEFINE([HAVE_HWPROBE_H], [1], [Define if asm/hwprobe.h exists])
65+
AM_CONDITIONAL([HAVE_HWPROBE_H], [true]) hwprobe_h=yes],
66+
[AC_DEFINE([HAVE_HWPROBE_H], [0], [Define if asm/hwprobe.h not exists])
67+
AM_CONDITIONAL([HAVE_HWPROBE_H], [false]) hwprobe_h=no]
7268
)
73-
if test "x$rvv" = "xyes"; then
74-
CFLAGS+=" -march=rv64gcv"
75-
CCASFLAGS+=" -march=rv64gcv"
69+
if test "x$hwprobe_h" = "xyes"; then
70+
AC_MSG_CHECKING([ZBC support])
71+
AC_COMPILE_IFELSE(
72+
[AC_LANG_PROGRAM([#include <asm/hwprobe.h>], [
73+
int a = RISCV_HWPROBE_EXT_ZBC;
74+
__asm__ volatile(
75+
".option arch, +zbc\n"
76+
"clmul zero, zero, zero\n"
77+
"clmulh zero, zero, zero\n"
78+
);
79+
])],
80+
[AC_DEFINE([HAVE_ZBC], [1], [Enable ZBC instructions])
81+
AM_CONDITIONAL([HAVE_ZBC], [true]) zbc=yes],
82+
[AC_DEFINE([HAVE_ZBC], [0], [Disable ZBC instructions])
83+
AM_CONDITIONAL([HAVE_ZBC], [false]) zbc=no]
84+
)
85+
AC_MSG_RESULT([$zbc])
86+
AC_MSG_CHECKING([ZVBC support])
87+
AC_COMPILE_IFELSE(
88+
[AC_LANG_PROGRAM([#include <asm/hwprobe.h>], [
89+
int a = RISCV_HWPROBE_EXT_ZVBC;
90+
__asm__ volatile(
91+
".option arch, +v, +zvbc\n"
92+
"vsetivli zero, 2, e64, m1, ta, ma\n"
93+
"vclmul.vv v0, v0, v0\n"
94+
"vclmulh.vv v0, v0, v0\n"
95+
);
96+
])],
97+
[AC_DEFINE([HAVE_ZVBC], [1], [Enable ZVBC instructions])
98+
AM_CONDITIONAL([HAVE_ZVBC], [true]) zvbc=yes],
99+
[AC_DEFINE([HAVE_ZVBC], [0], [Disable ZVBC instructions])
100+
AM_CONDITIONAL([HAVE_ZVBC], [false]) zvbc=no]
101+
)
102+
AC_MSG_RESULT([$zvbc])
76103
fi
104+
AC_MSG_CHECKING([RVV support])
105+
AS_IF([test "x$zvbc" = "xno"],
106+
[
107+
AC_COMPILE_IFELSE(
108+
[AC_LANG_PROGRAM([], [
109+
__asm__ volatile(
110+
".option arch, +v\n"
111+
"vsetivli zero, 0, e8, m1, ta, ma\n"
112+
);
113+
])],
114+
[AC_DEFINE([HAVE_RVV], [1], [Enable RVV instructions])
115+
AM_CONDITIONAL([HAVE_RVV], [true]) rvv=yes],
116+
[AC_DEFINE([HAVE_RVV], [0], [Disable RVV instructions])
117+
AM_CONDITIONAL([HAVE_RVV], [false]) rvv=no]
118+
)
119+
],
120+
[AC_DEFINE([HAVE_RVV], [1], [Enable RVV instructions])
121+
AM_CONDITIONAL([HAVE_RVV], [true]) rvv=yes]
122+
)
77123
AC_MSG_RESULT([$rvv])
124+
AS_IF([test "x$zvbc" = "xyes" && test "x$zbc" = "xyes"],
125+
[
126+
CFLAGS="$CFLAGS -march=rv64gcv_zbc_zvbc"
127+
CCASFLAGS="$CCASFLAGS -march=rv64gcv_zbc_zvbc"
128+
],
129+
[test "x$rvv" = "xyes"],
130+
[
131+
CFLAGS="$CFLAGS -march=rv64gcv"
132+
CCASFLAGS="$CCASFLAGS -march=rv64gcv"
133+
]
134+
)
78135
;;
79136

80137
*)
@@ -239,4 +296,4 @@ AC_MSG_RESULT([
239296
ldflags: ${LDFLAGS}
240297
241298
debug: ${enable_debug}
242-
])
299+
])

‎crc/Makefile.am‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -28,14 +28,14 @@
2828
########################################################################
2929

3030
include crc/aarch64/Makefile.am
31+
include crc/riscv64/Makefile.am
3132

3233
lsrc += \
3334
crc/crc_base.c \
3435
crc/crc64_base.c
3536

3637
lsrc_base_aliases += crc/crc_base_aliases.c
3738
lsrc_ppc64le += crc/crc_base_aliases.c
38-
lsrc_riscv64 += crc/crc_base_aliases.c
3939

4040
lsrc_x86_64 += \
4141
crc/crc16_t10dif_01.asm \

‎crc/riscv64/Makefile.am‎

Lines changed: 46 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,46 @@
1+
########################################################################
2+
# Copyright(c) 2025 ZTE Corporation All rights reserved.
3+
#
4+
# Redistribution and use in source and binary forms, with or without
5+
# modification, are permitted provided that the following conditions
6+
# are met:
7+
# * Redistributions of source code must retain the above copyright
8+
# notice, this list of conditions and the following disclaimer.
9+
# * Redistributions in binary form must reproduce the above copyright
10+
# notice, this list of conditions and the following disclaimer in
11+
# the documentation and/or other materials provided with the
12+
# distribution.
13+
# * Neither the name of ZTE Corporation nor the names of its
14+
# contributors may be used to endorse or promote products derived
15+
# from this software without specific prior written permission.
16+
#
17+
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18+
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19+
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20+
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21+
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22+
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23+
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24+
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25+
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26+
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27+
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28+
#########################################################################
29+
lsrc_riscv64 += \
30+
crc/riscv64/crc_multibinary_riscv.S \
31+
crc/riscv64/crc_riscv64_dispatcher.c
32+
33+
lsrc_riscv64 += \
34+
crc/riscv64/crc16_t10dif_vclmul.S \
35+
crc/riscv64/crc16_t10dif_copy_vclmul.S \
36+
crc/riscv64/crc32_ieee_norm_vclmul.S \
37+
crc/riscv64/crc32_iscsi_refl_vclmul.S \
38+
crc/riscv64/crc32_gzip_refl_vclmul.S \
39+
crc/riscv64/crc64_ecma_refl_vclmul.S \
40+
crc/riscv64/crc64_ecma_norm_vclmul.S \
41+
crc/riscv64/crc64_iso_refl_vclmul.S \
42+
crc/riscv64/crc64_iso_norm_vclmul.S \
43+
crc/riscv64/crc64_jones_refl_vclmul.S \
44+
crc/riscv64/crc64_jones_norm_vclmul.S \
45+
crc/riscv64/crc64_rocksoft_refl_vclmul.S \
46+
crc/riscv64/crc64_rocksoft_norm_vclmul.S

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