cpu: add support for DIT detection

rolandshoemaker · rolandshoemaker · commit 47fe91694258 · 2024-07-11T16:45:38.000Z
Change-Id: I9f0991da9684ebd297e40a754e34130c418c34d0 Reviewed-on: https://go-review.googlesource.com/c/sys/+/597377 Reviewed-by: Ian Lance Taylor <iant@google.com> LUCI-TryBot-Result: Go LUCI <golang-scoped@luci-project-accounts.iam.gserviceaccount.com>
diff --git a/cpu/cpu.go b/cpu/cpu.go
@@ -105,6 +105,7 @@ var ARM64 struct {
 	HasSVE      bool // Scalable Vector Extensions
 	HasSVE2     bool // Scalable Vector Extensions 2
 	HasASIMDFHM bool // Advanced SIMD multiplication FP16 to FP32
+	HasDIT      bool // Data Independent Timing support
 	_           CacheLinePad
 }
 
diff --git a/cpu/cpu_arm64.go b/cpu/cpu_arm64.go
@@ -168,6 +168,11 @@ func parseARM64SystemRegisters(isar0, isar1, pfr0 uint64) {
 
 		parseARM64SVERegister(getzfr0())
 	}
+
+	switch extractBits(pfr0, 48, 51) {
+	case 1:
+		ARM64.HasDIT = true
+	}
 }
 
 func parseARM64SVERegister(zfr0 uint64) {

Original file line number	Diff line number	Diff line change
`@@ -105,6 +105,7 @@ var ARM64 struct {`
`105`	`105`	`HasSVE bool // Scalable Vector Extensions`
`106`	`106`	`HasSVE2 bool // Scalable Vector Extensions 2`
`107`	`107`	`HasASIMDFHM bool // Advanced SIMD multiplication FP16 to FP32`
	`108`	`+ HasDIT bool // Data Independent Timing support`
`108`	`109`	`_ CacheLinePad`
`109`	`110`	`}`
`110`	`111`
Original file line number	Diff line number	Diff line change
`@@ -168,6 +168,11 @@ func parseARM64SystemRegisters(isar0, isar1, pfr0 uint64) {`
`168`	`168`
`169`	`169`	`parseARM64SVERegister(getzfr0())`
`170`	`170`	`}`
	`171`	`+`
	`172`	`+ switch extractBits(pfr0, 48, 51) {`
	`173`	`+ case 1:`
	`174`	`+ ARM64.HasDIT = true`
	`175`	`+ }`
`171`	`176`	`}`
`172`	`177`
`173`	`178`	`func parseARM64SVERegister(zfr0 uint64) {`