cmd/compile: use ISEL, cleanup use of zero & extensions

Abandoned earlier efforts to expose zero register,
but left it in numbering to decrease squirrelyness of
register allocator.

ISELrelOp used in code generation of bool := x relOp y.
Some patterns added to better elide zero case and
some sign extension.

Updates: #17109

Change-Id: Ida7839f0023ca8f0ffddc0545f0ac269e65b05d9
Reviewed-on: https://go-review.googlesource.com/29380
Run-TryBot: David Chase <[email protected]>
TryBot-Result: Gobot Gobot <[email protected]>
Reviewed-by: Keith Randall <[email protected]>
Reviewed-by: Cherry Zhang <[email protected]>

Author: dr2chase

src/cmd/compile/internal/gc/go.go

@@ -336,6 +336,9 @@ const (
 
 	// Instruction updates whichever of from/to is type D_OREG. (ppc64)
 	PostInc = 1 << 29
+
+	// Optional 3rd input operand, only ever read.
+	From3Read = 1 << 30
 )
 
 type Arch struct {

src/cmd/compile/internal/gc/plive.go

@@ -624,6 +624,20 @@ func progeffects(prog *obj.Prog, vars []*Node, uevar bvec, varkill bvec, avarini
 		}
 	}
 
+	if info.Flags&From3Read != 0 {
+		from := prog.From3
+		if from.Node != nil && from.Sym != nil {
+			n := from.Node.(*Node)
+			if pos := liveIndex(n, vars); pos >= 0 {
+				if n.Addrtaken {
+					bvset(avarinit, pos)
+				} else {
+					bvset(uevar, pos)
+				}
+			}
+		}
+	}
+
 	if info.Flags&(RightRead|RightWrite|RightAddr) != 0 {
 		to := &prog.To
 		if to.Node != nil && to.Sym != nil {

src/cmd/compile/internal/ppc64/prog.go

@@ -100,6 +100,8 @@ var progtable = [ppc64.ALAST & obj.AMask]gc.ProgInfo{
 	ppc64.AMOVHZ & obj.AMask: {Flags: gc.SizeW | gc.LeftRead | gc.RightWrite | gc.Move | gc.Conv},
 	ppc64.AMOVW & obj.AMask:  {Flags: gc.SizeL | gc.LeftRead | gc.RightWrite | gc.Move | gc.Conv},
 
+	ppc64.AISEL & obj.AMask: {Flags: gc.SizeQ | gc.RegRead | gc.From3Read | gc.RightWrite},
+
 	// there is no AMOVWU.
 	ppc64.AMOVWZU & obj.AMask: {Flags: gc.SizeL | gc.LeftRead | gc.RightWrite | gc.Move | gc.Conv | gc.PostInc},
 	ppc64.AMOVWZ & obj.AMask:  {Flags: gc.SizeL | gc.LeftRead | gc.RightWrite | gc.Move | gc.Conv},

src/cmd/compile/internal/ppc64/ssa.go

@@ -26,6 +26,28 @@ var condOps = map[ssa.Op]obj.As{
 	ssa.OpPPC64FGreaterEqual: ppc64.ABGT, // 2 branches for FCMP >=, second is BEQ
 }
 
+// iselOp encodes mapping of comparison operations onto ISEL operands
+type iselOp struct {
+	cond        int64
+	valueIfCond int // if cond is true, the value to return (0 or 1)
+}
+
+// Input registers to ISEL used for comparison. Index 0 is zero, 1 is (will be) 1
+var iselRegs = [2]int16{ppc64.REG_R0, ppc64.REGTMP}
+
+var iselOps = map[ssa.Op]iselOp{
+	ssa.OpPPC64Equal:         iselOp{cond: ppc64.C_COND_EQ, valueIfCond: 1},
+	ssa.OpPPC64NotEqual:      iselOp{cond: ppc64.C_COND_EQ, valueIfCond: 0},
+	ssa.OpPPC64LessThan:      iselOp{cond: ppc64.C_COND_LT, valueIfCond: 1},
+	ssa.OpPPC64GreaterEqual:  iselOp{cond: ppc64.C_COND_LT, valueIfCond: 0},
+	ssa.OpPPC64GreaterThan:   iselOp{cond: ppc64.C_COND_GT, valueIfCond: 1},
+	ssa.OpPPC64LessEqual:     iselOp{cond: ppc64.C_COND_GT, valueIfCond: 0},
+	ssa.OpPPC64FLessThan:     iselOp{cond: ppc64.C_COND_LT, valueIfCond: 1},
+	ssa.OpPPC64FGreaterThan:  iselOp{cond: ppc64.C_COND_GT, valueIfCond: 1},
+	ssa.OpPPC64FLessEqual:    iselOp{cond: ppc64.C_COND_LT, valueIfCond: 1}, // 2 comparisons, 2nd is EQ
+	ssa.OpPPC64FGreaterEqual: iselOp{cond: ppc64.C_COND_GT, valueIfCond: 1}, // 2 comparisons, 2nd is EQ
+}
+
 // markMoves marks any MOVXconst ops that need to avoid clobbering flags.
 func ssaMarkMoves(s *gc.SSAGenState, b *ssa.Block) {
 	//	flive := b.FlagsLiveAtEnd
@@ -34,7 +56,7 @@ func ssaMarkMoves(s *gc.SSAGenState, b *ssa.Block) {
 	//	}
 	//	for i := len(b.Values) - 1; i >= 0; i-- {
 	//		v := b.Values[i]
-	//		if flive && (v.Op == ssa.OpPPC64MOVWconst || v.Op == ssa.OpPPC64MOVDconst) {
+	//		if flive && (v.Op == v.Op == ssa.OpPPC64MOVDconst) {
 	//			// The "mark" is any non-nil Aux value.
 	//			v.Aux = v
 	//		}
@@ -120,6 +142,17 @@ func scratchFpMem(s *gc.SSAGenState, a *obj.Addr) {
 	a.Reg = ppc64.REGSP
 }
 
+func ssaGenISEL(v *ssa.Value, cr int64, r1, r2 int16) {
+	r := v.Reg()
+	p := gc.Prog(ppc64.AISEL)
+	p.To.Type = obj.TYPE_REG
+	p.To.Reg = r
+	p.Reg = r1
+	p.From3 = &obj.Addr{Type: obj.TYPE_REG, Reg: r2}
+	p.From.Type = obj.TYPE_CONST
+	p.From.Offset = cr
+}
+
 func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
 	s.SetLineno(v.Line)
 	switch v.Op {
@@ -382,7 +415,7 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
 			v.Fatalf("bad reg %s for symbol type %T, want %s", reg, v.Aux, wantreg)
 		}
 
-	case ssa.OpPPC64MOVDconst, ssa.OpPPC64MOVWconst:
+	case ssa.OpPPC64MOVDconst:
 		p := gc.Prog(v.Op.Asm())
 		p.From.Type = obj.TYPE_CONST
 		p.From.Offset = v.AuxInt
@@ -418,7 +451,7 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
 		p.To.Reg = v.Reg()
 		p.To.Type = obj.TYPE_REG
 
-	case ssa.OpPPC64MOVDload, ssa.OpPPC64MOVWload, ssa.OpPPC64MOVBload, ssa.OpPPC64MOVHload, ssa.OpPPC64MOVWZload, ssa.OpPPC64MOVBZload, ssa.OpPPC64MOVHZload:
+	case ssa.OpPPC64MOVDload, ssa.OpPPC64MOVWload, ssa.OpPPC64MOVHload, ssa.OpPPC64MOVWZload, ssa.OpPPC64MOVBZload, ssa.OpPPC64MOVHZload:
 		p := gc.Prog(v.Op.Asm())
 		p.From.Type = obj.TYPE_MEM
 		p.From.Reg = v.Args[0].Reg()
@@ -465,65 +498,80 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
 		ssa.OpPPC64GreaterThan,
 		ssa.OpPPC64FGreaterThan,
 		ssa.OpPPC64GreaterEqual:
+
 		// On Power7 or later, can use isel instruction:
 		// for a < b, a > b, a = b:
-		//   rt := 1
-		//   isel rt,rt,r0,cond
+		//   rtmp := 1
+		//   isel rt,rtmp,r0,cond // rt is target in ppc asm
 
 		// for  a >= b, a <= b, a != b:
-		//   rt := 1
-		//   isel rt,0,rt,!cond
-
-		// However, PPCbe support is for older machines than that,
-		// and isel (which looks a lot like fsel) isn't recognized
-		// yet by the Go assembler.  So for now, use the old instruction
-		// sequence, which we'll need anyway.
-		// TODO: add support for isel on PPCle and use it.
+		//   rtmp := 1
+		//   isel rt,0,rtmp,!cond // rt is target in ppc asm
 
-		// generate boolean values
-		// use conditional move
+		if v.Block.Func.Config.OldArch {
+			p := gc.Prog(ppc64.AMOVD)
+			p.From.Type = obj.TYPE_CONST
+			p.From.Offset = 1
+			p.To.Type = obj.TYPE_REG
+			p.To.Reg = v.Reg()
 
-		p := gc.Prog(ppc64.AMOVW)
-		p.From.Type = obj.TYPE_CONST
-		p.From.Offset = 1
-		p.To.Type = obj.TYPE_REG
-		p.To.Reg = v.Reg()
+			pb := gc.Prog(condOps[v.Op])
+			pb.To.Type = obj.TYPE_BRANCH
 
-		pb := gc.Prog(condOps[v.Op])
-		pb.To.Type = obj.TYPE_BRANCH
+			p = gc.Prog(ppc64.AMOVD)
+			p.From.Type = obj.TYPE_CONST
+			p.From.Offset = 0
+			p.To.Type = obj.TYPE_REG
+			p.To.Reg = v.Reg()
 
-		p = gc.Prog(ppc64.AMOVW)
+			p = gc.Prog(obj.ANOP)
+			gc.Patch(pb, p)
+			break
+		}
+		// Modern PPC uses ISEL
+		p := gc.Prog(ppc64.AMOVD)
 		p.From.Type = obj.TYPE_CONST
-		p.From.Offset = 0
+		p.From.Offset = 1
 		p.To.Type = obj.TYPE_REG
-		p.To.Reg = v.Reg()
-
-		p = gc.Prog(obj.ANOP)
-		gc.Patch(pb, p)
+		p.To.Reg = iselRegs[1]
+		iop := iselOps[v.Op]
+		ssaGenISEL(v, iop.cond, iselRegs[iop.valueIfCond], iselRegs[1-iop.valueIfCond])
 
 	case ssa.OpPPC64FLessEqual, // These include a second branch for EQ -- dealing with NaN prevents REL= to !REL conversion
 		ssa.OpPPC64FGreaterEqual:
 
-		p := gc.Prog(ppc64.AMOVW)
-		p.From.Type = obj.TYPE_CONST
-		p.From.Offset = 1
-		p.To.Type = obj.TYPE_REG
-		p.To.Reg = v.Reg()
+		if v.Block.Func.Config.OldArch {
+			p := gc.Prog(ppc64.AMOVW)
+			p.From.Type = obj.TYPE_CONST
+			p.From.Offset = 1
+			p.To.Type = obj.TYPE_REG
+			p.To.Reg = v.Reg()
 
-		pb0 := gc.Prog(condOps[v.Op])
-		pb0.To.Type = obj.TYPE_BRANCH
-		pb1 := gc.Prog(ppc64.ABEQ)
-		pb1.To.Type = obj.TYPE_BRANCH
+			pb0 := gc.Prog(condOps[v.Op])
+			pb0.To.Type = obj.TYPE_BRANCH
+			pb1 := gc.Prog(ppc64.ABEQ)
+			pb1.To.Type = obj.TYPE_BRANCH
 
-		p = gc.Prog(ppc64.AMOVW)
+			p = gc.Prog(ppc64.AMOVW)
+			p.From.Type = obj.TYPE_CONST
+			p.From.Offset = 0
+			p.To.Type = obj.TYPE_REG
+			p.To.Reg = v.Reg()
+
+			p = gc.Prog(obj.ANOP)
+			gc.Patch(pb0, p)
+			gc.Patch(pb1, p)
+			break
+		}
+		// Modern PPC uses ISEL
+		p := gc.Prog(ppc64.AMOVD)
 		p.From.Type = obj.TYPE_CONST
-		p.From.Offset = 0
+		p.From.Offset = 1
 		p.To.Type = obj.TYPE_REG
-		p.To.Reg = v.Reg()
-
-		p = gc.Prog(obj.ANOP)
-		gc.Patch(pb0, p)
-		gc.Patch(pb1, p)
+		p.To.Reg = iselRegs[1]
+		iop := iselOps[v.Op]
+		ssaGenISEL(v, iop.cond, iselRegs[iop.valueIfCond], iselRegs[1-iop.valueIfCond])
+		ssaGenISEL(v, ppc64.C_COND_EQ, iselRegs[1], v.Reg())
 
 	case ssa.OpPPC64LoweredZero:
 		// Similar to how this is done on ARM,

src/cmd/compile/internal/ssa/config.go

@@ -32,8 +32,9 @@ type Config struct {
 	noDuffDevice    bool                       // Don't use Duff's device
 	nacl            bool                       // GOOS=nacl
 	use387          bool                       // GO386=387
+	OldArch         bool                       // True for older versions of architecture, e.g. true for PPC64BE, false for PPC64LE
 	NeedsFpScratch  bool                       // No direct move between GP and FP register sets
-	DebugTest       bool                       // as a debugging aid for binary search using GOSSAHASH, make buggy new code conditional on this
+	DebugTest       bool                       // default true unless $GOSSAHASH != ""; as a debugging aid, make new code conditional on this and use GOSSAHASH to binary search for failing cases
 	sparsePhiCutoff uint64                     // Sparse phi location algorithm used above this #blocks*#variables score
 	curFunc         *Func
 
@@ -180,7 +181,10 @@ func NewConfig(arch string, fe Frontend, ctxt *obj.Link, optimize bool) *Config
 		c.FPReg = framepointerRegARM64
 		c.hasGReg = true
 		c.noDuffDevice = obj.GOOS == "darwin" // darwin linker cannot handle BR26 reloc with non-zero addend
-	case "ppc64le", "ppc64":
+	case "ppc64":
+		c.OldArch = true
+		fallthrough
+	case "ppc64le":
 		c.IntSize = 8
 		c.PtrSize = 8
 		c.lowerBlock = rewriteBlockPPC64