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[release-branch.go1.21] Revert "cmd/compile: omit redundant sign/unsign extension on arm64"
This reverts CL 427454. Reason for revert: causes incorrect generated code in some rare cases We'll fix-forward at tip, so the revert just needs to be done for 1.21. Fixes #62143 Change-Id: Id242230481ff4d4ba5f58236c6d8237729fc3b80 Reviewed-on: https://go-review.googlesource.com/c/go/+/520976 Run-TryBot: Keith Randall <[email protected]> Reviewed-by: Ruinan Sun <[email protected]> Reviewed-by: Keith Randall <[email protected]> TryBot-Result: Gopher Robot <[email protected]> Reviewed-by: Cherry Mui <[email protected]>
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src/cmd/compile/internal/ssa/_gen/ARM64.rules

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@@ -1571,14 +1571,6 @@
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// zero upper bit of the register; no need to zero-extend
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(MOVBUreg x:((Equal|NotEqual|LessThan|LessThanU|LessThanF|LessEqual|LessEqualU|LessEqualF|GreaterThan|GreaterThanU|GreaterThanF|GreaterEqual|GreaterEqualU|GreaterEqualF) _)) => (MOVDreg x)
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// omit unsign extension
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(MOVWUreg x) && zeroUpper32Bits(x, 3) => x
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// omit sign extension
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(MOVWreg <t> (ANDconst x [c])) && uint64(c) & uint64(0xffffffff80000000) == 0 => (ANDconst <t> x [c])
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(MOVHreg <t> (ANDconst x [c])) && uint64(c) & uint64(0xffffffffffff8000) == 0 => (ANDconst <t> x [c])
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(MOVBreg <t> (ANDconst x [c])) && uint64(c) & uint64(0xffffffffffffff80) == 0 => (ANDconst <t> x [c])
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// absorb flag constants into conditional instructions
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(CSEL [cc] x _ flag) && ccARM64Eval(cc, flag) > 0 => x
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(CSEL [cc] _ y flag) && ccARM64Eval(cc, flag) < 0 => y

src/cmd/compile/internal/ssa/_gen/ARM64Ops.go

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@@ -13,7 +13,6 @@ import "strings"
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// - *const instructions may use a constant larger than the instruction can encode.
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// In this case the assembler expands to multiple instructions and uses tmp
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// register (R27).
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// - All 32-bit Ops will zero the upper 32 bits of the destination register.
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// Suffixes encode the bit width of various instructions.
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// D (double word) = 64 bit

src/cmd/compile/internal/ssa/rewrite.go

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Original file line numberDiff line numberDiff line change
@@ -1281,10 +1281,6 @@ func zeroUpper32Bits(x *Value, depth int) bool {
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OpAMD64SHRL, OpAMD64SHRLconst, OpAMD64SARL, OpAMD64SARLconst,
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OpAMD64SHLL, OpAMD64SHLLconst:
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return true
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case OpARM64REV16W, OpARM64REVW, OpARM64RBITW, OpARM64CLZW, OpARM64EXTRWconst,
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OpARM64MULW, OpARM64MNEGW, OpARM64UDIVW, OpARM64DIVW, OpARM64UMODW,
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OpARM64MADDW, OpARM64MSUBW, OpARM64RORW, OpARM64RORWconst:
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return true
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case OpArg:
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return x.Type.Size() == 4
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case OpPhi, OpSelect0, OpSelect1:

src/cmd/compile/internal/ssa/rewriteARM64.go

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test/codegen/noextend.go

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@@ -6,8 +6,6 @@
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package codegen
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9-
import "math/bits"
10-
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var sval64 [8]int64
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var sval32 [8]int32
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var sval16 [8]int16
@@ -187,95 +185,3 @@ func cmp64(u8 *uint8, x16 *int16, u16 *uint16, x32 *int32, u32 *uint32) bool {
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}
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return false
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}
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// no unsign extension following 32 bits ops
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func noUnsignEXT(t1, t2, t3, t4 uint32, k int64) uint64 {
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var ret uint64
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// arm64:"RORW",-"MOVWU"
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ret += uint64(bits.RotateLeft32(t1, 7))
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// arm64:"MULW",-"MOVWU"
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ret *= uint64(t1 * t2)
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// arm64:"MNEGW",-"MOVWU"
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ret += uint64(-t1 * t3)
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// arm64:"UDIVW",-"MOVWU"
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ret += uint64(t1 / t4)
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// arm64:-"MOVWU"
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ret += uint64(t2 % t3)
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// arm64:"MSUBW",-"MOVWU"
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ret += uint64(t1 - t2*t3)
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// arm64:"MADDW",-"MOVWU"
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ret += uint64(t3*t4 + t2)
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// arm64:"REVW",-"MOVWU"
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ret += uint64(bits.ReverseBytes32(t1))
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// arm64:"RBITW",-"MOVWU"
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ret += uint64(bits.Reverse32(t1))
222-
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// arm64:"CLZW",-"MOVWU"
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ret += uint64(bits.LeadingZeros32(t1))
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// arm64:"REV16W",-"MOVWU"
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ret += uint64(((t1 & 0xff00ff00) >> 8) | ((t1 & 0x00ff00ff) << 8))
228-
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// arm64:"EXTRW",-"MOVWU"
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ret += uint64((t1 << 25) | (t2 >> 7))
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return ret
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}
234-
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// no sign extension when the upper bits of the result are zero
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func noSignEXT(x int) int64 {
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t1 := int32(x)
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var ret int64
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// arm64:-"MOVW"
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ret += int64(t1 & 1)
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// arm64:-"MOVW"
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ret += int64(int32(x & 0x7fffffff))
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// arm64:-"MOVH"
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ret += int64(int16(x & 0x7fff))
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// arm64:-"MOVB"
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ret += int64(int8(x & 0x7f))
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return ret
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}
256-
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// corner cases that sign extension must not be omitted
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func shouldSignEXT(x int) int64 {
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t1 := int32(x)
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var ret int64
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// arm64:"MOVW"
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ret += int64(t1 & (-1))
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// arm64:"MOVW"
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ret += int64(int32(x & 0x80000000))
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// arm64:"MOVW"
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ret += int64(int32(x & 0x1100000011111111))
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// arm64:"MOVH"
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ret += int64(int16(x & 0x1100000000001111))
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276-
// arm64:"MOVB"
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ret += int64(int8(x & 0x1100000000000011))
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return ret
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}

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