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cmd/compile: MOVBload and MOVBQZXload are the same op
No need to have both ops when they do the same thing. Just declare MOVBload to zero extend and we can get rid of MOVBQZXload. Same for W and L. Kind of a followon cleanup for https://go-review.googlesource.com/c/19506/ Should enable an easier fix for #14920 Change-Id: I7cfac909a8ba387f433a6ae75c050740ebb34d42 Reviewed-on: https://go-review.googlesource.com/21004 Run-TryBot: Keith Randall <[email protected]> TryBot-Result: Gobot Gobot <[email protected]> Reviewed-by: Brad Fitzpatrick <[email protected]>
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5 files changed

+133
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‎src/cmd/compile/internal/amd64/ssa.go

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -660,7 +660,7 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
660660
p.From.Val = math.Float64frombits(uint64(v.AuxInt))
661661
p.To.Type = obj.TYPE_REG
662662
p.To.Reg = x
663-
case ssa.OpAMD64MOVQload, ssa.OpAMD64MOVSSload, ssa.OpAMD64MOVSDload, ssa.OpAMD64MOVLload, ssa.OpAMD64MOVWload, ssa.OpAMD64MOVBload, ssa.OpAMD64MOVBQSXload, ssa.OpAMD64MOVBQZXload, ssa.OpAMD64MOVWQSXload, ssa.OpAMD64MOVWQZXload, ssa.OpAMD64MOVLQSXload, ssa.OpAMD64MOVLQZXload, ssa.OpAMD64MOVOload:
663+
case ssa.OpAMD64MOVQload, ssa.OpAMD64MOVSSload, ssa.OpAMD64MOVSDload, ssa.OpAMD64MOVLload, ssa.OpAMD64MOVWload, ssa.OpAMD64MOVBload, ssa.OpAMD64MOVBQSXload, ssa.OpAMD64MOVWQSXload, ssa.OpAMD64MOVLQSXload, ssa.OpAMD64MOVOload:
664664
p := gc.Prog(v.Op.Asm())
665665
p.From.Type = obj.TYPE_MEM
666666
p.From.Reg = gc.SSARegNum(v.Args[0])
@@ -1044,8 +1044,7 @@ func ssaGenValue(s *gc.SSAGenState, v *ssa.Value) {
10441044
switch w.Op {
10451045
case ssa.OpAMD64MOVQload, ssa.OpAMD64MOVLload, ssa.OpAMD64MOVWload, ssa.OpAMD64MOVBload,
10461046
ssa.OpAMD64MOVQstore, ssa.OpAMD64MOVLstore, ssa.OpAMD64MOVWstore, ssa.OpAMD64MOVBstore,
1047-
ssa.OpAMD64MOVBQSXload, ssa.OpAMD64MOVBQZXload, ssa.OpAMD64MOVWQSXload,
1048-
ssa.OpAMD64MOVWQZXload, ssa.OpAMD64MOVLQSXload, ssa.OpAMD64MOVLQZXload,
1047+
ssa.OpAMD64MOVBQSXload, ssa.OpAMD64MOVWQSXload, ssa.OpAMD64MOVLQSXload,
10491048
ssa.OpAMD64MOVSSload, ssa.OpAMD64MOVSDload, ssa.OpAMD64MOVOload,
10501049
ssa.OpAMD64MOVSSstore, ssa.OpAMD64MOVSDstore, ssa.OpAMD64MOVOstore:
10511050
if w.Args[0] == v.Args[0] && w.Aux == nil && w.AuxInt >= 0 && w.AuxInt < minZeroPage {

‎src/cmd/compile/internal/ssa/gen/AMD64.rules

Lines changed: 21 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -619,11 +619,15 @@
619619
// This prevents a single load from being split into multiple loads
620620
// which then might return different values. See test/atomicload.go.
621621
(MOVBQSX x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 -> @x.Block (MOVBQSXload <v.Type> [off] {sym} ptr mem)
622-
(MOVBQZX x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 -> @x.Block (MOVBQZXload <v.Type> [off] {sym} ptr mem)
622+
(MOVBQZX x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 -> @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
623623
(MOVWQSX x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 -> @x.Block (MOVWQSXload <v.Type> [off] {sym} ptr mem)
624-
(MOVWQZX x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 -> @x.Block (MOVWQZXload <v.Type> [off] {sym} ptr mem)
624+
(MOVWQZX x:(MOVWload [off] {sym} ptr mem)) && x.Uses == 1 -> @x.Block (MOVWload <v.Type> [off] {sym} ptr mem)
625625
(MOVLQSX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 -> @x.Block (MOVLQSXload <v.Type> [off] {sym} ptr mem)
626-
(MOVLQZX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 -> @x.Block (MOVLQZXload <v.Type> [off] {sym} ptr mem)
626+
(MOVLQZX x:(MOVLload [off] {sym} ptr mem)) && x.Uses == 1 -> @x.Block (MOVLload <v.Type> [off] {sym} ptr mem)
627+
628+
(MOVBQZX x:(MOVBloadidx1 [off] {sym} ptr idx mem)) && x.Uses == 1 -> @x.Block (MOVBloadidx1 <v.Type> [off] {sym} ptr idx mem)
629+
(MOVWQZX x:(MOVWloadidx2 [off] {sym} ptr idx mem)) && x.Uses == 1 -> @x.Block (MOVWloadidx2 <v.Type> [off] {sym} ptr idx mem)
630+
(MOVLQZX x:(MOVLloadidx4 [off] {sym} ptr idx mem)) && x.Uses == 1 -> @x.Block (MOVLloadidx4 <v.Type> [off] {sym} ptr idx mem)
627631

628632
// replace load from same location as preceding store with copy
629633
(MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> x
@@ -705,12 +709,6 @@
705709
(MOVOload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
706710
(MOVOload [off1+off2] {mergeSym(sym1,sym2)} base mem)
707711

708-
(MOVBQZXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
709-
(MOVBQZXload [off1+off2] {mergeSym(sym1,sym2)} base mem)
710-
(MOVWQZXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
711-
(MOVWQZXload [off1+off2] {mergeSym(sym1,sym2)} base mem)
712-
(MOVLQZXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
713-
(MOVLQZXload [off1+off2] {mergeSym(sym1,sym2)} base mem)
714712
(MOVBQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
715713
(MOVBQSXload [off1+off2] {mergeSym(sym1,sym2)} base mem)
716714
(MOVWQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem) && is32Bit(off1+off2) && canMergeSym(sym1, sym2) ->
@@ -1197,21 +1195,21 @@
11971195
// Combining byte loads into larger (unaligned) loads.
11981196
// There are many ways these combinations could occur. This is
11991197
// designed to match the way encoding/binary.LittleEndian does it.
1200-
(ORW x:(MOVBQZXload [i] {s} p mem)
1201-
(SHLWconst [8] (MOVBQZXload [i+1] {s} p mem))) -> @x.Block (MOVWload [i] {s} p mem)
1198+
(ORW x:(MOVBload [i] {s} p mem)
1199+
(SHLWconst [8] (MOVBload [i+1] {s} p mem))) -> @x.Block (MOVWload [i] {s} p mem)
12021200

12031201
(ORL (ORL (ORL
1204-
x:(MOVBQZXload [i] {s} p mem)
1205-
(SHLLconst [8] (MOVBQZXload [i+1] {s} p mem)))
1206-
(SHLLconst [16] (MOVBQZXload [i+2] {s} p mem)))
1207-
(SHLLconst [24] (MOVBQZXload [i+3] {s} p mem))) -> @x.Block (MOVLload [i] {s} p mem)
1202+
x:(MOVBload [i] {s} p mem)
1203+
(SHLLconst [8] (MOVBload [i+1] {s} p mem)))
1204+
(SHLLconst [16] (MOVBload [i+2] {s} p mem)))
1205+
(SHLLconst [24] (MOVBload [i+3] {s} p mem))) -> @x.Block (MOVLload [i] {s} p mem)
12081206

12091207
(ORQ (ORQ (ORQ (ORQ (ORQ (ORQ (ORQ
1210-
x:(MOVBQZXload [i] {s} p mem)
1211-
(SHLQconst [8] (MOVBQZXload [i+1] {s} p mem)))
1212-
(SHLQconst [16] (MOVBQZXload [i+2] {s} p mem)))
1213-
(SHLQconst [24] (MOVBQZXload [i+3] {s} p mem)))
1214-
(SHLQconst [32] (MOVBQZXload [i+4] {s} p mem)))
1215-
(SHLQconst [40] (MOVBQZXload [i+5] {s} p mem)))
1216-
(SHLQconst [48] (MOVBQZXload [i+6] {s} p mem)))
1217-
(SHLQconst [56] (MOVBQZXload [i+7] {s} p mem))) -> @x.Block (MOVQload [i] {s} p mem)
1208+
x:(MOVBload [i] {s} p mem)
1209+
(SHLQconst [8] (MOVBload [i+1] {s} p mem)))
1210+
(SHLQconst [16] (MOVBload [i+2] {s} p mem)))
1211+
(SHLQconst [24] (MOVBload [i+3] {s} p mem)))
1212+
(SHLQconst [32] (MOVBload [i+4] {s} p mem)))
1213+
(SHLQconst [40] (MOVBload [i+5] {s} p mem)))
1214+
(SHLQconst [48] (MOVBload [i+6] {s} p mem)))
1215+
(SHLQconst [56] (MOVBload [i+7] {s} p mem))) -> @x.Block (MOVQload [i] {s} p mem)

‎src/cmd/compile/internal/ssa/gen/AMD64Ops.go

Lines changed: 6 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -367,15 +367,12 @@ func init() {
367367
// Note: LEAQ{1,2,4,8} must not have OpSB as either argument.
368368

369369
// auxint+aux == add auxint and the offset of the symbol in aux (if any) to the effective address
370-
{name: "MOVBload", argLength: 2, reg: gpload, asm: "MOVBLZX", aux: "SymOff", typ: "UInt8"}, // load byte from arg0+auxint+aux. arg1=mem
371-
{name: "MOVBQSXload", argLength: 2, reg: gpload, asm: "MOVBQSX", aux: "SymOff"}, // ditto, extend to int64
372-
{name: "MOVBQZXload", argLength: 2, reg: gpload, asm: "MOVBLZX", aux: "SymOff"}, // ditto, extend to uint64
373-
{name: "MOVWload", argLength: 2, reg: gpload, asm: "MOVWLZX", aux: "SymOff", typ: "UInt16"}, // load 2 bytes from arg0+auxint+aux. arg1=mem
374-
{name: "MOVWQSXload", argLength: 2, reg: gpload, asm: "MOVWQSX", aux: "SymOff"}, // ditto, extend to int64
375-
{name: "MOVWQZXload", argLength: 2, reg: gpload, asm: "MOVWLZX", aux: "SymOff"}, // ditto, extend to uint64
376-
{name: "MOVLload", argLength: 2, reg: gpload, asm: "MOVL", aux: "SymOff", typ: "UInt32"}, // load 4 bytes from arg0+auxint+aux. arg1=mem
377-
{name: "MOVLQSXload", argLength: 2, reg: gpload, asm: "MOVLQSX", aux: "SymOff"}, // ditto, extend to int64
378-
{name: "MOVLQZXload", argLength: 2, reg: gpload, asm: "MOVL", aux: "SymOff"}, // ditto, extend to uint64
370+
{name: "MOVBload", argLength: 2, reg: gpload, asm: "MOVBLZX", aux: "SymOff", typ: "UInt8"}, // load byte from arg0+auxint+aux. arg1=mem. Zero extend.
371+
{name: "MOVBQSXload", argLength: 2, reg: gpload, asm: "MOVBQSX", aux: "SymOff"}, // ditto, sign extend to int64
372+
{name: "MOVWload", argLength: 2, reg: gpload, asm: "MOVWLZX", aux: "SymOff", typ: "UInt16"}, // load 2 bytes from arg0+auxint+aux. arg1=mem. Zero extend.
373+
{name: "MOVWQSXload", argLength: 2, reg: gpload, asm: "MOVWQSX", aux: "SymOff"}, // ditto, sign extend to int64
374+
{name: "MOVLload", argLength: 2, reg: gpload, asm: "MOVL", aux: "SymOff", typ: "UInt32"}, // load 4 bytes from arg0+auxint+aux. arg1=mem. Zero extend.
375+
{name: "MOVLQSXload", argLength: 2, reg: gpload, asm: "MOVLQSX", aux: "SymOff"}, // ditto, sign extend to int64
379376
{name: "MOVQload", argLength: 2, reg: gpload, asm: "MOVQ", aux: "SymOff", typ: "UInt64"}, // load 8 bytes from arg0+auxint+aux. arg1=mem
380377
{name: "MOVBstore", argLength: 3, reg: gpstore, asm: "MOVB", aux: "SymOff", typ: "Mem"}, // store byte in arg1 to arg0+auxint+aux. arg2=mem
381378
{name: "MOVWstore", argLength: 3, reg: gpstore, asm: "MOVW", aux: "SymOff", typ: "Mem"}, // store 2 bytes in arg1 to arg0+auxint+aux. arg2=mem

‎src/cmd/compile/internal/ssa/opGen.go

Lines changed: 0 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -261,13 +261,10 @@ const (
261261
OpAMD64LEAQ8
262262
OpAMD64MOVBload
263263
OpAMD64MOVBQSXload
264-
OpAMD64MOVBQZXload
265264
OpAMD64MOVWload
266265
OpAMD64MOVWQSXload
267-
OpAMD64MOVWQZXload
268266
OpAMD64MOVLload
269267
OpAMD64MOVLQSXload
270-
OpAMD64MOVLQZXload
271268
OpAMD64MOVQload
272269
OpAMD64MOVBstore
273270
OpAMD64MOVWstore
@@ -3393,20 +3390,6 @@ var opcodeTable = [...]opInfo{
33933390
},
33943391
},
33953392
},
3396-
{
3397-
name: "MOVBQZXload",
3398-
auxType: auxSymOff,
3399-
argLen: 2,
3400-
asm: x86.AMOVBLZX,
3401-
reg: regInfo{
3402-
inputs: []inputInfo{
3403-
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3404-
},
3405-
outputs: []regMask{
3406-
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3407-
},
3408-
},
3409-
},
34103393
{
34113394
name: "MOVWload",
34123395
auxType: auxSymOff,
@@ -3435,20 +3418,6 @@ var opcodeTable = [...]opInfo{
34353418
},
34363419
},
34373420
},
3438-
{
3439-
name: "MOVWQZXload",
3440-
auxType: auxSymOff,
3441-
argLen: 2,
3442-
asm: x86.AMOVWLZX,
3443-
reg: regInfo{
3444-
inputs: []inputInfo{
3445-
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3446-
},
3447-
outputs: []regMask{
3448-
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3449-
},
3450-
},
3451-
},
34523421
{
34533422
name: "MOVLload",
34543423
auxType: auxSymOff,
@@ -3477,20 +3446,6 @@ var opcodeTable = [...]opInfo{
34773446
},
34783447
},
34793448
},
3480-
{
3481-
name: "MOVLQZXload",
3482-
auxType: auxSymOff,
3483-
argLen: 2,
3484-
asm: x86.AMOVL,
3485-
reg: regInfo{
3486-
inputs: []inputInfo{
3487-
{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R14 R15 SB
3488-
},
3489-
outputs: []regMask{
3490-
65519, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R14 R15
3491-
},
3492-
},
3493-
},
34943449
{
34953450
name: "MOVQload",
34963451
auxType: auxSymOff,

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